/* Opcode table for the ARC.
- Copyright (C) 1994-2016 Free Software Foundation, Inc.
+ Copyright (C) 1994-2021 Free Software Foundation, Inc.
Contributed by Claudiu Zissulescu (claziss@synopsys.com)
#include "libiberty.h"
/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
- instructions. Support for this target is available when binutils is
- configured and built for the 'arc*-mellanox-*-*' target. As far as
- possible all ARC NPS400 features are built into all ARC target builds as
+ instructions. All NPS400 features are built into all ARC target builds as
this reduces the chances that regressions might creep in. */
+/* Insert RA register into a 32-bit opcode, with checks. */
+
+static unsigned long long
+insert_ra_chk (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | (value & 0x3F);
+}
+
/* Insert RB register into a 32-bit opcode. */
-static unsigned
-insert_rb (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+
+static unsigned long long
+insert_rb (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
}
-static int
-extract_rb (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+/* Insert RB register with checks. */
+
+static unsigned long long
+insert_rb_chk (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
+static long long
+extract_rb (unsigned long long insn,
+ bfd_boolean * invalid)
{
int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
return value;
}
-static unsigned
-insert_rad (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_rad (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value & 0x01)
- *errmsg = _("Improper register value.");
+ *errmsg = _("cannot use odd number destination register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
return insn | (value & 0x3F);
}
-static unsigned
-insert_rcd (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_rcd (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value & 0x01)
- *errmsg = _("Improper register value.");
+ *errmsg = _("cannot use odd number source register");
return insn | ((value & 0x3F) << 6);
}
+static unsigned long long
+insert_rbd (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ if (value & 0x01)
+ *errmsg = _("cannot use odd number source register");
+ if (value == 60)
+ *errmsg = _("LP_COUNT register cannot be used as destination register");
+
+ return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
+}
+
/* Dummy insert ZERO operand function. */
-static unsigned
-insert_za (unsigned insn,
- int value,
- const char **errmsg)
+static unsigned long long
+insert_za (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value)
*errmsg = _("operand is not zero");
/* Insert Y-bit in bbit/br instructions. This function is called only
when solving fixups. */
-static unsigned
-insert_Ybit (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_Ybit (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
if (value > 0)
insn |= 0x08;
/* Insert Y-bit in bbit/br instructions. This function is called only
when solving fixups. */
-static unsigned
-insert_NYbit (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_NYbit (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
if (value < 0)
insn |= 0x08;
/* Insert H register into a 16-bit opcode. */
-static unsigned
-insert_rhv1 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_rhv1 (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
}
-static int
-extract_rhv1 (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_rhv1 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- int value = 0;
+ int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
return value;
}
/* Insert H register into a 16-bit opcode. */
-static unsigned
-insert_rhv2 (unsigned insn,
- int value,
- const char **errmsg)
+static unsigned long long
+insert_rhv2 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value == 0x1E)
- *errmsg =
- _("Register R30 is a limm indicator for this type of instruction.");
+ *errmsg = _("register R30 is a limm indicator");
+ else if (value < 0 || value > 31)
+ *errmsg = _("register out of range");
return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
}
-static int
-extract_rhv2 (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_rhv2 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
return value;
}
-static unsigned
-insert_r0 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_r0 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 0)
- *errmsg = _("Register must be R0.");
+ *errmsg = _("register must be R0");
return insn;
}
-static int
-extract_r0 (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 0;
}
-static unsigned
-insert_r1 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_r1 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 1)
- *errmsg = _("Register must be R1.");
+ *errmsg = _("register must be R1");
return insn;
}
-static int
-extract_r1 (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 1;
}
-static unsigned
-insert_r2 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_r2 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 2)
- *errmsg = _("Register must be R2.");
+ *errmsg = _("register must be R2");
return insn;
}
-static int
-extract_r2 (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 2;
}
-static unsigned
-insert_r3 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_r3 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 3)
- *errmsg = _("Register must be R3.");
+ *errmsg = _("register must be R3");
return insn;
}
-static int
-extract_r3 (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 3;
}
-static unsigned
-insert_sp (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_sp (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 28)
- *errmsg = _("Register must be SP.");
+ *errmsg = _("register must be SP");
return insn;
}
-static int
-extract_sp (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 28;
}
-static unsigned
-insert_gp (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_gp (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 26)
- *errmsg = _("Register must be GP.");
+ *errmsg = _("register must be GP");
return insn;
}
-static int
-extract_gp (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 26;
}
-static unsigned
-insert_pcl (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_pcl (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 63)
- *errmsg = _("Register must be PCL.");
+ *errmsg = _("register must be PCL");
return insn;
}
-static int
-extract_pcl (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 63;
}
-static unsigned
-insert_blink (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_blink (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 31)
- *errmsg = _("Register must be BLINK.");
+ *errmsg = _("register must be BLINK");
return insn;
}
-static int
-extract_blink (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 31;
}
-static unsigned
-insert_ilink1 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_ilink1 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 29)
- *errmsg = _("Register must be ILINK1.");
+ *errmsg = _("register must be ILINK1");
return insn;
}
-static int
-extract_ilink1 (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 29;
}
-static unsigned
-insert_ilink2 (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_ilink2 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 30)
- *errmsg = _("Register must be ILINK2.");
+ *errmsg = _("register must be ILINK2");
return insn;
}
-static int
-extract_ilink2 (unsigned insn ATTRIBUTE_UNUSED,
+static long long
+extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return 30;
}
-static unsigned
-insert_ras (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_ras (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
switch (value)
{
insn |= (value - 8);
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ *errmsg = _("register must be either r0-r3 or r12-r15");
break;
}
return insn;
}
-static int
-extract_ras (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_ras (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
int value = insn & 0x07;
+
if (value > 3)
return (value + 8);
else
return value;
}
-static unsigned
-insert_rbs (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_rbs (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
switch (value)
{
insn |= ((value - 8)) << 8;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ *errmsg = _("register must be either r0-r3 or r12-r15");
break;
}
return insn;
}
-static int
-extract_rbs (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_rbs (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 8) & 0x07;
+
if (value > 3)
return (value + 8);
else
return value;
}
-static unsigned
-insert_rcs (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_rcs (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
switch (value)
{
insn |= ((value - 8)) << 5;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ *errmsg = _("register must be either r0-r3 or r12-r15");
break;
}
return insn;
}
-static int
-extract_rcs (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_rcs (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 5) & 0x07;
+
if (value > 3)
return (value + 8);
else
return value;
}
-static unsigned
-insert_simm3s (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_simm3s (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
int tmp = 0;
switch (value)
tmp = 0x06;
break;
default:
- *errmsg = _("Accepted values are from -1 to 6.");
+ *errmsg = _("accepted values are from -1 to 6");
break;
}
return insn;
}
-static int
-extract_simm3s (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_simm3s (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
int value = (insn >> 8) & 0x07;
+
if (value == 7)
return -1;
else
return value;
}
-static unsigned
-insert_rrange (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_rrange (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
int reg1 = (value >> 16) & 0xFFFF;
int reg2 = value & 0xFFFF;
+
if (reg1 != 13)
- {
- *errmsg = _("First register of the range should be r13.");
- return insn;
- }
- if (reg2 < 13 || reg2 > 26)
- {
- *errmsg = _("Last register of the range doesn't fit.");
- return insn;
- }
- insn |= ((reg2 - 12) & 0x0F) << 1;
+ *errmsg = _("first register of the range should be r13");
+ else if (reg2 < 13 || reg2 > 26)
+ *errmsg = _("last register of the range doesn't fit");
+ else
+ insn |= ((reg2 - 12) & 0x0F) << 1;
return insn;
}
-static int
-extract_rrange (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_rrange (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return (insn >> 1) & 0x0F;
}
-static unsigned
-insert_fpel (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_r13el (unsigned long long insn,
+ long long int value,
+ const char **errmsg)
+{
+ if (value != 13)
+ {
+ *errmsg = _("invalid register number, should be fp");
+ return insn;
+ }
+
+ insn |= 0x02;
+ return insn;
+}
+
+static unsigned long long
+insert_fpel (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 27)
{
- *errmsg = _("Invalid register number, should be fp.");
+ *errmsg = _("invalid register number, should be fp");
return insn;
}
return insn;
}
-static int
-extract_fpel (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_fpel (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x0100) ? 27 : -1;
}
-static unsigned
-insert_blinkel (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_blinkel (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 31)
{
- *errmsg = _("Invalid register number, should be blink.");
+ *errmsg = _("invalid register number, should be blink");
return insn;
}
return insn;
}
-static int
-extract_blinkel (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_blinkel (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x0200) ? 31 : -1;
}
-static unsigned
-insert_pclel (unsigned insn,
- int value,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_pclel (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
if (value != 63)
{
- *errmsg = _("Invalid register number, should be pcl.");
+ *errmsg = _("invalid register number, should be pcl");
return insn;
}
return insn;
}
-static int
-extract_pclel (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_pclel (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
return (insn & 0x0400) ? 63 : -1;
}
#define INSERT_W6
+
/* mask = 00000000000000000000111111000000
insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
-static unsigned
-insert_w6 (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+
+static unsigned long long
+insert_w6 (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
insn |= ((value >> 0) & 0x003f) << 6;
}
#define EXTRACT_W6
+
/* mask = 00000000000000000000111111000000. */
-static int
-extract_w6 (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+
+static long long
+extract_w6 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- unsigned value = 0;
+ int value = 0;
value |= ((insn >> 6) & 0x003f) << 0;
+ /* Extend the sign. */
+ int signbit = 1 << 5;
+ value = (value ^ signbit) - signbit;
+
return value;
}
#define INSERT_G_S
+
/* mask = 0000011100022000
insn = 01000ggghhhGG0HH. */
-static unsigned
-insert_g_s (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+
+static unsigned long long
+insert_g_s (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
insn |= ((value >> 0) & 0x0007) << 8;
insn |= ((value >> 3) & 0x0003) << 3;
}
#define EXTRACT_G_S
+
/* mask = 0000011100022000. */
-static int
-extract_g_s (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+
+static long long
+extract_g_s (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
int value = 0;
+ int signbit = 1 << (6 - 1);
value |= ((insn >> 8) & 0x0007) << 0;
value |= ((insn >> 3) & 0x0003) << 3;
/* Extend the sign. */
- int signbit = 1 << (6 - 1);
value = (value ^ signbit) - signbit;
return value;
}
/* ARC NPS400 Support: See comment near head of file. */
-static unsigned
-insert_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
+static unsigned long long \
+insert_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ long long value, \
+ const char ** errmsg) \
+{ \
+ switch (value) \
+ { \
+ case 0: \
+ case 1: \
+ case 2: \
+ case 3: \
+ insn |= value << (OFFSET); \
+ break; \
+ case 12: \
+ case 13: \
+ case 14: \
+ case 15: \
+ insn |= (value - 8) << (OFFSET); \
+ break; \
+ default: \
+ *errmsg = _("register must be either r0-r3 or r12-r15"); \
+ break; \
+ } \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_3bit_reg_at_##OFFSET##_##NAME \
+ (unsigned long long insn, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ int value = (insn >> (OFFSET)) & 0x07; \
+ if (value > 3) \
+ value += 8; \
+ return value; \
+} \
+
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
+
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
+MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
+
+static unsigned long long
+insert_nps_bitop_size_2b (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
switch (value)
{
- case 0:
case 1:
+ value = 0;
+ break;
case 2:
- case 3:
- insn |= value << 24;
+ value = 1;
break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= (value - 8) << 24;
+ case 4:
+ value = 2;
+ break;
+ case 8:
+ value = 3;
break;
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
+ value = 0;
+ *errmsg = _("invalid size, should be 1, 2, 4, or 8");
break;
}
+
+ insn |= value << 10;
return insn;
}
-static int
-extract_nps_3bit_dst (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_nps_bitop_size_2b (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- int value = (insn >> 24) & 0x07;
- if (value > 3)
- return (value + 8);
- else
- return value;
+ return 1 << ((insn >> 10) & 0x3);
}
-static unsigned
-insert_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_nps_bitop_uimm8 (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value >> 5) & 7) << 12;
+ insn |= (value & 0x1f);
+ return insn;
+}
+
+static long long
+extract_nps_bitop_uimm8 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
+}
+
+static unsigned long long
+insert_nps_rflt_uimm6 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
switch (value)
{
- case 0:
case 1:
case 2:
- case 3:
- insn |= value << 21;
- break;
- case 12:
- case 13:
- case 14:
- case 15:
- insn |= (value - 8) << 21;
+ case 4:
break;
+
default:
- *errmsg = _("Register must be either r0-r3 or r12-r15.");
- break;
+ *errmsg = _("invalid immediate, must be 1, 2, or 4");
+ value = 0;
}
+
+ insn |= (value << 6);
return insn;
}
-static int
-extract_nps_3bit_src2 (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_nps_rflt_uimm6 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- int value = (insn >> 21) & 0x07;
- if (value > 3)
- return (value + 8);
- else
- return value;
+ return (insn >> 6) & 0x3f;
+}
+
+static unsigned long long
+insert_nps_dst_pos_and_size (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
+ return insn;
}
-static unsigned
-insert_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+static long long
+extract_nps_dst_pos_and_size (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- if (value < 1 || value > 32)
+ return (insn & 0x1f);
+}
+
+static unsigned long long
+insert_nps_cmem_uimm16 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ int top = (value >> 16) & 0xffff;
+
+ if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
+ *errmsg = _("invalid value for CMEM ld/st immediate");
+ insn |= (value & 0xffff);
+ return insn;
+}
+
+static long long
+extract_nps_cmem_uimm16 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
+}
+
+static unsigned long long
+insert_nps_imm_offset (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ switch (value)
{
- *errmsg = _("Invalid bit size, should be between 1 and 32 inclusive.");
- return insn;
+ case 0:
+ case 16:
+ case 32:
+ case 48:
+ case 64:
+ value = value >> 4;
+ break;
+ default:
+ *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
+ value = 0;
}
-
- --value;
- insn |= ((value & 0x1f) << 10);
+ insn |= (value << 10);
return insn;
}
-static int
-extract_nps_bitop_size (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_nps_imm_offset (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- return ((insn >> 10) & 0x1f) + 1;
+ return ((insn >> 10) & 0x7) * 16;
}
-static unsigned
-insert_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_nps_imm_entry (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
switch (value)
{
- case 1:
+ case 16:
value = 0;
break;
- case 2:
+ case 32:
value = 1;
break;
- case 4:
+ case 64:
value = 2;
break;
- case 8:
- value = 3;
- break;
+ case 128:
+ value = 3;
+ break;
default:
+ *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
value = 0;
- *errmsg = _("Invalid size, should be 1, 2, 4, or 8.");
- break;
}
-
- insn |= value << 10;
+ insn |= (value << 2);
return insn;
}
-static int
-extract_nps_bitop_size_2b (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_nps_imm_entry (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- return 1 << ((insn >> 10) & 0x3);
+ int imm_entry = ((insn >> 2) & 0x7);
+ return (1 << (imm_entry + 4));
}
-static unsigned
-insert_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_nps_size_16bit (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
- insn |= ((value >> 5) & 7) << 12;
- insn |= (value & 0x1f);
+ if ((value < 1) || (value > 64))
+ {
+ *errmsg = _("invalid size value must be on range 1-64.");
+ value = 0;
+ }
+ value = value & 0x3f;
+ insn |= (value << 6);
return insn;
}
-static int
-extract_nps_bitop_uimm8 (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_nps_size_16bit (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
+}
+
+
+#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
+static unsigned long long \
+insert_nps_##NAME##_pos (unsigned long long insn, \
+ long long value, \
+ const char ** errmsg) \
+{ \
+ switch (value) \
+ { \
+ case 0: \
+ case 8: \
+ case 16: \
+ case 24: \
+ value = value / 8; \
+ break; \
+ default: \
+ *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
+ value = 0; \
+ } \
+ insn |= (value << SHIFT); \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_##NAME##_pos (unsigned long long insn, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ((insn >> SHIFT) & 0x3) * 8; \
+}
+
+MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
+MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
+
+#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char ** errmsg) \
+ { \
+ if (value < LOWER || value > UPPER) \
+ { \
+ *errmsg = _("invalid size, value must be " \
+ #LOWER " to " #UPPER "."); \
+ return insn; \
+ } \
+ value -= BIAS; \
+ insn |= (value << SHIFT); \
+ return insn; \
+ } \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
+}
+
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
+MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
+
+static long long
+extract_nps_qcmp_m3 (unsigned long long insn,
+ bfd_boolean * invalid)
+{
+ int m3 = (insn >> 5) & 0xf;
+ if (m3 == 0xf)
+ *invalid = TRUE;
+ return m3;
+}
+
+static long long
+extract_nps_qcmp_m2 (unsigned long long insn,
+ bfd_boolean * invalid)
+{
+ bfd_boolean tmp_invalid = FALSE;
+ int m2 = (insn >> 15) & 0x1;
+ int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
+
+ if (m2 == 0 && m3 == 0xf)
+ *invalid = TRUE;
+ return m2;
+}
+
+static long long
+extract_nps_qcmp_m1 (unsigned long long insn,
+ bfd_boolean * invalid)
+{
+ bfd_boolean tmp_invalid = FALSE;
+ int m1 = (insn >> 14) & 0x1;
+ int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
+ int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
+
+ if (m1 == 0 && m2 == 0 && m3 == 0xf)
+ *invalid = TRUE;
+ return m1;
+}
+
+static unsigned long long
+insert_nps_calc_entry_size (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ unsigned pwr;
+
+ if (value < 1 || value > 256)
+ {
+ *errmsg = _("value out of range 1 - 256");
+ return 0;
+ }
+
+ for (pwr = 0; (value & 1) == 0; value >>= 1)
+ ++pwr;
+
+ if (value != 1)
+ {
+ *errmsg = _("value must be power of 2");
+ return 0;
+ }
+
+ return insn | (pwr << 8);
+}
+
+static long long
+extract_nps_calc_entry_size (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
+ unsigned entry_size = (insn >> 8) & 0xf;
+ return 1 << entry_size;
}
-static unsigned
-insert_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_nps_bitop_mod4 (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
{
- switch (value)
- {
- case 1:
- case 2:
- case 4:
- break;
+ return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
+}
- default:
- *errmsg = _("invalid immediate, must be 1, 2, or 4");
- value = 0;
- }
+static long long
+extract_nps_bitop_mod4 (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
+}
- insn |= (value << 6);
- return insn;
+static unsigned long long
+insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ long long value,
+ const char ** errmsg ATTRIBUTE_UNUSED)
+{
+ return insn | (value << 42) | (value << 37);
}
-static int
-extract_nps_rflt_uimm6 (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long
+extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
+ bfd_boolean * invalid)
{
- return (insn >> 6) & 0x3f;
+ if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
+ *invalid = TRUE;
+ return ((insn >> 37) & 0x1f);
}
-static unsigned
-insert_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
- int value ATTRIBUTE_UNUSED,
- const char **errmsg ATTRIBUTE_UNUSED)
+static unsigned long long
+insert_nps_bitop_ins_ext (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
{
- insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
+ if (value < 0 || value > 28)
+ *errmsg = _("value must be in the range 0 to 28");
+ return insn | (value << 20);
+}
+
+static long long
+extract_nps_bitop_ins_ext (unsigned long long insn,
+ bfd_boolean * invalid)
+{
+ int value = (insn >> 20) & 0x1f;
+
+ if (value > 28)
+ *invalid = TRUE;
+ return value;
+}
+
+#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char ** errmsg) \
+{ \
+ if (value < 1 || value > UPPER) \
+ *errmsg = _("value must be in the range 1 to " #UPPER); \
+ if (value == UPPER) \
+ value = 0; \
+ return insn | (value << SHIFT); \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
+ if (value == 0) \
+ value = UPPER; \
+ return value; \
+}
+
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
+MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
+
+static unsigned long long
+insert_nps_min_hofs (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ if (value < 0 || value > 240)
+ *errmsg = _("value must be in the range 0 to 240");
+ if ((value % 16) != 0)
+ *errmsg = _("value must be a multiple of 16");
+ value = value / 16;
+ return insn | (value << 6);
+}
+
+static long long
+extract_nps_min_hofs (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = (insn >> 6) & 0xF;
+ return value * 16;
+}
+
+#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
+static unsigned long long \
+insert_nps_##NAME (unsigned long long insn, \
+ long long value, \
+ const char ** errmsg) \
+{ \
+ if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
+ *errmsg = _("invalid address type for operand"); \
+ return insn; \
+} \
+ \
+static long long \
+extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
+ bfd_boolean * invalid ATTRIBUTE_UNUSED) \
+{ \
+ return ARC_NPS400_ADDRTYPE_##VALUE; \
+}
+
+MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
+MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
+MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
+MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
+MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
+MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
+MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
+MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
+MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
+MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
+MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
+MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
+MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
+MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
+MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
+MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
+
+static unsigned long long
+insert_nps_rbdouble_64 (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ if (value < 0 || value > 31)
+ *errmsg = _("value must be in the range 0 to 31");
+ return insn | (value << 43) | (value << 48);
+}
+
+
+static long long
+extract_nps_rbdouble_64 (unsigned long long insn,
+ bfd_boolean * invalid)
+{
+ int value1 = (insn >> 43) & 0x1F;
+ int value2 = (insn >> 48) & 0x1F;
+
+ if (value1 != value2)
+ *invalid = TRUE;
+
+ return value1;
+}
+
+static unsigned long long
+insert_nps_misc_imm_offset (unsigned long long insn,
+ long long value,
+ const char ** errmsg)
+{
+ if (value & 0x3)
+ {
+ *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
+ value = 0;
+ }
+ insn |= (value << 6);
return insn;
}
-static int
-extract_nps_dst_pos_and_size (unsigned insn ATTRIBUTE_UNUSED,
- bfd_boolean * invalid ATTRIBUTE_UNUSED)
+static long long int
+extract_nps_misc_imm_offset (unsigned long long insn,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
{
- return (insn & 0x1f);
+ return ((insn >> 8) & 0x1f) * 4;
+}
+
+static long long int
+extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
+ bfd_boolean * invalid ATTRIBUTE_UNUSED)
+{
+ int value = 0;
+
+ value |= ((insn >> 6) & 0x003f) << 0;
+ value |= ((insn >> 0) & 0x003f) << 6;
+
+ return value;
}
/* Include the generic extract/insert functions. Order is important
{ "ls", 14, 5, 0, 1 },
#define F_PNZ (F_LS + 1)
{ "pnz", 15, 5, 0, 1 },
+#define F_NJ (F_PNZ + 1)
+ { "nj", 21, 5, 0, 1 },
+#define F_NM (F_NJ + 1)
+ { "nm", 23, 5, 0, 1 },
+#define F_NO_T (F_NM + 1)
+ { "nt", 24, 5, 0, 1 },
/* FLAG. */
-#define F_FLAG (F_PNZ + 1)
+#define F_FLAG (F_NO_T + 1)
{ "f", 1, 1, 15, 1 },
#define F_FFAKE (F_FLAG + 1)
{ "f", 0, 0, 0, 1 },
{ "d", 1, 1, 5, 1 },
#define F_DFAKE (F_D + 1)
{ "d", 0, 0, 0, 1 },
+#define F_DNZ_ND (F_DFAKE + 1)
+ { "nd", 0, 1, 16, 0 },
+#define F_DNZ_D (F_DNZ_ND + 1)
+ { "d", 1, 1, 16, 1 },
/* Data size. */
-#define F_SIZEB1 (F_DFAKE + 1)
+#define F_SIZEB1 (F_DNZ_D + 1)
{ "b", 1, 2, 1, 1 },
#define F_SIZEB7 (F_SIZEB1 + 1)
{ "b", 1, 2, 7, 1 },
{ "di", 1, 1, 5, 1 },
#define F_DI11 (F_DI5 + 1)
{ "di", 1, 1, 11, 1 },
-#define F_DI15 (F_DI11 + 1)
+#define F_DI14 (F_DI11 + 1)
+ { "di", 1, 1, 14, 1 },
+#define F_DI15 (F_DI14 + 1)
{ "di", 1, 1, 15, 1 },
/* ARCv2 specific. */
{ "h", 2, 2, 7, 1 },
#define F_H17 (F_H7 + 1)
{ "h", 2, 2, 17, 1 },
+#define F_SIZED (F_H17 + 1)
+ { "dd", 8, 0, 0, 0 }, /* Fake. */
/* Fake Flags. */
-#define F_NE (F_H17 + 1)
+#define F_NE (F_SIZED + 1)
{ "ne", 0, 0, 0, 1 },
/* ARC NPS400 Support: See comment near head of file. */
#define F_NPS_CL (F_NE + 1)
{ "cl", 0, 0, 0, 1 },
-#define F_NPS_FLAG (F_NPS_CL + 1)
+#define F_NPS_NA (F_NPS_CL + 1)
+ { "na", 1, 1, 9, 1 },
+
+#define F_NPS_SR (F_NPS_NA + 1)
+ { "s", 1, 1, 13, 1 },
+
+#define F_NPS_M (F_NPS_SR + 1)
+ { "m", 1, 1, 7, 1 },
+
+#define F_NPS_FLAG (F_NPS_M + 1)
{ "f", 1, 1, 20, 1 },
#define F_NPS_R (F_NPS_FLAG + 1)
#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
{ "restore", 0, 0, 0, 1 },
+#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
+ { "sx", 1, 1, 14, 1 },
+
+#define F_NPS_AR (F_NPS_SX + 1)
+ { "ar", 0, 1, 0, 1 },
+
+#define F_NPS_AL (F_NPS_AR + 1)
+ { "al", 1, 1, 0, 1 },
+
+#define F_NPS_S (F_NPS_AL + 1)
+ { "s", 0, 0, 0, 1 },
+
+#define F_NPS_ZNCV_RD (F_NPS_S + 1)
+ { "rd", 0, 1, 15, 1 },
+
+#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
+ { "wr", 1, 1, 15, 1 },
+
+#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
+ { "p0", 0, 0, 0, 1 },
+
+#define F_NPS_P1 (F_NPS_P0 + 1)
+ { "p1", 0, 0, 0, 1 },
+
+#define F_NPS_P2 (F_NPS_P1 + 1)
+ { "p2", 0, 0, 0, 1 },
+
+#define F_NPS_P3 (F_NPS_P2 + 1)
+ { "p3", 0, 0, 0, 1 },
+
+#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
+ { "di", 0, 0, 0, 1 },
+
+#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
+ { "cl", 1, 1, 6, 1 },
+
+#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
+ { "cl", 1, 1, 16, 1 },
+
+#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
+ { "x2", 1, 2, 9, 1 },
+
+#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
+ { "x2", 1, 2, 22, 1 },
+
+#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
+ { "x4", 2, 2, 9, 1 },
+
+#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
+ { "x4", 2, 2, 22, 1 },
+
+#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
+ { "core", 1, 3, 6, 1 },
+
+#define F_NPS_CLSR (F_NPS_CORE + 1)
+ { "clsr", 2, 3, 6, 1 },
+
+#define F_NPS_ALL (F_NPS_CLSR + 1)
+ { "all", 3, 3, 6, 1 },
+
+#define F_NPS_GIC (F_NPS_ALL + 1)
+ { "gic", 4, 3, 6, 1 },
+
+#define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
+ { "gic", 5, 3, 6, 1 },
};
const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
#define C_EMPTY 0
{ F_CLASS_NONE, { F_NULL } },
-#define C_CC (C_EMPTY + 1)
- { F_CLASS_OPTIONAL, { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
- F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
- F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
- F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
- F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
- F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+#define C_CC_EQ (C_EMPTY + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
+
+#define C_CC_GE (C_CC_EQ + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
+
+#define C_CC_GT (C_CC_GE + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
+
+#define C_CC_HI (C_CC_GT + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
+
+#define C_CC_HS (C_CC_HI + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
+
+#define C_CC_LE (C_CC_HS + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
+
+#define C_CC_LO (C_CC_LE + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
+
+#define C_CC_LS (C_CC_LO + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
+
+#define C_CC_LT (C_CC_LS + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
+
+#define C_CC_NE (C_CC_LT + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
+
+#define C_AA_AB (C_CC_NE + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
+
+#define C_AA_AW (C_AA_AB + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
+
+#define C_ZZ_D (C_AA_AW + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
+
+#define C_ZZ_H (C_ZZ_D + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
+
+#define C_ZZ_B (C_ZZ_H + 1)
+ {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
+
+#define C_CC (C_ZZ_B + 1)
+ { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
+ { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
+ F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
+ F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
+ F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
+ F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
+ F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
#define C_AA_ADDR3 (C_CC + 1)
#define C_AA27 (C_CC + 1)
- { F_CLASS_OPTIONAL, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
#define C_AA21 (C_AA_ADDR3 + 1)
- { F_CLASS_OPTIONAL, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
#define C_AA8 (C_AA_ADDR9 + 1)
- { F_CLASS_OPTIONAL, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
+ { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
#define C_F (C_AA_ADDR22 + 1)
{ F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
{ F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
#define C_D (C_T + 1)
{ F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
+#define C_DNZ_D (C_D + 1)
+ { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
-#define C_DHARD (C_D + 1)
+#define C_DHARD (C_DNZ_D + 1)
{ F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
#define C_DI20 (C_DHARD + 1)
{ F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
-#define C_DI16 (C_DI20 + 1)
+#define C_DI14 (C_DI20 + 1)
+ { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
+#define C_DI16 (C_DI14 + 1)
{ F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
#define C_DI26 (C_DI16 + 1)
{ F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
{ F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
#define C_NE (C_AS + 1)
- { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
+ { F_CLASS_REQUIRED, { F_NE, F_NULL}},
/* ARC NPS400 Support: See comment near head of file. */
#define C_NPS_CL (C_NE + 1)
{ F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
-#define C_NPS_F (C_NPS_CL + 1)
+#define C_NPS_NA (C_NPS_CL + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
+
+#define C_NPS_SR (C_NPS_NA + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
+
+#define C_NPS_M (C_NPS_SR + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
+
+#define C_NPS_F (C_NPS_M + 1)
{ F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
#define C_NPS_R (C_NPS_F + 1)
#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
{ F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
+#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
+
+#define C_NPS_AR_AL (C_NPS_SX + 1)
+ { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
+
+#define C_NPS_S (C_NPS_AR_AL + 1)
+ { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
+
+#define C_NPS_ZNCV (C_NPS_S + 1)
+ { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
+
+#define C_NPS_P0 (C_NPS_ZNCV + 1)
+ { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
+
+#define C_NPS_P1 (C_NPS_P0 + 1)
+ { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
+
+#define C_NPS_P2 (C_NPS_P1 + 1)
+ { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
+
+#define C_NPS_P3 (C_NPS_P2 + 1)
+ { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
+
+#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
+ { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
+
+#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
+
+#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
+
+#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
+
+#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
+ { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
+
+#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
+ { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
+
+#define C_NPS_CLSR (C_NPS_CORE + 1)
+ { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
+
+#define C_NPS_ALL (C_NPS_CLSR + 1)
+ { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
+
+#define C_NPS_GIC (C_NPS_ALL + 1)
+ { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
+
+#define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
+ { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
};
const unsigned char flags_none[] = { 0 };
index is used to indicate end-of-list. */
#define UNUSED 0
{ 0, 0, 0, 0, 0, 0 },
+
+#define IGNORED (UNUSED + 1)
+ { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
+
/* The plain integer register fields. Used by 32 bit
instructions. */
-#define RA (UNUSED + 1)
+#define RA (IGNORED + 1)
{ 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
-#define RB (RA + 1)
+#define RA_CHK (RA + 1)
+ { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
+#define RB (RA_CHK + 1)
{ 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
-#define RC (RB + 1)
+#define RB_CHK (RB + 1)
+ { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
+#define RC (RB_CHK + 1)
{ 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
#define RBdup (RC + 1)
{ 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
#define RAD (RBdup + 1)
{ 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
-#define RCD (RAD + 1)
+#define RAD_CHK (RAD + 1)
+ { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
+#define RCD (RAD_CHK + 1)
{ 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
+#define RBD (RCD + 1)
+ { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rbd, extract_rb },
+#define RBDdup (RBD + 1)
+ { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_TRUNCATE,
+ insert_rbd, extract_rb },
/* The plain integer register fields. Used by short
instructions. */
-#define RA16 (RCD + 1)
-#define RA_S (RCD + 1)
+#define RA16 (RBDdup + 1)
+#define RA_S (RBDdup + 1)
{ 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
#define RB16 (RA16 + 1)
#define RB_S (RA16 + 1)
#define RRANGE_EL (ZA + 1)
{ 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
insert_rrange, extract_rrange},
-#define FP_EL (RRANGE_EL + 1)
+#define R13_EL (RRANGE_EL + 1)
+ { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
+ insert_r13el, extract_rrange },
+#define FP_EL (R13_EL + 1)
{ 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
insert_fpel, extract_fpel },
#define BLINK_EL (FP_EL + 1)
#define UIMM6_20 (FKT_NT + 1)
{6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
+ /* Exactly like the above but used by relaxation. */
+#define UIMM6_20R (UIMM6_20 + 1)
+ {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+ insert_uimm6_20, extract_uimm6_20},
+
/* SIMM12_20 mask = 00000000000000000000111111222222. */
-#define SIMM12_20 (UIMM6_20 + 1)
+#define SIMM12_20 (UIMM6_20R + 1)
{12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
+ /* Exactly like the above but used by relaxation. */
+#define SIMM12_20R (SIMM12_20 + 1)
+ {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
+ insert_simm12_20, extract_simm12_20},
+
+ /* UIMM12_20 mask = 00000000000000000000111111222222. */
+#define UIMM12_20 (SIMM12_20R + 1)
+ {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
+
/* SIMM3_5_S mask = 0000011100000000. */
-#define SIMM3_5_S (SIMM12_20 + 1)
+#define SIMM3_5_S (UIMM12_20 + 1)
{3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
insert_simm3s, extract_simm3s},
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
extract_uimm7_a32_11_s},
+ /* The same as above but used by relaxation. */
+#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
+ {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
+ | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
+ insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
+
/* UIMM7_9_S mask = 0000000001111111. */
-#define UIMM7_9_S (UIMM7_A32_11_S + 1)
+#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
{7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
/* UIMM3_13_S mask = 0000000000000111. */
#define UIMM3_13_S (UIMM7_9_S + 1)
{3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
+ /* Exactly like the above but used for relaxation. */
+#define UIMM3_13R_S (UIMM3_13_S + 1)
+ {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+ insert_uimm3_13_s, extract_uimm3_13_s},
+
/* SIMM11_A32_7_S mask = 0000000111111111. */
-#define SIMM11_A32_7_S (UIMM3_13_S + 1)
+#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
{11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
| ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
/* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
#define SIMM21_A16_5 (UIMM6_8 + 1)
{21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
- | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE,
+ | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
insert_simm21_a16_5, extract_simm21_a16_5},
/* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
extract_simm8_a16_9_s},
+/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
+#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
+ {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
+ | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
+ extract_uimm10_6_s},
+
/* UIMM3_23 mask = 00000000000000000000000111000000. */
-#define UIMM3_23 (SIMM8_A16_9_S + 1)
+#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
{3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
/* UIMM10_6_S mask = 0000001111111111. */
{9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
insert_simm9_8, extract_simm9_8},
+ /* The same as above but used by relaxation. */
+#define SIMM9_8R (SIMM9_8 + 1)
+ {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
+ | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
+
/* UIMM10_A32_8_S mask = 0000000011111111. */
-#define UIMM10_A32_8_S (SIMM9_8 + 1)
+#define UIMM10_A32_8_S (SIMM9_8R + 1)
{10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
| ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
extract_uimm10_a32_8_s},
#define UIMM8_8_S (SIMM13_A16_20 + 1)
{8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
+ /* The same as above but used for relaxation. */
+#define UIMM8_8R_S (UIMM8_8_S + 1)
+ {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
+ insert_uimm8_8_s, extract_uimm8_8_s},
+
/* W6 mask = 00000000000000000000111111000000. */
-#define W6 (UIMM8_8_S + 1)
+#define W6 (UIMM8_8R_S + 1)
{6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
/* UIMM6_5_S mask = 0000011111100000. */
/* ARC NPS400 Support: See comment near head of file. */
#define NPS_R_DST_3B (UIMM6_5_S + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
- { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK, insert_nps_3bit_dst, extract_nps_3bit_dst },
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
- { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_nps_3bit_src2, extract_nps_3bit_src2 },
+ { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
#define NPS_R_DST (NPS_R_SRC2_3B + 1)
{ 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
{ 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
- { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size, extract_nps_bitop_size },
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bitop_size, extract_nps_bitop_size },
#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
- { 5, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
- { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
- { 8, 0, 0, ARC_OPERAND_UNSIGNED, insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
+ { 8, 0, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
{ 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
-#define NPS_RFLT_UIMM6 (NPS_UIMM16 + 1)
- { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
-};
+#define NPS_SIMM16 (NPS_UIMM16 + 1)
+ { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
+
+#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
+ { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
+
+#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
+ { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
+
+#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_src2_pos, extract_nps_src2_pos },
+
+#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_src1_pos, extract_nps_src1_pos },
+
+#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_addb_size, extract_nps_addb_size },
+
+#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_andb_size, extract_nps_andb_size },
+
+#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_fxorb_size, extract_nps_fxorb_size },
+
+#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_wxorb_size, extract_nps_wxorb_size },
+
+#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
+ { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
+
+#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
+ { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_qcmp_size, extract_nps_qcmp_size },
+
+#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
+ { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
+
+#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
+ { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
+
+#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
+ { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
+
+#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
+ { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_calc_entry_size, extract_nps_calc_entry_size },
+
+#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
+ { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
+
+#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
+ { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
+
+#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
+ { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
+
+#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
+ { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bitop2_size, extract_nps_bitop2_size },
+
+#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
+ { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bitop1_size, extract_nps_bitop1_size },
+
+#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
+
+#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
+ { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
+ { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
+ { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
+ { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
+ { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
+ { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
+ { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
+ { 2, 0, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
+
+#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
+ { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
+ { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
+ { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
+ { 5, 20, 0, ARC_OPERAND_UNSIGNED,
+ insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
+
+#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
+ { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
+ { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_field_size, extract_nps_field_size },
+
+#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
+ { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_shift_factor, extract_nps_shift_factor },
+
+#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
+ { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
+
+#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
+ { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
+ { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
+
+#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
+ { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_min_hofs, extract_nps_min_hofs },
+
+#define NPS_PSBC (NPS_MIN_HOFS + 1)
+ { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_DPI_DST (NPS_PSBC + 1)
+ { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
+
+ /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
+ but doesn't duplicate an operand. */
+#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
+ { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
+
+#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
+ { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_hash_width, extract_nps_hash_width },
+
+#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
+ { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
+ { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
+ { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
+ { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_hash_len, extract_nps_hash_len },
+
+#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
+ { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
+ { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
+ { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
+ { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
+ { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
+ { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_index3, extract_nps_index3 },
+
+#define COLON (NPS_E4BY_INDEX3 + 1)
+ { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
+
+#define NPS_BD (COLON + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_bd, extract_nps_bd },
+
+#define NPS_JID (NPS_BD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_jid, extract_nps_jid },
+
+#define NPS_LBD (NPS_JID + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_lbd, extract_nps_lbd },
+
+#define NPS_MBD (NPS_LBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_mbd, extract_nps_mbd },
+
+#define NPS_SD (NPS_MBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_sd, extract_nps_sd },
+
+#define NPS_SM (NPS_SD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_sm, extract_nps_sm },
+
+#define NPS_XA (NPS_SM + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_xa, extract_nps_xa },
+
+#define NPS_XD (NPS_XA + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_xd, extract_nps_xd },
+
+#define NPS_CD (NPS_XD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_cd, extract_nps_cd },
+
+#define NPS_CBD (NPS_CD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_cbd, extract_nps_cbd },
+
+#define NPS_CJID (NPS_CBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_cjid, extract_nps_cjid },
+
+#define NPS_CLBD (NPS_CJID + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_clbd, extract_nps_clbd },
+
+#define NPS_CM (NPS_CLBD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_cm, extract_nps_cm },
+
+#define NPS_CSD (NPS_CM + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_csd, extract_nps_csd },
+
+#define NPS_CXA (NPS_CSD + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_cxa, extract_nps_cxa },
+
+#define NPS_CXD (NPS_CXA + 1)
+ { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
+ insert_nps_cxd, extract_nps_cxd },
+
+#define NPS_BD_TYPE (NPS_CXD + 1)
+ { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
+ { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_bd_num_buff, extract_nps_bd_num_buff },
+
+#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
+ { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
+ { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_size_16bit, extract_nps_size_16bit },
+
+#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
+ { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_pmu_num_job, extract_nps_pmu_num_job },
+
+#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
+ { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_imm_entry, extract_nps_imm_entry },
+
+#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
+ { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_imm_offset, extract_nps_imm_offset },
+
+#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
+ { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
+
+#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
+ { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
+
+#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
+ { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
+
+#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
+ { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
+
+#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
+ { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
+
+#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
+ { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
+
+#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
+ { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
+
+#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
+ { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
+
+#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
+ { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
+
+#define NPS_RB_64 (NPS_RA_64 + 1)
+ { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
+
+#define NPS_RBdup_64 (NPS_RB_64 + 1)
+ { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
+
+#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
+ { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
+ insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
+
+#define NPS_RC_64 (NPS_RBdouble_64 + 1)
+ { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
+
+#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
+ { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
+
+#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
+ { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
+ insert_nps_proto_size, extract_nps_proto_size }
+};
const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
const unsigned arc_Toperand = FKT_T;
const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
+const unsigned char arg_32bit_rc[] = { RC };
+const unsigned char arg_32bit_u6[] = { UIMM6_20 };
+const unsigned char arg_32bit_limm[] = { LIMM };
+
/* The opcode table.
The format of the opcode table is:
{ "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
- F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
+ F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
+ F_NO_T, F_NULL } },
{ "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
const struct arc_aux_reg arc_aux_regs[] =
{
#undef DEF
-#define DEF(ADDR, SUBCLASS, NAME) \
- { ADDR, SUBCLASS, #NAME, sizeof (#NAME)-1 },
+#define DEF(ADDR, CPU, SUBCLASS, NAME) \
+ { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
#include "arc-regs.h"
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
{ SIMM25_A16_5 }, { C_D }},
- /* add_s c,b,u3 01101bbbccc00uuu. Wants UIMM3_13_S_PCREL. */
+ /* add_s c,b,u3 01101bbbccc00uuu. */
{ "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+ { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
- /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. Wants
- UIMM6_20_PCREL. */
+ /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
{ "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, UIMM6_20 }, { C_F }},
+ { RA, RB, UIMM6_20R }, { C_F }},
/* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
{ "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
{ RA, RB, LIMM }, { C_F }},
- /* ld_s c,b,u7 10000bbbcccuuuuu. Wants UIMM7_A32_11_S_PCREL. */
+ /* ld_s c,b,u7 10000bbbcccuuuuu. */
{ "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RC_S, BRAKET, RB_S, UIMM7_A32_11_S, BRAKETdup }, { 0 }},
+ { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
/* ld<.di><.aa><.x><zz> a,b,s9
- 00010bbbssssssssSBBBDaaZZXAAAAAA. Wants SIMM9_8_PCREL. */
+ 00010bbbssssssssSBBBDaaZZXAAAAAA. */
{ "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RA, BRAKET, RB, SIMM9_8, BRAKETdup },
+ { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
{ C_ZZ23, C_DI20, C_AA21, C_X25 }},
/* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
{ RA, BRAKET, RB, LIMM, BRAKETdup },
{ C_ZZ13, C_DI16, C_AA8, C_X15 }},
- /* mov_s b,u8 11011bbbuuuuuuuu. Wants UIMM8_8_S_PCREL. */
+ /* mov_s b,u8 11011bbbuuuuuuuu. */
{ "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB_S, UIMM8_8_S }, { 0 }},
+ { RB_S, UIMM8_8R_S }, { 0 }},
- /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. Wants
- SIMM12_20_PCREL. */
+ /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
{ "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, SIMM12_20 }, { C_F }},
+ { RB, SIMM12_20R }, { C_F }},
/* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
{ "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
{ RB, LIMM }, { C_F }},
- /* sub_s c,b,u3 01101bbbccc01uuu. UIMM3_13_S_PCREL. */
+ /* sub_s c,b,u3 01101bbbccc01uuu. */
{ "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RC_S, RB_S, UIMM3_13_S }, { 0 }},
+ { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
- /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA.
- UIMM6_20_PCREL. */
+ /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
{ "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RA, RB, UIMM6_20 }, { C_F }},
+ { RA, RB, UIMM6_20R }, { C_F }},
/* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
{ "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
{ RA, RB, LIMM }, { C_F }},
- /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA.
- UIMM6_20_PCREL. */
+ /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
{ "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
- | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20 }, { C_F }},
+ | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
/* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
{ "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
| ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
- /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ.
- UIMM6_20_PCREL. */
+ /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
{ "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
- { RB, UIMM6_20 }, { C_F, C_CC }},
+ { RB, UIMM6_20R }, { C_F, C_CC }},
/* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
{ "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
{ RB, LIMM }, { C_F, C_CC }},
- /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ.
- UIMM6_20_PCREL. */
+ /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
{ "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
| ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
- { RB, RBdup, UIMM6_20 }, { C_F, C_CC }},
+ { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
/* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
{ "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
};
const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
+
+/* Return length of an opcode in bytes. */
+
+int
+arc_opcode_len (const struct arc_opcode *opcode)
+{
+ if (opcode->mask < 0x10000ull)
+ return 2;
+
+ if (opcode->mask < 0x100000000ull)
+ return 4;
+
+ if (opcode->mask < 0x1000000000000ull)
+ return 6;
+
+ return 8;
+}
projects / thirdparty / binutils-gdb.git / blobdiff