/* Print i386 instructions for GDB, the GNU debugger.
- Copyright (C) 1988-2019 Free Software Foundation, Inc.
+ Copyright (C) 1988-2021 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
#include "opintl.h"
#include "opcode/i386.h"
#include "libiberty.h"
+#include "safe-ctype.h"
#include <setjmp.h>
static void OP_C (int, int);
static void OP_D (int, int);
static void OP_T (int, int);
-static void OP_R (int, int);
static void OP_MMX (int, int);
static void OP_XMM (int, int);
static void OP_EM (int, int);
static void OP_XS (int, int);
static void OP_M (int, int);
static void OP_VEX (int, int);
-static void OP_EX_Vex (int, int);
-static void OP_EX_VexW (int, int);
-static void OP_EX_VexImmW (int, int);
-static void OP_XMM_Vex (int, int);
-static void OP_XMM_VexW (int, int);
+static void OP_VexR (int, int);
+static void OP_VexW (int, int);
static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
+static void OP_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
-static void VCMP_Fixup (int, int);
static void VPCMP_Fixup (int, int);
static void VPCOM_Fixup (int, int);
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
-static void OP_Mwaitx (int, int);
static void NOP_Fixup1 (int, int);
static void NOP_Fixup2 (int, int);
static void OP_3DNowSuffix (int, int);
static void CMP_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
+static void SEP_Fixup (int, int);
static void BND_Fixup (int, int);
static void NOTRACK_Fixup (int, int);
static void HLE_Fixup1 (int, int);
static void HLE_Fixup3 (int, int);
static void CMPXCHG8B_Fixup (int, int);
static void XMM_Fixup (int, int);
-static void CRC32_Fixup (int, int);
static void FXSAVE_Fixup (int, int);
-static void PCMPESTR_Fixup (int, int);
-static void OP_LWPCB_E (int, int);
-static void OP_LWP_E (int, int);
-static void OP_Vex_2src_1 (int, int);
-static void OP_Vex_2src_2 (int, int);
-static void MOVBE_Fixup (int, int);
+static void MOVSXD_Fixup (int, int);
static void OP_Mask (int, int);
static int rex;
/* Bits of REX we've already used. */
static int rex_used;
-/* REX bits in original REX prefix ignored. */
-static int rex_ignored;
/* Mark parts used in the REX prefix. When we are testing for
empty prefix (for 8bit register REX extension), just mask it
out. Otherwise test for REX bit is excuse for existence of REX
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
+#define Mv { OP_M, v_mode }
#define Mv_bnd { OP_M, v_bndmk_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gm { OP_G, m_mode }
#define Gva { OP_G, va_mode }
#define Gw { OP_G, w_mode }
-#define Rd { OP_R, d_mode }
-#define Rdq { OP_R, dq_mode }
-#define Rm { OP_R, m_mode }
#define Ib { OP_I, b_mode }
#define sIb { OP_sI, b_mode } /* sign extened byte */
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
#define I1 { OP_I, const_1_mode }
#define Jb { OP_J, b_mode }
#define Jv { OP_J, v_mode }
+#define Jdqw { OP_J, dqw_mode }
#define Cm { OP_C, m_mode }
#define Dm { OP_D, m_mode }
#define Td { OP_T, d_mode }
#define RMDX { OP_REG, dx_reg }
#define eAX { OP_IMREG, eAX_reg }
-#define eBX { OP_IMREG, eBX_reg }
-#define eCX { OP_IMREG, eCX_reg }
-#define eDX { OP_IMREG, eDX_reg }
-#define eSP { OP_IMREG, eSP_reg }
-#define eBP { OP_IMREG, eBP_reg }
-#define eSI { OP_IMREG, eSI_reg }
-#define eDI { OP_IMREG, eDI_reg }
#define AL { OP_IMREG, al_reg }
#define CL { OP_IMREG, cl_reg }
-#define DL { OP_IMREG, dl_reg }
-#define BL { OP_IMREG, bl_reg }
-#define AH { OP_IMREG, ah_reg }
-#define CH { OP_IMREG, ch_reg }
-#define DH { OP_IMREG, dh_reg }
-#define BH { OP_IMREG, bh_reg }
-#define AX { OP_IMREG, ax_reg }
-#define DX { OP_IMREG, dx_reg }
#define zAX { OP_IMREG, z_mode_ax_reg }
#define indirDX { OP_IMREG, indir_dx_reg }
#define XMScalar { OP_XMM, scalar_mode }
#define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
#define XMM { OP_XMM, xmm_mode }
+#define TMM { OP_XMM, tmm_mode }
#define XMxmmq { OP_XMM, xmmq_mode }
#define EM { OP_EM, v_mode }
#define EMS { OP_EM, v_swap_mode }
#define EMd { OP_EM, d_mode }
#define EMx { OP_EM, x_mode }
-#define EXbScalar { OP_EX, b_scalar_mode }
+#define EXbwUnit { OP_EX, bw_unit_mode }
#define EXw { OP_EX, w_mode }
-#define EXwScalar { OP_EX, w_scalar_mode }
#define EXd { OP_EX, d_mode }
-#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
-#define EXdScalarS { OP_EX, d_scalar_swap_mode }
#define EXq { OP_EX, q_mode }
-#define EXqScalar { OP_EX, q_scalar_mode }
-#define EXqScalarS { OP_EX, q_scalar_swap_mode }
#define EXqS { OP_EX, q_swap_mode }
#define EXx { OP_EX, x_mode }
#define EXxS { OP_EX, x_swap_mode }
#define EXxmm { OP_EX, xmm_mode }
#define EXymm { OP_EX, ymm_mode }
+#define EXtmm { OP_EX, tmm_mode }
#define EXxmmq { OP_EX, xmmq_mode }
#define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
#define EXxmm_mb { OP_EX, xmm_mb_mode }
#define EXxmm_mw { OP_EX, xmm_mw_mode }
#define EXxmm_md { OP_EX, xmm_md_mode }
#define EXxmm_mq { OP_EX, xmm_mq_mode }
-#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define EMCq { OP_EMC, q_mode }
#define MXC { OP_MXC, 0 }
#define OPSUF { OP_3DNowSuffix, 0 }
+#define SEP { SEP_Fixup, 0 }
#define CMP { CMP_Fixup, 0 }
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
-#define Vex_2src_1 { OP_Vex_2src_1, 0 }
-#define Vex_2src_2 { OP_Vex_2src_2, 0 }
#define Vex { OP_VEX, vex_mode }
+#define VexW { OP_VexW, vex_mode }
#define VexScalar { OP_VEX, vex_scalar_mode }
+#define VexScalarR { OP_VexR, vex_scalar_mode }
#define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
-#define Vex128 { OP_VEX, vex128_mode }
-#define Vex256 { OP_VEX, vex256_mode }
#define VexGdq { OP_VEX, dq_mode }
-#define EXdVex { OP_EX_Vex, d_mode }
-#define EXdVexS { OP_EX_Vex, d_swap_mode }
-#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
-#define EXqVex { OP_EX_Vex, q_mode }
-#define EXqVexS { OP_EX_Vex, q_swap_mode }
-#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
-#define EXVexW { OP_EX_VexW, x_mode }
-#define EXdVexW { OP_EX_VexW, d_mode }
-#define EXqVexW { OP_EX_VexW, q_mode }
-#define EXVexImmW { OP_EX_VexImmW, x_mode }
-#define XMVex { OP_XMM_Vex, 0 }
-#define XMVexScalar { OP_XMM_Vex, scalar_mode }
-#define XMVexW { OP_XMM_VexW, 0 }
+#define VexTmm { OP_VEX, tmm_mode }
#define XMVexI4 { OP_REG_VexI4, x_mode }
+#define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
+#define VexI4 { OP_VexI4, 0 }
#define PCLMUL { PCLMUL_Fixup, 0 }
-#define VCMP { VCMP_Fixup, 0 }
#define VPCMP { VPCMP_Fixup, 0 }
#define VPCOM { VPCOM_Fixup, 0 }
#define MaskG { OP_G, mask_mode }
#define MaskE { OP_E, mask_mode }
#define MaskBDE { OP_E, mask_bd_mode }
-#define MaskR { OP_R, mask_mode }
#define MaskVex { OP_VEX, mask_mode }
#define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
#define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
#define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode }
+#define MVexSIBMEM { OP_M, vex_sibmem_mode }
+
/* Used handle "rep" prefix for string instructions. */
#define Xbr { REP_Fixup, eSI_reg }
#define Xvr { REP_Fixup, eSI_reg }
x_mode,
/* Similar to x_mode, but with different EVEX mem shifts. */
evex_x_gscat_mode,
+ /* Similar to x_mode, but with yet different EVEX mem shifts. */
+ bw_unit_mode,
/* Similar to x_mode, but with disabled broadcast. */
evex_x_nobcst_mode,
/* Similar to x_mode, but with operands swapped and disabled broadcast
xmm_md_mode,
/* XMM register or quad word memory operand */
xmm_mq_mode,
- /* XMM register or double/quad word memory operand, depending on
- VEX.W. */
- xmm_mdq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
ymmq_mode,
/* 32-byte YMM or 16-byte word operand */
ymmxmm_mode,
+ /* TMM operand */
+ tmm_mode,
/* d_mode in 32bit, q_mode in 64bit mode. */
m_mode,
/* pair of v_mode operands */
a_mode,
cond_jump_mode,
loop_jcxz_mode,
+ movsxd_mode,
v_bnd_mode,
/* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
v_bndmk_mode,
/* operand size depends on REX prefixes. */
dq_mode,
- /* registers like dq_mode, memory like w_mode. */
+ /* registers like dq_mode, memory like w_mode, displacements like
+ v_mode without considering Intel64 ISA. */
dqw_mode,
/* bounds operand */
bnd_mode,
dqd_mode,
/* normal vex mode */
vex_mode,
- /* 128bit vex mode */
- vex128_mode,
- /* 256bit vex mode */
- vex256_mode,
- /* operand size depends on the VEX.W bit. */
- vex_w_dq_mode,
-
- /* Similar to vex_w_dq_mode, with VSIB dword indices. */
+
+ /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
/* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
vex_vsib_d_w_d_mode,
- /* Similar to vex_w_dq_mode, with VSIB qword indices. */
+ /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
vex_vsib_q_w_dq_mode,
/* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
vex_vsib_q_w_d_mode,
+ /* mandatory non-vector SIB. */
+ vex_sibmem_mode,
/* scalar, ignore vector length. */
scalar_mode,
- /* like b_mode, ignore vector length. */
- b_scalar_mode,
- /* like w_mode, ignore vector length. */
- w_scalar_mode,
- /* like d_mode, ignore vector length. */
- d_scalar_mode,
- /* like d_swap_mode, ignore vector length. */
- d_scalar_swap_mode,
- /* like q_mode, ignore vector length. */
- q_scalar_mode,
- /* like q_swap_mode, ignore vector length. */
- q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
vex_scalar_mode,
- /* like vex_w_dq_mode, ignore vector length. */
+ /* Operand size depends on the VEX.W bit, ignore vector length. */
vex_scalar_w_dq_mode,
/* Static rounding. */
REG_0F01,
REG_0F0D,
REG_0F18,
- REG_0F1C_MOD_0,
- REG_0F1E_MOD_3,
+ REG_0F1C_P_0_MOD_0,
+ REG_0F1E_P_1_MOD_3,
+ REG_0F38D8_PREFIX_1,
+ REG_0F3A0F_PREFIX_1_MOD_3,
REG_0F71,
REG_0F72,
REG_0F73,
REG_VEX_0F72,
REG_VEX_0F73,
REG_VEX_0FAE,
+ REG_VEX_0F3849_X86_64_P_0_W_0_M_1,
REG_VEX_0F38F3,
- REG_XOP_LWPCB,
- REG_XOP_LWP,
- REG_XOP_TBM_01,
- REG_XOP_TBM_02,
+
+ REG_0FXOP_09_01_L_0,
+ REG_0FXOP_09_02_L_0,
+ REG_0FXOP_09_12_M_1_L_0,
+ REG_0FXOP_0A_12_L_0,
REG_EVEX_0F71,
REG_EVEX_0F72,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
+ MOD_0F12_PREFIX_2,
MOD_0F13,
MOD_0F16_PREFIX_0,
+ MOD_0F16_PREFIX_2,
MOD_0F17,
MOD_0F18_REG_0,
MOD_0F18_REG_1,
MOD_0F1B_PREFIX_1,
MOD_0F1C_PREFIX_0,
MOD_0F1E_PREFIX_1,
- MOD_0F24,
- MOD_0F26,
MOD_0F2B_PREFIX_0,
MOD_0F2B_PREFIX_1,
MOD_0F2B_PREFIX_2,
MOD_0F2B_PREFIX_3,
- MOD_0F51,
+ MOD_0F50,
MOD_0F71_REG_2,
MOD_0F71_REG_4,
MOD_0F71_REG_6,
MOD_0FD7,
MOD_0FE7_PREFIX_2,
MOD_0FF0_PREFIX_3,
- MOD_0F382A_PREFIX_2,
- MOD_0F38F5_PREFIX_2,
+ MOD_0F382A,
+ MOD_0F38DC_PREFIX_1,
+ MOD_0F38DD_PREFIX_1,
+ MOD_0F38DE_PREFIX_1,
+ MOD_0F38DF_PREFIX_1,
+ MOD_0F38F5,
MOD_0F38F6_PREFIX_0,
MOD_0F38F8_PREFIX_1,
MOD_0F38F8_PREFIX_2,
MOD_0F38F8_PREFIX_3,
- MOD_0F38F9_PREFIX_0,
+ MOD_0F38F9,
+ MOD_0F38FA_PREFIX_1,
+ MOD_0F38FB_PREFIX_1,
+ MOD_0F3A0F_PREFIX_1,
MOD_62_32BIT,
MOD_C4_32BIT,
MOD_C5_32BIT,
MOD_VEX_0F12_PREFIX_0,
+ MOD_VEX_0F12_PREFIX_2,
MOD_VEX_0F13,
MOD_VEX_0F16_PREFIX_0,
+ MOD_VEX_0F16_PREFIX_2,
MOD_VEX_0F17,
MOD_VEX_0F2B,
MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F99_P_2_LEN_0,
MOD_VEX_0FAE_REG_2,
MOD_VEX_0FAE_REG_3,
- MOD_VEX_0FD7_PREFIX_2,
- MOD_VEX_0FE7_PREFIX_2,
+ MOD_VEX_0FD7,
+ MOD_VEX_0FE7,
MOD_VEX_0FF0_PREFIX_3,
- MOD_VEX_0F381A_PREFIX_2,
- MOD_VEX_0F382A_PREFIX_2,
- MOD_VEX_0F382C_PREFIX_2,
- MOD_VEX_0F382D_PREFIX_2,
- MOD_VEX_0F382E_PREFIX_2,
- MOD_VEX_0F382F_PREFIX_2,
- MOD_VEX_0F385A_PREFIX_2,
- MOD_VEX_0F388C_PREFIX_2,
- MOD_VEX_0F388E_PREFIX_2,
- MOD_VEX_W_0_0F3A30_P_2_LEN_0,
- MOD_VEX_W_1_0F3A30_P_2_LEN_0,
- MOD_VEX_W_0_0F3A31_P_2_LEN_0,
- MOD_VEX_W_1_0F3A31_P_2_LEN_0,
- MOD_VEX_W_0_0F3A32_P_2_LEN_0,
- MOD_VEX_W_1_0F3A32_P_2_LEN_0,
- MOD_VEX_W_0_0F3A33_P_2_LEN_0,
- MOD_VEX_W_1_0F3A33_P_2_LEN_0,
-
- MOD_EVEX_0F10_PREFIX_1,
- MOD_EVEX_0F10_PREFIX_3,
- MOD_EVEX_0F11_PREFIX_1,
- MOD_EVEX_0F11_PREFIX_3,
+ MOD_VEX_0F381A,
+ MOD_VEX_0F382A,
+ MOD_VEX_0F382C,
+ MOD_VEX_0F382D,
+ MOD_VEX_0F382E,
+ MOD_VEX_0F382F,
+ MOD_VEX_0F3849_X86_64_P_0_W_0,
+ MOD_VEX_0F3849_X86_64_P_2_W_0,
+ MOD_VEX_0F3849_X86_64_P_3_W_0,
+ MOD_VEX_0F384B_X86_64_P_1_W_0,
+ MOD_VEX_0F384B_X86_64_P_2_W_0,
+ MOD_VEX_0F384B_X86_64_P_3_W_0,
+ MOD_VEX_0F385A,
+ MOD_VEX_0F385C_X86_64_P_1_W_0,
+ MOD_VEX_0F385E_X86_64_P_0_W_0,
+ MOD_VEX_0F385E_X86_64_P_1_W_0,
+ MOD_VEX_0F385E_X86_64_P_2_W_0,
+ MOD_VEX_0F385E_X86_64_P_3_W_0,
+ MOD_VEX_0F388C,
+ MOD_VEX_0F388E,
+ MOD_VEX_0F3A30_L_0,
+ MOD_VEX_0F3A31_L_0,
+ MOD_VEX_0F3A32_L_0,
+ MOD_VEX_0F3A33_L_0,
+
+ MOD_VEX_0FXOP_09_12,
+
MOD_EVEX_0F12_PREFIX_0,
+ MOD_EVEX_0F12_PREFIX_2,
+ MOD_EVEX_0F13,
MOD_EVEX_0F16_PREFIX_0,
+ MOD_EVEX_0F16_PREFIX_2,
+ MOD_EVEX_0F17,
+ MOD_EVEX_0F2B,
+ MOD_EVEX_0F381A_W_0,
+ MOD_EVEX_0F381A_W_1,
+ MOD_EVEX_0F381B_W_0,
+ MOD_EVEX_0F381B_W_1,
+ MOD_EVEX_0F3828_P_1,
+ MOD_EVEX_0F382A_P_1_W_1,
+ MOD_EVEX_0F3838_P_1,
+ MOD_EVEX_0F383A_P_1_W_0,
+ MOD_EVEX_0F385A_W_0,
+ MOD_EVEX_0F385A_W_1,
+ MOD_EVEX_0F385B_W_0,
+ MOD_EVEX_0F385B_W_1,
+ MOD_EVEX_0F387A_W_0,
+ MOD_EVEX_0F387B_W_0,
+ MOD_EVEX_0F387C,
MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5,
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
- RM_0F01_REG_5,
- RM_0F01_REG_7,
- RM_0F1E_MOD_3_REG_7,
- RM_0FAE_REG_6,
- RM_0FAE_REG_7
+ RM_0F01_REG_5_MOD_3,
+ RM_0F01_REG_7_MOD_3,
+ RM_0F1E_P_1_MOD_3_REG_7,
+ RM_0F3A0F_P_1_MOD_3_REG_0,
+ RM_0FAE_REG_6_MOD_3_P_0,
+ RM_0FAE_REG_7_MOD_3,
+ RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0
};
enum
{
PREFIX_90 = 0,
- PREFIX_MOD_0_0F01_REG_5,
- PREFIX_MOD_3_0F01_REG_5_RM_0,
- PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F01_REG_1_RM_4,
+ PREFIX_0F01_REG_1_RM_5,
+ PREFIX_0F01_REG_1_RM_6,
+ PREFIX_0F01_REG_1_RM_7,
+ PREFIX_0F01_REG_3_RM_1,
+ PREFIX_0F01_REG_5_MOD_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_1,
+ PREFIX_0F01_REG_5_MOD_3_RM_2,
+ PREFIX_0F01_REG_5_MOD_3_RM_4,
+ PREFIX_0F01_REG_5_MOD_3_RM_5,
+ PREFIX_0F01_REG_5_MOD_3_RM_6,
+ PREFIX_0F01_REG_5_MOD_3_RM_7,
+ PREFIX_0F01_REG_7_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_6,
+ PREFIX_0F01_REG_7_MOD_3_RM_7,
PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F60,
PREFIX_0F61,
PREFIX_0F62,
- PREFIX_0F6C,
- PREFIX_0F6D,
PREFIX_0F6F,
PREFIX_0F70,
- PREFIX_0F73_REG_3,
- PREFIX_0F73_REG_7,
PREFIX_0F78,
PREFIX_0F79,
PREFIX_0F7C,
PREFIX_0F7D,
PREFIX_0F7E,
PREFIX_0F7F,
- PREFIX_0FAE_REG_0,
- PREFIX_0FAE_REG_1,
- PREFIX_0FAE_REG_2,
- PREFIX_0FAE_REG_3,
- PREFIX_MOD_0_0FAE_REG_4,
- PREFIX_MOD_3_0FAE_REG_4,
- PREFIX_MOD_0_0FAE_REG_5,
- PREFIX_MOD_3_0FAE_REG_5,
- PREFIX_MOD_0_0FAE_REG_6,
- PREFIX_MOD_1_0FAE_REG_6,
- PREFIX_0FAE_REG_7,
+ PREFIX_0FAE_REG_0_MOD_3,
+ PREFIX_0FAE_REG_1_MOD_3,
+ PREFIX_0FAE_REG_2_MOD_3,
+ PREFIX_0FAE_REG_3_MOD_3,
+ PREFIX_0FAE_REG_4_MOD_0,
+ PREFIX_0FAE_REG_4_MOD_3,
+ PREFIX_0FAE_REG_5_MOD_3,
+ PREFIX_0FAE_REG_6_MOD_0,
+ PREFIX_0FAE_REG_6_MOD_3,
+ PREFIX_0FAE_REG_7_MOD_0,
PREFIX_0FB8,
PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0FC2,
- PREFIX_MOD_0_0FC3,
- PREFIX_MOD_0_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_7,
+ PREFIX_0FC7_REG_6_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_3,
+ PREFIX_0FC7_REG_7_MOD_3,
PREFIX_0FD0,
PREFIX_0FD6,
PREFIX_0FE6,
PREFIX_0FE7,
PREFIX_0FF0,
PREFIX_0FF7,
- PREFIX_0F3810,
- PREFIX_0F3814,
- PREFIX_0F3815,
- PREFIX_0F3817,
- PREFIX_0F3820,
- PREFIX_0F3821,
- PREFIX_0F3822,
- PREFIX_0F3823,
- PREFIX_0F3824,
- PREFIX_0F3825,
- PREFIX_0F3828,
- PREFIX_0F3829,
- PREFIX_0F382A,
- PREFIX_0F382B,
- PREFIX_0F3830,
- PREFIX_0F3831,
- PREFIX_0F3832,
- PREFIX_0F3833,
- PREFIX_0F3834,
- PREFIX_0F3835,
- PREFIX_0F3837,
- PREFIX_0F3838,
- PREFIX_0F3839,
- PREFIX_0F383A,
- PREFIX_0F383B,
- PREFIX_0F383C,
- PREFIX_0F383D,
- PREFIX_0F383E,
- PREFIX_0F383F,
- PREFIX_0F3840,
- PREFIX_0F3841,
- PREFIX_0F3880,
- PREFIX_0F3881,
- PREFIX_0F3882,
- PREFIX_0F38C8,
- PREFIX_0F38C9,
- PREFIX_0F38CA,
- PREFIX_0F38CB,
- PREFIX_0F38CC,
- PREFIX_0F38CD,
- PREFIX_0F38CF,
- PREFIX_0F38DB,
+ PREFIX_0F38D8,
PREFIX_0F38DC,
PREFIX_0F38DD,
PREFIX_0F38DE,
PREFIX_0F38DF,
PREFIX_0F38F0,
PREFIX_0F38F1,
- PREFIX_0F38F5,
PREFIX_0F38F6,
PREFIX_0F38F8,
- PREFIX_0F38F9,
- PREFIX_0F3A08,
- PREFIX_0F3A09,
- PREFIX_0F3A0A,
- PREFIX_0F3A0B,
- PREFIX_0F3A0C,
- PREFIX_0F3A0D,
- PREFIX_0F3A0E,
- PREFIX_0F3A14,
- PREFIX_0F3A15,
- PREFIX_0F3A16,
- PREFIX_0F3A17,
- PREFIX_0F3A20,
- PREFIX_0F3A21,
- PREFIX_0F3A22,
- PREFIX_0F3A40,
- PREFIX_0F3A41,
- PREFIX_0F3A42,
- PREFIX_0F3A44,
- PREFIX_0F3A60,
- PREFIX_0F3A61,
- PREFIX_0F3A62,
- PREFIX_0F3A63,
- PREFIX_0F3ACC,
- PREFIX_0F3ACE,
- PREFIX_0F3ACF,
- PREFIX_0F3ADF,
+ PREFIX_0F38FA,
+ PREFIX_0F38FB,
+ PREFIX_0F3A0F,
PREFIX_VEX_0F10,
PREFIX_VEX_0F11,
PREFIX_VEX_0F12,
PREFIX_VEX_0F5D,
PREFIX_VEX_0F5E,
PREFIX_VEX_0F5F,
- PREFIX_VEX_0F60,
- PREFIX_VEX_0F61,
- PREFIX_VEX_0F62,
- PREFIX_VEX_0F63,
- PREFIX_VEX_0F64,
- PREFIX_VEX_0F65,
- PREFIX_VEX_0F66,
- PREFIX_VEX_0F67,
- PREFIX_VEX_0F68,
- PREFIX_VEX_0F69,
- PREFIX_VEX_0F6A,
- PREFIX_VEX_0F6B,
- PREFIX_VEX_0F6C,
- PREFIX_VEX_0F6D,
- PREFIX_VEX_0F6E,
PREFIX_VEX_0F6F,
PREFIX_VEX_0F70,
- PREFIX_VEX_0F71_REG_2,
- PREFIX_VEX_0F71_REG_4,
- PREFIX_VEX_0F71_REG_6,
- PREFIX_VEX_0F72_REG_2,
- PREFIX_VEX_0F72_REG_4,
- PREFIX_VEX_0F72_REG_6,
- PREFIX_VEX_0F73_REG_2,
- PREFIX_VEX_0F73_REG_3,
- PREFIX_VEX_0F73_REG_6,
- PREFIX_VEX_0F73_REG_7,
- PREFIX_VEX_0F74,
- PREFIX_VEX_0F75,
- PREFIX_VEX_0F76,
- PREFIX_VEX_0F77,
PREFIX_VEX_0F7C,
PREFIX_VEX_0F7D,
PREFIX_VEX_0F7E,
PREFIX_VEX_0F98,
PREFIX_VEX_0F99,
PREFIX_VEX_0FC2,
- PREFIX_VEX_0FC4,
- PREFIX_VEX_0FC5,
PREFIX_VEX_0FD0,
- PREFIX_VEX_0FD1,
- PREFIX_VEX_0FD2,
- PREFIX_VEX_0FD3,
- PREFIX_VEX_0FD4,
- PREFIX_VEX_0FD5,
- PREFIX_VEX_0FD6,
- PREFIX_VEX_0FD7,
- PREFIX_VEX_0FD8,
- PREFIX_VEX_0FD9,
- PREFIX_VEX_0FDA,
- PREFIX_VEX_0FDB,
- PREFIX_VEX_0FDC,
- PREFIX_VEX_0FDD,
- PREFIX_VEX_0FDE,
- PREFIX_VEX_0FDF,
- PREFIX_VEX_0FE0,
- PREFIX_VEX_0FE1,
- PREFIX_VEX_0FE2,
- PREFIX_VEX_0FE3,
- PREFIX_VEX_0FE4,
- PREFIX_VEX_0FE5,
PREFIX_VEX_0FE6,
- PREFIX_VEX_0FE7,
- PREFIX_VEX_0FE8,
- PREFIX_VEX_0FE9,
- PREFIX_VEX_0FEA,
- PREFIX_VEX_0FEB,
- PREFIX_VEX_0FEC,
- PREFIX_VEX_0FED,
- PREFIX_VEX_0FEE,
- PREFIX_VEX_0FEF,
PREFIX_VEX_0FF0,
- PREFIX_VEX_0FF1,
- PREFIX_VEX_0FF2,
- PREFIX_VEX_0FF3,
- PREFIX_VEX_0FF4,
- PREFIX_VEX_0FF5,
- PREFIX_VEX_0FF6,
- PREFIX_VEX_0FF7,
- PREFIX_VEX_0FF8,
- PREFIX_VEX_0FF9,
- PREFIX_VEX_0FFA,
- PREFIX_VEX_0FFB,
- PREFIX_VEX_0FFC,
- PREFIX_VEX_0FFD,
- PREFIX_VEX_0FFE,
- PREFIX_VEX_0F3800,
- PREFIX_VEX_0F3801,
- PREFIX_VEX_0F3802,
- PREFIX_VEX_0F3803,
- PREFIX_VEX_0F3804,
- PREFIX_VEX_0F3805,
- PREFIX_VEX_0F3806,
- PREFIX_VEX_0F3807,
- PREFIX_VEX_0F3808,
- PREFIX_VEX_0F3809,
- PREFIX_VEX_0F380A,
- PREFIX_VEX_0F380B,
- PREFIX_VEX_0F380C,
- PREFIX_VEX_0F380D,
- PREFIX_VEX_0F380E,
- PREFIX_VEX_0F380F,
- PREFIX_VEX_0F3813,
- PREFIX_VEX_0F3816,
- PREFIX_VEX_0F3817,
- PREFIX_VEX_0F3818,
- PREFIX_VEX_0F3819,
- PREFIX_VEX_0F381A,
- PREFIX_VEX_0F381C,
- PREFIX_VEX_0F381D,
- PREFIX_VEX_0F381E,
- PREFIX_VEX_0F3820,
- PREFIX_VEX_0F3821,
- PREFIX_VEX_0F3822,
- PREFIX_VEX_0F3823,
- PREFIX_VEX_0F3824,
- PREFIX_VEX_0F3825,
- PREFIX_VEX_0F3828,
- PREFIX_VEX_0F3829,
- PREFIX_VEX_0F382A,
- PREFIX_VEX_0F382B,
- PREFIX_VEX_0F382C,
- PREFIX_VEX_0F382D,
- PREFIX_VEX_0F382E,
- PREFIX_VEX_0F382F,
- PREFIX_VEX_0F3830,
- PREFIX_VEX_0F3831,
- PREFIX_VEX_0F3832,
- PREFIX_VEX_0F3833,
- PREFIX_VEX_0F3834,
- PREFIX_VEX_0F3835,
- PREFIX_VEX_0F3836,
- PREFIX_VEX_0F3837,
- PREFIX_VEX_0F3838,
- PREFIX_VEX_0F3839,
- PREFIX_VEX_0F383A,
- PREFIX_VEX_0F383B,
- PREFIX_VEX_0F383C,
- PREFIX_VEX_0F383D,
- PREFIX_VEX_0F383E,
- PREFIX_VEX_0F383F,
- PREFIX_VEX_0F3840,
- PREFIX_VEX_0F3841,
- PREFIX_VEX_0F3845,
- PREFIX_VEX_0F3846,
- PREFIX_VEX_0F3847,
- PREFIX_VEX_0F3858,
- PREFIX_VEX_0F3859,
- PREFIX_VEX_0F385A,
- PREFIX_VEX_0F3878,
- PREFIX_VEX_0F3879,
- PREFIX_VEX_0F388C,
- PREFIX_VEX_0F388E,
- PREFIX_VEX_0F3890,
- PREFIX_VEX_0F3891,
- PREFIX_VEX_0F3892,
- PREFIX_VEX_0F3893,
- PREFIX_VEX_0F3896,
- PREFIX_VEX_0F3897,
- PREFIX_VEX_0F3898,
- PREFIX_VEX_0F3899,
- PREFIX_VEX_0F389A,
- PREFIX_VEX_0F389B,
- PREFIX_VEX_0F389C,
- PREFIX_VEX_0F389D,
- PREFIX_VEX_0F389E,
- PREFIX_VEX_0F389F,
- PREFIX_VEX_0F38A6,
- PREFIX_VEX_0F38A7,
- PREFIX_VEX_0F38A8,
- PREFIX_VEX_0F38A9,
- PREFIX_VEX_0F38AA,
- PREFIX_VEX_0F38AB,
- PREFIX_VEX_0F38AC,
- PREFIX_VEX_0F38AD,
- PREFIX_VEX_0F38AE,
- PREFIX_VEX_0F38AF,
- PREFIX_VEX_0F38B6,
- PREFIX_VEX_0F38B7,
- PREFIX_VEX_0F38B8,
- PREFIX_VEX_0F38B9,
- PREFIX_VEX_0F38BA,
- PREFIX_VEX_0F38BB,
- PREFIX_VEX_0F38BC,
- PREFIX_VEX_0F38BD,
- PREFIX_VEX_0F38BE,
- PREFIX_VEX_0F38BF,
- PREFIX_VEX_0F38CF,
- PREFIX_VEX_0F38DB,
- PREFIX_VEX_0F38DC,
- PREFIX_VEX_0F38DD,
- PREFIX_VEX_0F38DE,
- PREFIX_VEX_0F38DF,
- PREFIX_VEX_0F38F2,
- PREFIX_VEX_0F38F3_REG_1,
- PREFIX_VEX_0F38F3_REG_2,
- PREFIX_VEX_0F38F3_REG_3,
+ PREFIX_VEX_0F3849_X86_64,
+ PREFIX_VEX_0F384B_X86_64,
+ PREFIX_VEX_0F385C_X86_64,
+ PREFIX_VEX_0F385E_X86_64,
PREFIX_VEX_0F38F5,
PREFIX_VEX_0F38F6,
PREFIX_VEX_0F38F7,
- PREFIX_VEX_0F3A00,
- PREFIX_VEX_0F3A01,
- PREFIX_VEX_0F3A02,
- PREFIX_VEX_0F3A04,
- PREFIX_VEX_0F3A05,
- PREFIX_VEX_0F3A06,
- PREFIX_VEX_0F3A08,
- PREFIX_VEX_0F3A09,
- PREFIX_VEX_0F3A0A,
- PREFIX_VEX_0F3A0B,
- PREFIX_VEX_0F3A0C,
- PREFIX_VEX_0F3A0D,
- PREFIX_VEX_0F3A0E,
- PREFIX_VEX_0F3A0F,
- PREFIX_VEX_0F3A14,
- PREFIX_VEX_0F3A15,
- PREFIX_VEX_0F3A16,
- PREFIX_VEX_0F3A17,
- PREFIX_VEX_0F3A18,
- PREFIX_VEX_0F3A19,
- PREFIX_VEX_0F3A1D,
- PREFIX_VEX_0F3A20,
- PREFIX_VEX_0F3A21,
- PREFIX_VEX_0F3A22,
- PREFIX_VEX_0F3A30,
- PREFIX_VEX_0F3A31,
- PREFIX_VEX_0F3A32,
- PREFIX_VEX_0F3A33,
- PREFIX_VEX_0F3A38,
- PREFIX_VEX_0F3A39,
- PREFIX_VEX_0F3A40,
- PREFIX_VEX_0F3A41,
- PREFIX_VEX_0F3A42,
- PREFIX_VEX_0F3A44,
- PREFIX_VEX_0F3A46,
- PREFIX_VEX_0F3A48,
- PREFIX_VEX_0F3A49,
- PREFIX_VEX_0F3A4A,
- PREFIX_VEX_0F3A4B,
- PREFIX_VEX_0F3A4C,
- PREFIX_VEX_0F3A5C,
- PREFIX_VEX_0F3A5D,
- PREFIX_VEX_0F3A5E,
- PREFIX_VEX_0F3A5F,
- PREFIX_VEX_0F3A60,
- PREFIX_VEX_0F3A61,
- PREFIX_VEX_0F3A62,
- PREFIX_VEX_0F3A63,
- PREFIX_VEX_0F3A68,
- PREFIX_VEX_0F3A69,
- PREFIX_VEX_0F3A6A,
- PREFIX_VEX_0F3A6B,
- PREFIX_VEX_0F3A6C,
- PREFIX_VEX_0F3A6D,
- PREFIX_VEX_0F3A6E,
- PREFIX_VEX_0F3A6F,
- PREFIX_VEX_0F3A78,
- PREFIX_VEX_0F3A79,
- PREFIX_VEX_0F3A7A,
- PREFIX_VEX_0F3A7B,
- PREFIX_VEX_0F3A7C,
- PREFIX_VEX_0F3A7D,
- PREFIX_VEX_0F3A7E,
- PREFIX_VEX_0F3A7F,
- PREFIX_VEX_0F3ACE,
- PREFIX_VEX_0F3ACF,
- PREFIX_VEX_0F3ADF,
PREFIX_VEX_0F3AF0,
PREFIX_EVEX_0F10,
PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12,
- PREFIX_EVEX_0F13,
- PREFIX_EVEX_0F14,
- PREFIX_EVEX_0F15,
PREFIX_EVEX_0F16,
- PREFIX_EVEX_0F17,
- PREFIX_EVEX_0F28,
- PREFIX_EVEX_0F29,
PREFIX_EVEX_0F2A,
- PREFIX_EVEX_0F2B,
- PREFIX_EVEX_0F2C,
- PREFIX_EVEX_0F2D,
- PREFIX_EVEX_0F2E,
- PREFIX_EVEX_0F2F,
PREFIX_EVEX_0F51,
- PREFIX_EVEX_0F54,
- PREFIX_EVEX_0F55,
- PREFIX_EVEX_0F56,
- PREFIX_EVEX_0F57,
PREFIX_EVEX_0F58,
PREFIX_EVEX_0F59,
PREFIX_EVEX_0F5A,
PREFIX_EVEX_0F5D,
PREFIX_EVEX_0F5E,
PREFIX_EVEX_0F5F,
- PREFIX_EVEX_0F60,
- PREFIX_EVEX_0F61,
- PREFIX_EVEX_0F62,
- PREFIX_EVEX_0F63,
- PREFIX_EVEX_0F64,
- PREFIX_EVEX_0F65,
- PREFIX_EVEX_0F66,
- PREFIX_EVEX_0F67,
- PREFIX_EVEX_0F68,
- PREFIX_EVEX_0F69,
- PREFIX_EVEX_0F6A,
- PREFIX_EVEX_0F6B,
- PREFIX_EVEX_0F6C,
- PREFIX_EVEX_0F6D,
- PREFIX_EVEX_0F6E,
PREFIX_EVEX_0F6F,
PREFIX_EVEX_0F70,
- PREFIX_EVEX_0F71_REG_2,
- PREFIX_EVEX_0F71_REG_4,
- PREFIX_EVEX_0F71_REG_6,
- PREFIX_EVEX_0F72_REG_0,
- PREFIX_EVEX_0F72_REG_1,
- PREFIX_EVEX_0F72_REG_2,
- PREFIX_EVEX_0F72_REG_4,
- PREFIX_EVEX_0F72_REG_6,
- PREFIX_EVEX_0F73_REG_2,
- PREFIX_EVEX_0F73_REG_3,
- PREFIX_EVEX_0F73_REG_6,
- PREFIX_EVEX_0F73_REG_7,
- PREFIX_EVEX_0F74,
- PREFIX_EVEX_0F75,
- PREFIX_EVEX_0F76,
PREFIX_EVEX_0F78,
PREFIX_EVEX_0F79,
PREFIX_EVEX_0F7A,
PREFIX_EVEX_0F7E,
PREFIX_EVEX_0F7F,
PREFIX_EVEX_0FC2,
- PREFIX_EVEX_0FC4,
- PREFIX_EVEX_0FC5,
- PREFIX_EVEX_0FC6,
- PREFIX_EVEX_0FD1,
- PREFIX_EVEX_0FD2,
- PREFIX_EVEX_0FD3,
- PREFIX_EVEX_0FD4,
- PREFIX_EVEX_0FD5,
- PREFIX_EVEX_0FD6,
- PREFIX_EVEX_0FD8,
- PREFIX_EVEX_0FD9,
- PREFIX_EVEX_0FDA,
- PREFIX_EVEX_0FDB,
- PREFIX_EVEX_0FDC,
- PREFIX_EVEX_0FDD,
- PREFIX_EVEX_0FDE,
- PREFIX_EVEX_0FDF,
- PREFIX_EVEX_0FE0,
- PREFIX_EVEX_0FE1,
- PREFIX_EVEX_0FE2,
- PREFIX_EVEX_0FE3,
- PREFIX_EVEX_0FE4,
- PREFIX_EVEX_0FE5,
PREFIX_EVEX_0FE6,
- PREFIX_EVEX_0FE7,
- PREFIX_EVEX_0FE8,
- PREFIX_EVEX_0FE9,
- PREFIX_EVEX_0FEA,
- PREFIX_EVEX_0FEB,
- PREFIX_EVEX_0FEC,
- PREFIX_EVEX_0FED,
- PREFIX_EVEX_0FEE,
- PREFIX_EVEX_0FEF,
- PREFIX_EVEX_0FF1,
- PREFIX_EVEX_0FF2,
- PREFIX_EVEX_0FF3,
- PREFIX_EVEX_0FF4,
- PREFIX_EVEX_0FF5,
- PREFIX_EVEX_0FF6,
- PREFIX_EVEX_0FF8,
- PREFIX_EVEX_0FF9,
- PREFIX_EVEX_0FFA,
- PREFIX_EVEX_0FFB,
- PREFIX_EVEX_0FFC,
- PREFIX_EVEX_0FFD,
- PREFIX_EVEX_0FFE,
- PREFIX_EVEX_0F3800,
- PREFIX_EVEX_0F3804,
- PREFIX_EVEX_0F380B,
- PREFIX_EVEX_0F380C,
- PREFIX_EVEX_0F380D,
PREFIX_EVEX_0F3810,
PREFIX_EVEX_0F3811,
PREFIX_EVEX_0F3812,
PREFIX_EVEX_0F3813,
PREFIX_EVEX_0F3814,
PREFIX_EVEX_0F3815,
- PREFIX_EVEX_0F3816,
- PREFIX_EVEX_0F3818,
- PREFIX_EVEX_0F3819,
- PREFIX_EVEX_0F381A,
- PREFIX_EVEX_0F381B,
- PREFIX_EVEX_0F381C,
- PREFIX_EVEX_0F381D,
- PREFIX_EVEX_0F381E,
- PREFIX_EVEX_0F381F,
PREFIX_EVEX_0F3820,
PREFIX_EVEX_0F3821,
PREFIX_EVEX_0F3822,
PREFIX_EVEX_0F3828,
PREFIX_EVEX_0F3829,
PREFIX_EVEX_0F382A,
- PREFIX_EVEX_0F382B,
- PREFIX_EVEX_0F382C,
- PREFIX_EVEX_0F382D,
PREFIX_EVEX_0F3830,
PREFIX_EVEX_0F3831,
PREFIX_EVEX_0F3832,
PREFIX_EVEX_0F3833,
PREFIX_EVEX_0F3834,
PREFIX_EVEX_0F3835,
- PREFIX_EVEX_0F3836,
- PREFIX_EVEX_0F3837,
PREFIX_EVEX_0F3838,
PREFIX_EVEX_0F3839,
PREFIX_EVEX_0F383A,
- PREFIX_EVEX_0F383B,
- PREFIX_EVEX_0F383C,
- PREFIX_EVEX_0F383D,
- PREFIX_EVEX_0F383E,
- PREFIX_EVEX_0F383F,
- PREFIX_EVEX_0F3840,
- PREFIX_EVEX_0F3842,
- PREFIX_EVEX_0F3843,
- PREFIX_EVEX_0F3844,
- PREFIX_EVEX_0F3845,
- PREFIX_EVEX_0F3846,
- PREFIX_EVEX_0F3847,
- PREFIX_EVEX_0F384C,
- PREFIX_EVEX_0F384D,
- PREFIX_EVEX_0F384E,
- PREFIX_EVEX_0F384F,
- PREFIX_EVEX_0F3850,
- PREFIX_EVEX_0F3851,
PREFIX_EVEX_0F3852,
PREFIX_EVEX_0F3853,
- PREFIX_EVEX_0F3854,
- PREFIX_EVEX_0F3855,
- PREFIX_EVEX_0F3858,
- PREFIX_EVEX_0F3859,
- PREFIX_EVEX_0F385A,
- PREFIX_EVEX_0F385B,
- PREFIX_EVEX_0F3862,
- PREFIX_EVEX_0F3863,
- PREFIX_EVEX_0F3864,
- PREFIX_EVEX_0F3865,
- PREFIX_EVEX_0F3866,
PREFIX_EVEX_0F3868,
- PREFIX_EVEX_0F3870,
- PREFIX_EVEX_0F3871,
PREFIX_EVEX_0F3872,
- PREFIX_EVEX_0F3873,
- PREFIX_EVEX_0F3875,
- PREFIX_EVEX_0F3876,
- PREFIX_EVEX_0F3877,
- PREFIX_EVEX_0F3878,
- PREFIX_EVEX_0F3879,
- PREFIX_EVEX_0F387A,
- PREFIX_EVEX_0F387B,
- PREFIX_EVEX_0F387C,
- PREFIX_EVEX_0F387D,
- PREFIX_EVEX_0F387E,
- PREFIX_EVEX_0F387F,
- PREFIX_EVEX_0F3883,
- PREFIX_EVEX_0F3888,
- PREFIX_EVEX_0F3889,
- PREFIX_EVEX_0F388A,
- PREFIX_EVEX_0F388B,
- PREFIX_EVEX_0F388D,
- PREFIX_EVEX_0F388F,
- PREFIX_EVEX_0F3890,
- PREFIX_EVEX_0F3891,
- PREFIX_EVEX_0F3892,
- PREFIX_EVEX_0F3893,
- PREFIX_EVEX_0F3896,
- PREFIX_EVEX_0F3897,
- PREFIX_EVEX_0F3898,
- PREFIX_EVEX_0F3899,
PREFIX_EVEX_0F389A,
PREFIX_EVEX_0F389B,
- PREFIX_EVEX_0F389C,
- PREFIX_EVEX_0F389D,
- PREFIX_EVEX_0F389E,
- PREFIX_EVEX_0F389F,
- PREFIX_EVEX_0F38A0,
- PREFIX_EVEX_0F38A1,
- PREFIX_EVEX_0F38A2,
- PREFIX_EVEX_0F38A3,
- PREFIX_EVEX_0F38A6,
- PREFIX_EVEX_0F38A7,
- PREFIX_EVEX_0F38A8,
- PREFIX_EVEX_0F38A9,
PREFIX_EVEX_0F38AA,
PREFIX_EVEX_0F38AB,
- PREFIX_EVEX_0F38AC,
- PREFIX_EVEX_0F38AD,
- PREFIX_EVEX_0F38AE,
- PREFIX_EVEX_0F38AF,
- PREFIX_EVEX_0F38B4,
- PREFIX_EVEX_0F38B5,
- PREFIX_EVEX_0F38B6,
- PREFIX_EVEX_0F38B7,
- PREFIX_EVEX_0F38B8,
- PREFIX_EVEX_0F38B9,
- PREFIX_EVEX_0F38BA,
- PREFIX_EVEX_0F38BB,
- PREFIX_EVEX_0F38BC,
- PREFIX_EVEX_0F38BD,
- PREFIX_EVEX_0F38BE,
- PREFIX_EVEX_0F38BF,
- PREFIX_EVEX_0F38C4,
- PREFIX_EVEX_0F38C6_REG_1,
- PREFIX_EVEX_0F38C6_REG_2,
- PREFIX_EVEX_0F38C6_REG_5,
- PREFIX_EVEX_0F38C6_REG_6,
- PREFIX_EVEX_0F38C7_REG_1,
- PREFIX_EVEX_0F38C7_REG_2,
- PREFIX_EVEX_0F38C7_REG_5,
- PREFIX_EVEX_0F38C7_REG_6,
- PREFIX_EVEX_0F38C8,
- PREFIX_EVEX_0F38CA,
- PREFIX_EVEX_0F38CB,
- PREFIX_EVEX_0F38CC,
- PREFIX_EVEX_0F38CD,
- PREFIX_EVEX_0F38CF,
- PREFIX_EVEX_0F38DC,
- PREFIX_EVEX_0F38DD,
- PREFIX_EVEX_0F38DE,
- PREFIX_EVEX_0F38DF,
-
- PREFIX_EVEX_0F3A00,
- PREFIX_EVEX_0F3A01,
- PREFIX_EVEX_0F3A03,
- PREFIX_EVEX_0F3A04,
- PREFIX_EVEX_0F3A05,
- PREFIX_EVEX_0F3A08,
- PREFIX_EVEX_0F3A09,
- PREFIX_EVEX_0F3A0A,
- PREFIX_EVEX_0F3A0B,
- PREFIX_EVEX_0F3A0F,
- PREFIX_EVEX_0F3A14,
- PREFIX_EVEX_0F3A15,
- PREFIX_EVEX_0F3A16,
- PREFIX_EVEX_0F3A17,
- PREFIX_EVEX_0F3A18,
- PREFIX_EVEX_0F3A19,
- PREFIX_EVEX_0F3A1A,
- PREFIX_EVEX_0F3A1B,
- PREFIX_EVEX_0F3A1D,
- PREFIX_EVEX_0F3A1E,
- PREFIX_EVEX_0F3A1F,
- PREFIX_EVEX_0F3A20,
- PREFIX_EVEX_0F3A21,
- PREFIX_EVEX_0F3A22,
- PREFIX_EVEX_0F3A23,
- PREFIX_EVEX_0F3A25,
- PREFIX_EVEX_0F3A26,
- PREFIX_EVEX_0F3A27,
- PREFIX_EVEX_0F3A38,
- PREFIX_EVEX_0F3A39,
- PREFIX_EVEX_0F3A3A,
- PREFIX_EVEX_0F3A3B,
- PREFIX_EVEX_0F3A3E,
- PREFIX_EVEX_0F3A3F,
- PREFIX_EVEX_0F3A42,
- PREFIX_EVEX_0F3A43,
- PREFIX_EVEX_0F3A44,
- PREFIX_EVEX_0F3A50,
- PREFIX_EVEX_0F3A51,
- PREFIX_EVEX_0F3A54,
- PREFIX_EVEX_0F3A55,
- PREFIX_EVEX_0F3A56,
- PREFIX_EVEX_0F3A57,
- PREFIX_EVEX_0F3A66,
- PREFIX_EVEX_0F3A67,
- PREFIX_EVEX_0F3A70,
- PREFIX_EVEX_0F3A71,
- PREFIX_EVEX_0F3A72,
- PREFIX_EVEX_0F3A73,
- PREFIX_EVEX_0F3ACE,
- PREFIX_EVEX_0F3ACF
};
enum
{
X86_64_06 = 0,
X86_64_07,
- X86_64_0D,
+ X86_64_0E,
X86_64_16,
X86_64_17,
X86_64_1E,
X86_64_6F,
X86_64_82,
X86_64_9A,
+ X86_64_C2,
+ X86_64_C3,
X86_64_C4,
X86_64_C5,
X86_64_CE,
X86_64_EA,
X86_64_0F01_REG_0,
X86_64_0F01_REG_1,
+ X86_64_0F01_REG_1_RM_5_PREFIX_2,
+ X86_64_0F01_REG_1_RM_6_PREFIX_2,
+ X86_64_0F01_REG_1_RM_7_PREFIX_2,
X86_64_0F01_REG_2,
- X86_64_0F01_REG_3
+ X86_64_0F01_REG_3,
+ X86_64_0F24,
+ X86_64_0F26,
+ X86_64_VEX_0F3849,
+ X86_64_VEX_0F384B,
+ X86_64_VEX_0F385C,
+ X86_64_VEX_0F385E,
+ X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
+ X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
+ X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
+ X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
+ X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
+ X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
+ X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
+ X86_64_0FC7_REG_6_MOD_3_PREFIX_1
};
enum
{
VEX_LEN_0F12_P_0_M_0 = 0,
VEX_LEN_0F12_P_0_M_1,
- VEX_LEN_0F12_P_2,
+#define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
VEX_LEN_0F13_M_0,
VEX_LEN_0F16_P_0_M_0,
VEX_LEN_0F16_P_0_M_1,
- VEX_LEN_0F16_P_2,
+#define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
VEX_LEN_0F17_M_0,
VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2,
VEX_LEN_0F4A_P_2,
VEX_LEN_0F4B_P_0,
VEX_LEN_0F4B_P_2,
- VEX_LEN_0F6E_P_2,
- VEX_LEN_0F77_P_0,
+ VEX_LEN_0F6E,
+ VEX_LEN_0F77,
VEX_LEN_0F7E_P_1,
VEX_LEN_0F7E_P_2,
VEX_LEN_0F90_P_0,
VEX_LEN_0F99_P_2,
VEX_LEN_0FAE_R_2_M_0,
VEX_LEN_0FAE_R_3_M_0,
- VEX_LEN_0FC4_P_2,
- VEX_LEN_0FC5_P_2,
- VEX_LEN_0FD6_P_2,
- VEX_LEN_0FF7_P_2,
- VEX_LEN_0F3816_P_2,
- VEX_LEN_0F3819_P_2,
- VEX_LEN_0F381A_P_2_M_0,
- VEX_LEN_0F3836_P_2,
- VEX_LEN_0F3841_P_2,
- VEX_LEN_0F385A_P_2_M_0,
- VEX_LEN_0F38DB_P_2,
- VEX_LEN_0F38F2_P_0,
- VEX_LEN_0F38F3_R_1_P_0,
- VEX_LEN_0F38F3_R_2_P_0,
- VEX_LEN_0F38F3_R_3_P_0,
+ VEX_LEN_0FC4,
+ VEX_LEN_0FC5,
+ VEX_LEN_0FD6,
+ VEX_LEN_0FF7,
+ VEX_LEN_0F3816,
+ VEX_LEN_0F3819,
+ VEX_LEN_0F381A_M_0,
+ VEX_LEN_0F3836,
+ VEX_LEN_0F3841,
+ VEX_LEN_0F3849_X86_64_P_0_W_0_M_0,
+ VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0,
+ VEX_LEN_0F3849_X86_64_P_2_W_0_M_0,
+ VEX_LEN_0F3849_X86_64_P_3_W_0_M_0,
+ VEX_LEN_0F384B_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F384B_X86_64_P_2_W_0_M_0,
+ VEX_LEN_0F384B_X86_64_P_3_W_0_M_0,
+ VEX_LEN_0F385A_M_0,
+ VEX_LEN_0F385C_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_0_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_1_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_2_W_0_M_0,
+ VEX_LEN_0F385E_X86_64_P_3_W_0_M_0,
+ VEX_LEN_0F38DB,
+ VEX_LEN_0F38F2,
+ VEX_LEN_0F38F3_R_1,
+ VEX_LEN_0F38F3_R_2,
+ VEX_LEN_0F38F3_R_3,
VEX_LEN_0F38F5_P_0,
VEX_LEN_0F38F5_P_1,
VEX_LEN_0F38F5_P_3,
VEX_LEN_0F38F7_P_1,
VEX_LEN_0F38F7_P_2,
VEX_LEN_0F38F7_P_3,
- VEX_LEN_0F3A00_P_2,
- VEX_LEN_0F3A01_P_2,
- VEX_LEN_0F3A06_P_2,
- VEX_LEN_0F3A14_P_2,
- VEX_LEN_0F3A15_P_2,
- VEX_LEN_0F3A16_P_2,
- VEX_LEN_0F3A17_P_2,
- VEX_LEN_0F3A18_P_2,
- VEX_LEN_0F3A19_P_2,
- VEX_LEN_0F3A20_P_2,
- VEX_LEN_0F3A21_P_2,
- VEX_LEN_0F3A22_P_2,
- VEX_LEN_0F3A30_P_2,
- VEX_LEN_0F3A31_P_2,
- VEX_LEN_0F3A32_P_2,
- VEX_LEN_0F3A33_P_2,
- VEX_LEN_0F3A38_P_2,
- VEX_LEN_0F3A39_P_2,
- VEX_LEN_0F3A41_P_2,
- VEX_LEN_0F3A46_P_2,
- VEX_LEN_0F3A60_P_2,
- VEX_LEN_0F3A61_P_2,
- VEX_LEN_0F3A62_P_2,
- VEX_LEN_0F3A63_P_2,
- VEX_LEN_0F3A6A_P_2,
- VEX_LEN_0F3A6B_P_2,
- VEX_LEN_0F3A6E_P_2,
- VEX_LEN_0F3A6F_P_2,
- VEX_LEN_0F3A7A_P_2,
- VEX_LEN_0F3A7B_P_2,
- VEX_LEN_0F3A7E_P_2,
- VEX_LEN_0F3A7F_P_2,
- VEX_LEN_0F3ADF_P_2,
+ VEX_LEN_0F3A00,
+ VEX_LEN_0F3A01,
+ VEX_LEN_0F3A06,
+ VEX_LEN_0F3A14,
+ VEX_LEN_0F3A15,
+ VEX_LEN_0F3A16,
+ VEX_LEN_0F3A17,
+ VEX_LEN_0F3A18,
+ VEX_LEN_0F3A19,
+ VEX_LEN_0F3A20,
+ VEX_LEN_0F3A21,
+ VEX_LEN_0F3A22,
+ VEX_LEN_0F3A30,
+ VEX_LEN_0F3A31,
+ VEX_LEN_0F3A32,
+ VEX_LEN_0F3A33,
+ VEX_LEN_0F3A38,
+ VEX_LEN_0F3A39,
+ VEX_LEN_0F3A41,
+ VEX_LEN_0F3A46,
+ VEX_LEN_0F3A60,
+ VEX_LEN_0F3A61,
+ VEX_LEN_0F3A62,
+ VEX_LEN_0F3A63,
+ VEX_LEN_0F3ADF,
VEX_LEN_0F3AF0_P_3,
+ VEX_LEN_0FXOP_08_85,
+ VEX_LEN_0FXOP_08_86,
+ VEX_LEN_0FXOP_08_87,
+ VEX_LEN_0FXOP_08_8E,
+ VEX_LEN_0FXOP_08_8F,
+ VEX_LEN_0FXOP_08_95,
+ VEX_LEN_0FXOP_08_96,
+ VEX_LEN_0FXOP_08_97,
+ VEX_LEN_0FXOP_08_9E,
+ VEX_LEN_0FXOP_08_9F,
+ VEX_LEN_0FXOP_08_A3,
+ VEX_LEN_0FXOP_08_A6,
+ VEX_LEN_0FXOP_08_B6,
+ VEX_LEN_0FXOP_08_C0,
+ VEX_LEN_0FXOP_08_C1,
+ VEX_LEN_0FXOP_08_C2,
+ VEX_LEN_0FXOP_08_C3,
VEX_LEN_0FXOP_08_CC,
VEX_LEN_0FXOP_08_CD,
VEX_LEN_0FXOP_08_CE,
VEX_LEN_0FXOP_08_ED,
VEX_LEN_0FXOP_08_EE,
VEX_LEN_0FXOP_08_EF,
- VEX_LEN_0FXOP_09_80,
- VEX_LEN_0FXOP_09_81
+ VEX_LEN_0FXOP_09_01,
+ VEX_LEN_0FXOP_09_02,
+ VEX_LEN_0FXOP_09_12_M_1,
+ VEX_LEN_0FXOP_09_82_W_0,
+ VEX_LEN_0FXOP_09_83_W_0,
+ VEX_LEN_0FXOP_09_90,
+ VEX_LEN_0FXOP_09_91,
+ VEX_LEN_0FXOP_09_92,
+ VEX_LEN_0FXOP_09_93,
+ VEX_LEN_0FXOP_09_94,
+ VEX_LEN_0FXOP_09_95,
+ VEX_LEN_0FXOP_09_96,
+ VEX_LEN_0FXOP_09_97,
+ VEX_LEN_0FXOP_09_98,
+ VEX_LEN_0FXOP_09_99,
+ VEX_LEN_0FXOP_09_9A,
+ VEX_LEN_0FXOP_09_9B,
+ VEX_LEN_0FXOP_09_C1,
+ VEX_LEN_0FXOP_09_C2,
+ VEX_LEN_0FXOP_09_C3,
+ VEX_LEN_0FXOP_09_C6,
+ VEX_LEN_0FXOP_09_C7,
+ VEX_LEN_0FXOP_09_CB,
+ VEX_LEN_0FXOP_09_D1,
+ VEX_LEN_0FXOP_09_D2,
+ VEX_LEN_0FXOP_09_D3,
+ VEX_LEN_0FXOP_09_D6,
+ VEX_LEN_0FXOP_09_D7,
+ VEX_LEN_0FXOP_09_DB,
+ VEX_LEN_0FXOP_09_E1,
+ VEX_LEN_0FXOP_09_E2,
+ VEX_LEN_0FXOP_09_E3,
+ VEX_LEN_0FXOP_0A_12,
};
enum
{
- EVEX_LEN_0F6E_P_2 = 0,
+ EVEX_LEN_0F6E = 0,
EVEX_LEN_0F7E_P_1,
EVEX_LEN_0F7E_P_2,
- EVEX_LEN_0FD6_P_2,
- EVEX_LEN_0F3819_P_2_W_0,
- EVEX_LEN_0F3819_P_2_W_1,
- EVEX_LEN_0F381A_P_2_W_0,
- EVEX_LEN_0F381A_P_2_W_1,
- EVEX_LEN_0F381B_P_2_W_0,
- EVEX_LEN_0F381B_P_2_W_1,
- EVEX_LEN_0F385A_P_2_W_0,
- EVEX_LEN_0F385A_P_2_W_1,
- EVEX_LEN_0F385B_P_2_W_0,
- EVEX_LEN_0F385B_P_2_W_1,
- EVEX_LEN_0F38C6_REG_1_PREFIX_2,
- EVEX_LEN_0F38C6_REG_2_PREFIX_2,
- EVEX_LEN_0F38C6_REG_5_PREFIX_2,
- EVEX_LEN_0F38C6_REG_6_PREFIX_2,
- EVEX_LEN_0F38C7_R_1_P_2_W_0,
- EVEX_LEN_0F38C7_R_1_P_2_W_1,
- EVEX_LEN_0F38C7_R_2_P_2_W_0,
- EVEX_LEN_0F38C7_R_2_P_2_W_1,
- EVEX_LEN_0F38C7_R_5_P_2_W_0,
- EVEX_LEN_0F38C7_R_5_P_2_W_1,
- EVEX_LEN_0F38C7_R_6_P_2_W_0,
- EVEX_LEN_0F38C7_R_6_P_2_W_1,
- EVEX_LEN_0F3A18_P_2_W_0,
- EVEX_LEN_0F3A18_P_2_W_1,
- EVEX_LEN_0F3A19_P_2_W_0,
- EVEX_LEN_0F3A19_P_2_W_1,
- EVEX_LEN_0F3A1A_P_2_W_0,
- EVEX_LEN_0F3A1A_P_2_W_1,
- EVEX_LEN_0F3A1B_P_2_W_0,
- EVEX_LEN_0F3A1B_P_2_W_1,
- EVEX_LEN_0F3A23_P_2_W_0,
- EVEX_LEN_0F3A23_P_2_W_1,
- EVEX_LEN_0F3A38_P_2_W_0,
- EVEX_LEN_0F3A38_P_2_W_1,
- EVEX_LEN_0F3A39_P_2_W_0,
- EVEX_LEN_0F3A39_P_2_W_1,
- EVEX_LEN_0F3A3A_P_2_W_0,
- EVEX_LEN_0F3A3A_P_2_W_1,
- EVEX_LEN_0F3A3B_P_2_W_0,
- EVEX_LEN_0F3A3B_P_2_W_1,
- EVEX_LEN_0F3A43_P_2_W_0,
- EVEX_LEN_0F3A43_P_2_W_1
+ EVEX_LEN_0FC4,
+ EVEX_LEN_0FC5,
+ EVEX_LEN_0FD6,
+ EVEX_LEN_0F3816,
+ EVEX_LEN_0F3819_W_0,
+ EVEX_LEN_0F3819_W_1,
+ EVEX_LEN_0F381A_W_0_M_0,
+ EVEX_LEN_0F381A_W_1_M_0,
+ EVEX_LEN_0F381B_W_0_M_0,
+ EVEX_LEN_0F381B_W_1_M_0,
+ EVEX_LEN_0F3836,
+ EVEX_LEN_0F385A_W_0_M_0,
+ EVEX_LEN_0F385A_W_1_M_0,
+ EVEX_LEN_0F385B_W_0_M_0,
+ EVEX_LEN_0F385B_W_1_M_0,
+ EVEX_LEN_0F38C6_R_1_M_0,
+ EVEX_LEN_0F38C6_R_2_M_0,
+ EVEX_LEN_0F38C6_R_5_M_0,
+ EVEX_LEN_0F38C6_R_6_M_0,
+ EVEX_LEN_0F38C7_R_1_M_0_W_0,
+ EVEX_LEN_0F38C7_R_1_M_0_W_1,
+ EVEX_LEN_0F38C7_R_2_M_0_W_0,
+ EVEX_LEN_0F38C7_R_2_M_0_W_1,
+ EVEX_LEN_0F38C7_R_5_M_0_W_0,
+ EVEX_LEN_0F38C7_R_5_M_0_W_1,
+ EVEX_LEN_0F38C7_R_6_M_0_W_0,
+ EVEX_LEN_0F38C7_R_6_M_0_W_1,
+ EVEX_LEN_0F3A00_W_1,
+ EVEX_LEN_0F3A01_W_1,
+ EVEX_LEN_0F3A14,
+ EVEX_LEN_0F3A15,
+ EVEX_LEN_0F3A16,
+ EVEX_LEN_0F3A17,
+ EVEX_LEN_0F3A18_W_0,
+ EVEX_LEN_0F3A18_W_1,
+ EVEX_LEN_0F3A19_W_0,
+ EVEX_LEN_0F3A19_W_1,
+ EVEX_LEN_0F3A1A_W_0,
+ EVEX_LEN_0F3A1A_W_1,
+ EVEX_LEN_0F3A1B_W_0,
+ EVEX_LEN_0F3A1B_W_1,
+ EVEX_LEN_0F3A20,
+ EVEX_LEN_0F3A21_W_0,
+ EVEX_LEN_0F3A22,
+ EVEX_LEN_0F3A23_W_0,
+ EVEX_LEN_0F3A23_W_1,
+ EVEX_LEN_0F3A38_W_0,
+ EVEX_LEN_0F3A38_W_1,
+ EVEX_LEN_0F3A39_W_0,
+ EVEX_LEN_0F3A39_W_1,
+ EVEX_LEN_0F3A3A_W_0,
+ EVEX_LEN_0F3A3A_W_1,
+ EVEX_LEN_0F3A3B_W_0,
+ EVEX_LEN_0F3A3B_W_1,
+ EVEX_LEN_0F3A43_W_0,
+ EVEX_LEN_0F3A43_W_1
};
enum
VEX_W_0F98_P_2_LEN_0,
VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0,
- VEX_W_0F380C_P_2,
- VEX_W_0F380D_P_2,
- VEX_W_0F380E_P_2,
- VEX_W_0F380F_P_2,
- VEX_W_0F3816_P_2,
- VEX_W_0F3818_P_2,
- VEX_W_0F3819_P_2,
- VEX_W_0F381A_P_2_M_0,
- VEX_W_0F382C_P_2_M_0,
- VEX_W_0F382D_P_2_M_0,
- VEX_W_0F382E_P_2_M_0,
- VEX_W_0F382F_P_2_M_0,
- VEX_W_0F3836_P_2,
- VEX_W_0F3846_P_2,
- VEX_W_0F3858_P_2,
- VEX_W_0F3859_P_2,
- VEX_W_0F385A_P_2_M_0,
- VEX_W_0F3878_P_2,
- VEX_W_0F3879_P_2,
- VEX_W_0F38CF_P_2,
- VEX_W_0F3A00_P_2,
- VEX_W_0F3A01_P_2,
- VEX_W_0F3A02_P_2,
- VEX_W_0F3A04_P_2,
- VEX_W_0F3A05_P_2,
- VEX_W_0F3A06_P_2,
- VEX_W_0F3A18_P_2,
- VEX_W_0F3A19_P_2,
- VEX_W_0F3A30_P_2_LEN_0,
- VEX_W_0F3A31_P_2_LEN_0,
- VEX_W_0F3A32_P_2_LEN_0,
- VEX_W_0F3A33_P_2_LEN_0,
- VEX_W_0F3A38_P_2,
- VEX_W_0F3A39_P_2,
- VEX_W_0F3A46_P_2,
- VEX_W_0F3A48_P_2,
- VEX_W_0F3A49_P_2,
- VEX_W_0F3A4A_P_2,
- VEX_W_0F3A4B_P_2,
- VEX_W_0F3A4C_P_2,
- VEX_W_0F3ACE_P_2,
- VEX_W_0F3ACF_P_2,
-
- EVEX_W_0F10_P_0,
- EVEX_W_0F10_P_1_M_0,
- EVEX_W_0F10_P_1_M_1,
- EVEX_W_0F10_P_2,
- EVEX_W_0F10_P_3_M_0,
- EVEX_W_0F10_P_3_M_1,
- EVEX_W_0F11_P_0,
- EVEX_W_0F11_P_1_M_0,
- EVEX_W_0F11_P_1_M_1,
- EVEX_W_0F11_P_2,
- EVEX_W_0F11_P_3_M_0,
- EVEX_W_0F11_P_3_M_1,
- EVEX_W_0F12_P_0_M_0,
+ VEX_W_0F380C,
+ VEX_W_0F380D,
+ VEX_W_0F380E,
+ VEX_W_0F380F,
+ VEX_W_0F3813,
+ VEX_W_0F3816_L_1,
+ VEX_W_0F3818,
+ VEX_W_0F3819_L_1,
+ VEX_W_0F381A_M_0_L_1,
+ VEX_W_0F382C_M_0,
+ VEX_W_0F382D_M_0,
+ VEX_W_0F382E_M_0,
+ VEX_W_0F382F_M_0,
+ VEX_W_0F3836,
+ VEX_W_0F3846,
+ VEX_W_0F3849_X86_64_P_0,
+ VEX_W_0F3849_X86_64_P_2,
+ VEX_W_0F3849_X86_64_P_3,
+ VEX_W_0F384B_X86_64_P_1,
+ VEX_W_0F384B_X86_64_P_2,
+ VEX_W_0F384B_X86_64_P_3,
+ VEX_W_0F3850,
+ VEX_W_0F3851,
+ VEX_W_0F3852,
+ VEX_W_0F3853,
+ VEX_W_0F3858,
+ VEX_W_0F3859,
+ VEX_W_0F385A_M_0_L_0,
+ VEX_W_0F385C_X86_64_P_1,
+ VEX_W_0F385E_X86_64_P_0,
+ VEX_W_0F385E_X86_64_P_1,
+ VEX_W_0F385E_X86_64_P_2,
+ VEX_W_0F385E_X86_64_P_3,
+ VEX_W_0F3878,
+ VEX_W_0F3879,
+ VEX_W_0F38CF,
+ VEX_W_0F3A00_L_1,
+ VEX_W_0F3A01_L_1,
+ VEX_W_0F3A02,
+ VEX_W_0F3A04,
+ VEX_W_0F3A05,
+ VEX_W_0F3A06_L_1,
+ VEX_W_0F3A18_L_1,
+ VEX_W_0F3A19_L_1,
+ VEX_W_0F3A1D,
+ VEX_W_0F3A38_L_1,
+ VEX_W_0F3A39_L_1,
+ VEX_W_0F3A46_L_1,
+ VEX_W_0F3A4A,
+ VEX_W_0F3A4B,
+ VEX_W_0F3A4C,
+ VEX_W_0F3ACE,
+ VEX_W_0F3ACF,
+
+ VEX_W_0FXOP_08_85_L_0,
+ VEX_W_0FXOP_08_86_L_0,
+ VEX_W_0FXOP_08_87_L_0,
+ VEX_W_0FXOP_08_8E_L_0,
+ VEX_W_0FXOP_08_8F_L_0,
+ VEX_W_0FXOP_08_95_L_0,
+ VEX_W_0FXOP_08_96_L_0,
+ VEX_W_0FXOP_08_97_L_0,
+ VEX_W_0FXOP_08_9E_L_0,
+ VEX_W_0FXOP_08_9F_L_0,
+ VEX_W_0FXOP_08_A6_L_0,
+ VEX_W_0FXOP_08_B6_L_0,
+ VEX_W_0FXOP_08_C0_L_0,
+ VEX_W_0FXOP_08_C1_L_0,
+ VEX_W_0FXOP_08_C2_L_0,
+ VEX_W_0FXOP_08_C3_L_0,
+ VEX_W_0FXOP_08_CC_L_0,
+ VEX_W_0FXOP_08_CD_L_0,
+ VEX_W_0FXOP_08_CE_L_0,
+ VEX_W_0FXOP_08_CF_L_0,
+ VEX_W_0FXOP_08_EC_L_0,
+ VEX_W_0FXOP_08_ED_L_0,
+ VEX_W_0FXOP_08_EE_L_0,
+ VEX_W_0FXOP_08_EF_L_0,
+
+ VEX_W_0FXOP_09_80,
+ VEX_W_0FXOP_09_81,
+ VEX_W_0FXOP_09_82,
+ VEX_W_0FXOP_09_83,
+ VEX_W_0FXOP_09_C1_L_0,
+ VEX_W_0FXOP_09_C2_L_0,
+ VEX_W_0FXOP_09_C3_L_0,
+ VEX_W_0FXOP_09_C6_L_0,
+ VEX_W_0FXOP_09_C7_L_0,
+ VEX_W_0FXOP_09_CB_L_0,
+ VEX_W_0FXOP_09_D1_L_0,
+ VEX_W_0FXOP_09_D2_L_0,
+ VEX_W_0FXOP_09_D3_L_0,
+ VEX_W_0FXOP_09_D6_L_0,
+ VEX_W_0FXOP_09_D7_L_0,
+ VEX_W_0FXOP_09_DB_L_0,
+ VEX_W_0FXOP_09_E1_L_0,
+ VEX_W_0FXOP_09_E2_L_0,
+ VEX_W_0FXOP_09_E3_L_0,
+
+ EVEX_W_0F10_P_1,
+ EVEX_W_0F10_P_3,
+ EVEX_W_0F11_P_1,
+ EVEX_W_0F11_P_3,
EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_2,
EVEX_W_0F12_P_3,
- EVEX_W_0F13_P_0,
- EVEX_W_0F13_P_2,
- EVEX_W_0F14_P_0,
- EVEX_W_0F14_P_2,
- EVEX_W_0F15_P_0,
- EVEX_W_0F15_P_2,
- EVEX_W_0F16_P_0_M_0,
EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1,
- EVEX_W_0F16_P_2,
- EVEX_W_0F17_P_0,
- EVEX_W_0F17_P_2,
- EVEX_W_0F28_P_0,
- EVEX_W_0F28_P_2,
- EVEX_W_0F29_P_0,
- EVEX_W_0F29_P_2,
EVEX_W_0F2A_P_3,
- EVEX_W_0F2B_P_0,
- EVEX_W_0F2B_P_2,
- EVEX_W_0F2E_P_0,
- EVEX_W_0F2E_P_2,
- EVEX_W_0F2F_P_0,
- EVEX_W_0F2F_P_2,
- EVEX_W_0F51_P_0,
EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_2,
EVEX_W_0F51_P_3,
- EVEX_W_0F54_P_0,
- EVEX_W_0F54_P_2,
- EVEX_W_0F55_P_0,
- EVEX_W_0F55_P_2,
- EVEX_W_0F56_P_0,
- EVEX_W_0F56_P_2,
- EVEX_W_0F57_P_0,
- EVEX_W_0F57_P_2,
- EVEX_W_0F58_P_0,
EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_2,
EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_0,
EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_2,
EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0,
EVEX_W_0F5A_P_1,
EVEX_W_0F5B_P_0,
EVEX_W_0F5B_P_1,
EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_2,
EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_2,
EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_2,
EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_2,
EVEX_W_0F5F_P_3,
- EVEX_W_0F62_P_2,
- EVEX_W_0F66_P_2,
- EVEX_W_0F6A_P_2,
- EVEX_W_0F6B_P_2,
- EVEX_W_0F6C_P_2,
- EVEX_W_0F6D_P_2,
+ EVEX_W_0F62,
+ EVEX_W_0F66,
+ EVEX_W_0F6A,
+ EVEX_W_0F6B,
+ EVEX_W_0F6C,
+ EVEX_W_0F6D,
EVEX_W_0F6F_P_1,
EVEX_W_0F6F_P_2,
EVEX_W_0F6F_P_3,
EVEX_W_0F70_P_2,
- EVEX_W_0F72_R_2_P_2,
- EVEX_W_0F72_R_6_P_2,
- EVEX_W_0F73_R_2_P_2,
- EVEX_W_0F73_R_6_P_2,
- EVEX_W_0F76_P_2,
+ EVEX_W_0F72_R_2,
+ EVEX_W_0F72_R_6,
+ EVEX_W_0F73_R_2,
+ EVEX_W_0F73_R_6,
+ EVEX_W_0F76,
EVEX_W_0F78_P_0,
EVEX_W_0F78_P_2,
EVEX_W_0F79_P_0,
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_0,
EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3,
- EVEX_W_0FC6_P_0,
- EVEX_W_0FC6_P_2,
- EVEX_W_0FD2_P_2,
- EVEX_W_0FD3_P_2,
- EVEX_W_0FD4_P_2,
- EVEX_W_0FD6_P_2,
+ EVEX_W_0FD2,
+ EVEX_W_0FD3,
+ EVEX_W_0FD4,
+ EVEX_W_0FD6_L_0,
EVEX_W_0FE6_P_1,
EVEX_W_0FE6_P_2,
EVEX_W_0FE6_P_3,
- EVEX_W_0FE7_P_2,
- EVEX_W_0FF2_P_2,
- EVEX_W_0FF3_P_2,
- EVEX_W_0FF4_P_2,
- EVEX_W_0FFA_P_2,
- EVEX_W_0FFB_P_2,
- EVEX_W_0FFE_P_2,
- EVEX_W_0F380C_P_2,
- EVEX_W_0F380D_P_2,
+ EVEX_W_0FE7,
+ EVEX_W_0FF2,
+ EVEX_W_0FF3,
+ EVEX_W_0FF4,
+ EVEX_W_0FFA,
+ EVEX_W_0FFB,
+ EVEX_W_0FFE,
+ EVEX_W_0F380D,
EVEX_W_0F3810_P_1,
EVEX_W_0F3810_P_2,
EVEX_W_0F3811_P_1,
EVEX_W_0F3813_P_2,
EVEX_W_0F3814_P_1,
EVEX_W_0F3815_P_1,
- EVEX_W_0F3818_P_2,
- EVEX_W_0F3819_P_2,
- EVEX_W_0F381A_P_2,
- EVEX_W_0F381B_P_2,
- EVEX_W_0F381E_P_2,
- EVEX_W_0F381F_P_2,
+ EVEX_W_0F3819,
+ EVEX_W_0F381A,
+ EVEX_W_0F381B,
+ EVEX_W_0F381E,
+ EVEX_W_0F381F,
EVEX_W_0F3820_P_1,
EVEX_W_0F3821_P_1,
EVEX_W_0F3822_P_1,
EVEX_W_0F3824_P_1,
EVEX_W_0F3825_P_1,
EVEX_W_0F3825_P_2,
- EVEX_W_0F3826_P_1,
- EVEX_W_0F3826_P_2,
- EVEX_W_0F3828_P_1,
EVEX_W_0F3828_P_2,
- EVEX_W_0F3829_P_1,
EVEX_W_0F3829_P_2,
EVEX_W_0F382A_P_1,
EVEX_W_0F382A_P_2,
- EVEX_W_0F382B_P_2,
+ EVEX_W_0F382B,
EVEX_W_0F3830_P_1,
EVEX_W_0F3831_P_1,
EVEX_W_0F3832_P_1,
EVEX_W_0F3834_P_1,
EVEX_W_0F3835_P_1,
EVEX_W_0F3835_P_2,
- EVEX_W_0F3837_P_2,
- EVEX_W_0F3838_P_1,
- EVEX_W_0F3839_P_1,
+ EVEX_W_0F3837,
EVEX_W_0F383A_P_1,
- EVEX_W_0F3840_P_2,
EVEX_W_0F3852_P_1,
- EVEX_W_0F3854_P_2,
- EVEX_W_0F3855_P_2,
- EVEX_W_0F3858_P_2,
- EVEX_W_0F3859_P_2,
- EVEX_W_0F385A_P_2,
- EVEX_W_0F385B_P_2,
- EVEX_W_0F3862_P_2,
- EVEX_W_0F3863_P_2,
- EVEX_W_0F3866_P_2,
- EVEX_W_0F3868_P_3,
- EVEX_W_0F3870_P_2,
- EVEX_W_0F3871_P_2,
+ EVEX_W_0F3859,
+ EVEX_W_0F385A,
+ EVEX_W_0F385B,
+ EVEX_W_0F3870,
EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
EVEX_W_0F3872_P_3,
- EVEX_W_0F3873_P_2,
- EVEX_W_0F3875_P_2,
- EVEX_W_0F3878_P_2,
- EVEX_W_0F3879_P_2,
- EVEX_W_0F387A_P_2,
- EVEX_W_0F387B_P_2,
- EVEX_W_0F387D_P_2,
- EVEX_W_0F3883_P_2,
- EVEX_W_0F388D_P_2,
- EVEX_W_0F3891_P_2,
- EVEX_W_0F3893_P_2,
- EVEX_W_0F38A1_P_2,
- EVEX_W_0F38A3_P_2,
- EVEX_W_0F38C7_R_1_P_2,
- EVEX_W_0F38C7_R_2_P_2,
- EVEX_W_0F38C7_R_5_P_2,
- EVEX_W_0F38C7_R_6_P_2,
-
- EVEX_W_0F3A00_P_2,
- EVEX_W_0F3A01_P_2,
- EVEX_W_0F3A04_P_2,
- EVEX_W_0F3A05_P_2,
- EVEX_W_0F3A08_P_2,
- EVEX_W_0F3A09_P_2,
- EVEX_W_0F3A0A_P_2,
- EVEX_W_0F3A0B_P_2,
- EVEX_W_0F3A18_P_2,
- EVEX_W_0F3A19_P_2,
- EVEX_W_0F3A1A_P_2,
- EVEX_W_0F3A1B_P_2,
- EVEX_W_0F3A1D_P_2,
- EVEX_W_0F3A21_P_2,
- EVEX_W_0F3A23_P_2,
- EVEX_W_0F3A38_P_2,
- EVEX_W_0F3A39_P_2,
- EVEX_W_0F3A3A_P_2,
- EVEX_W_0F3A3B_P_2,
- EVEX_W_0F3A3E_P_2,
- EVEX_W_0F3A3F_P_2,
- EVEX_W_0F3A42_P_2,
- EVEX_W_0F3A43_P_2,
- EVEX_W_0F3A50_P_2,
- EVEX_W_0F3A51_P_2,
- EVEX_W_0F3A56_P_2,
- EVEX_W_0F3A57_P_2,
- EVEX_W_0F3A66_P_2,
- EVEX_W_0F3A67_P_2,
- EVEX_W_0F3A70_P_2,
- EVEX_W_0F3A71_P_2,
- EVEX_W_0F3A72_P_2,
- EVEX_W_0F3A73_P_2,
- EVEX_W_0F3ACE_P_2,
- EVEX_W_0F3ACF_P_2
+ EVEX_W_0F387A,
+ EVEX_W_0F387B,
+ EVEX_W_0F3883,
+ EVEX_W_0F3891,
+ EVEX_W_0F3893,
+ EVEX_W_0F38A1,
+ EVEX_W_0F38A3,
+ EVEX_W_0F38C7_R_1_M_0,
+ EVEX_W_0F38C7_R_2_M_0,
+ EVEX_W_0F38C7_R_5_M_0,
+ EVEX_W_0F38C7_R_6_M_0,
+
+ EVEX_W_0F3A00,
+ EVEX_W_0F3A01,
+ EVEX_W_0F3A05,
+ EVEX_W_0F3A08,
+ EVEX_W_0F3A09,
+ EVEX_W_0F3A0A,
+ EVEX_W_0F3A0B,
+ EVEX_W_0F3A18,
+ EVEX_W_0F3A19,
+ EVEX_W_0F3A1A,
+ EVEX_W_0F3A1B,
+ EVEX_W_0F3A21,
+ EVEX_W_0F3A23,
+ EVEX_W_0F3A38,
+ EVEX_W_0F3A39,
+ EVEX_W_0F3A3A,
+ EVEX_W_0F3A3B,
+ EVEX_W_0F3A42,
+ EVEX_W_0F3A43,
+ EVEX_W_0F3A70,
+ EVEX_W_0F3A72,
};
typedef void (*op_rtn) (int bytemode, int sizeflag);
'F' => print 'w' or 'l' depending on address size prefix (loop insns)
'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
'H' => print ",pt" or ",pn" branch hint
- 'I' => honor following macro letter even in Intel mode (implemented only
- for some of the macro letters)
- 'J' => print 'l'
+ 'I' unused.
+ 'J' unused.
'K' => print 'd' or 'q' if rex prefix is present.
- 'L' => print 'l' if suffix_always is true
+ 'L' unused.
'M' => print 'r' if intel_mnemonic is false.
'N' => print 'n' if instruction has no wait "prefix"
'O' => print 'd' or 'o' (or 'q' in Intel mode)
- 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix,
- or suffix_always is true. print 'q' if rex prefix is present.
+ 'P' => behave as 'T' except with register operand outside of suffix_always
+ mode
'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
is true
'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
'S' => print 'w', 'l' or 'q' if suffix_always is true
- 'T' => print 'q' in 64bit mode if instruction has no operand size
- prefix and behave as 'P' otherwise
- 'U' => print 'q' in 64bit mode if instruction has no operand size
- prefix and behave as 'Q' otherwise
- 'V' => print 'q' in 64bit mode if instruction has no operand size
- prefix and behave as 'S' otherwise
+ 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
+ prefix or if suffix_always is true.
+ 'U' unused.
+ 'V' unused.
'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
'Y' unused.
- 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
+ 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
- '^' => print 'w' or 'l' depending on operand size prefix or
- suffix_always is true (lcall/ljmp).
- '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
- on operand size prefix.
- '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
- has no operand size prefix for AMD64 ISA, behave as 'P'
- otherwise
+ '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
+ prefix or suffix_always is true (lcall/ljmp).
+ '@' => in 64bit mode for Intel64 ISA or if instruction
+ has no operand sizing prefix, print 'q' if suffix_always is true or
+ nothing otherwise; behave as 'P' in all other cases
2 upper case letter macros:
"XY" => print 'x' or 'y' if suffix_always is true or no register
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
- "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
- or suffix_always is true
+ "XV" => print "{vex3}" pseudo prefix
+ "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
+ being false, or no operand at all in 64bit mode, or if suffix_always
+ is true.
"LB" => print "abs" in 64bit mode and behave as 'B' otherwise
"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
"LV" => print "abs" for 64bit operand and behave as 'S' otherwise
- "LW" => print 'd', 'q' depending on the VEX.W bit
+ "DQ" => print 'd' or 'q' depending on the VEX.W bit
+ "BW" => print 'b' or 'w' depending on the VEX.W bit
"LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
an operand size prefix, or suffix_always is true. print
'q' if rex prefix is present.
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
- { X86_64_TABLE (X86_64_0D) },
+ { X86_64_TABLE (X86_64_0E) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
{ "dec{S|}", { RMeSI }, 0 },
{ "dec{S|}", { RMeDI }, 0 },
/* 50 */
- { "pushV", { RMrAX }, 0 },
- { "pushV", { RMrCX }, 0 },
- { "pushV", { RMrDX }, 0 },
- { "pushV", { RMrBX }, 0 },
- { "pushV", { RMrSP }, 0 },
- { "pushV", { RMrBP }, 0 },
- { "pushV", { RMrSI }, 0 },
- { "pushV", { RMrDI }, 0 },
+ { "push{!P|}", { RMrAX }, 0 },
+ { "push{!P|}", { RMrCX }, 0 },
+ { "push{!P|}", { RMrDX }, 0 },
+ { "push{!P|}", { RMrBX }, 0 },
+ { "push{!P|}", { RMrSP }, 0 },
+ { "push{!P|}", { RMrBP }, 0 },
+ { "push{!P|}", { RMrSI }, 0 },
+ { "push{!P|}", { RMrDI }, 0 },
/* 58 */
- { "popV", { RMrAX }, 0 },
- { "popV", { RMrCX }, 0 },
- { "popV", { RMrDX }, 0 },
- { "popV", { RMrBX }, 0 },
- { "popV", { RMrSP }, 0 },
- { "popV", { RMrBP }, 0 },
- { "popV", { RMrSI }, 0 },
- { "popV", { RMrDI }, 0 },
+ { "pop{!P|}", { RMrAX }, 0 },
+ { "pop{!P|}", { RMrCX }, 0 },
+ { "pop{!P|}", { RMrDX }, 0 },
+ { "pop{!P|}", { RMrBX }, 0 },
+ { "pop{!P|}", { RMrSP }, 0 },
+ { "pop{!P|}", { RMrBP }, 0 },
+ { "pop{!P|}", { RMrSI }, 0 },
+ { "pop{!P|}", { RMrDI }, 0 },
/* 60 */
{ X86_64_TABLE (X86_64_60) },
{ X86_64_TABLE (X86_64_61) },
{ Bad_Opcode }, /* op size prefix */
{ Bad_Opcode }, /* adr size prefix */
/* 68 */
- { "pushT", { sIv }, 0 },
+ { "pushP", { sIv }, 0 },
{ "imulS", { Gv, Ev, Iv }, 0 },
- { "pushT", { sIbT }, 0 },
+ { "pushP", { sIbT }, 0 },
{ "imulS", { Gv, Ev, sIb }, 0 },
{ "ins{b|}", { Ybr, indirDX }, 0 },
{ X86_64_TABLE (X86_64_6D) },
{ "cR{t|}O", { XX }, 0 },
{ X86_64_TABLE (X86_64_9A) },
{ Bad_Opcode }, /* fwait */
- { "pushfT", { XX }, 0 },
- { "popfT", { XX }, 0 },
+ { "pushfP", { XX }, 0 },
+ { "popfP", { XX }, 0 },
{ "sahf", { XX }, 0 },
{ "lahf", { XX }, 0 },
/* a0 */
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- { "retT", { Iw, BND }, 0 },
- { "retT", { BND }, 0 },
+ { X86_64_TABLE (X86_64_C2) },
+ { X86_64_TABLE (X86_64_C3) },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
{ REG_TABLE (REG_C7) },
/* c8 */
- { "enterT", { Iw, Ib }, 0 },
- { "leaveT", { XX }, 0 },
- { "Jret{|f}P", { Iw }, 0 },
- { "Jret{|f}P", { XX }, 0 },
+ { "enterP", { Iw, Ib }, 0 },
+ { "leaveP", { XX }, 0 },
+ { "{l|}ret{|f}%LP", { Iw }, 0 },
+ { "{l|}ret{|f}%LP", { XX }, 0 },
{ "int3", { XX }, 0 },
{ "int", { Ib }, 0 },
{ X86_64_TABLE (X86_64_CE) },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
- { "sysret%LP", { XX }, 0 },
+ { "sysret%LQ", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
{ PREFIX_TABLE (PREFIX_0F09) },
{ PREFIX_TABLE (PREFIX_0F1E) },
{ "nopQ", { Ev }, 0 },
/* 20 */
- { "movZ", { Rm, Cm }, 0 },
- { "movZ", { Rm, Dm }, 0 },
- { "movZ", { Cm, Rm }, 0 },
- { "movZ", { Dm, Rm }, 0 },
- { MOD_TABLE (MOD_0F24) },
+ { "movZ", { Em, Cm }, 0 },
+ { "movZ", { Em, Dm }, 0 },
+ { "movZ", { Cm, Em }, 0 },
+ { "movZ", { Dm, Em }, 0 },
+ { X86_64_TABLE (X86_64_0F24) },
{ Bad_Opcode },
- { MOD_TABLE (MOD_0F26) },
+ { X86_64_TABLE (X86_64_0F26) },
{ Bad_Opcode },
/* 28 */
{ "movapX", { XM, EXx }, PREFIX_OPCODE },
{ "rdtsc", { XX }, 0 },
{ "rdmsr", { XX }, 0 },
{ "rdpmc", { XX }, 0 },
- { "sysenter", { XX }, 0 },
- { "sysexit", { XX }, 0 },
+ { "sysenter", { SEP }, 0 },
+ { "sysexit", { SEP }, 0 },
{ Bad_Opcode },
{ "getsec", { XX }, 0 },
/* 38 */
{ "cmovleS", { Gv, Ev }, 0 },
{ "cmovgS", { Gv, Ev }, 0 },
/* 50 */
- { MOD_TABLE (MOD_0F51) },
+ { MOD_TABLE (MOD_0F50) },
{ PREFIX_TABLE (PREFIX_0F51) },
{ PREFIX_TABLE (PREFIX_0F52) },
{ PREFIX_TABLE (PREFIX_0F53) },
{ "punpckhwd", { MX, EM }, PREFIX_OPCODE },
{ "punpckhdq", { MX, EM }, PREFIX_OPCODE },
{ "packssdw", { MX, EM }, PREFIX_OPCODE },
- { PREFIX_TABLE (PREFIX_0F6C) },
- { PREFIX_TABLE (PREFIX_0F6D) },
+ { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
+ { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
{ "movK", { MX, Edq }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_0F6F) },
/* 70 */
{ "setle", { Eb }, 0 },
{ "setg", { Eb }, 0 },
/* a0 */
- { "pushT", { fs }, 0 },
- { "popT", { fs }, 0 },
+ { "pushP", { fs }, 0 },
+ { "popP", { fs }, 0 },
{ "cpuid", { XX }, 0 },
{ "btS", { Ev, Gv }, 0 },
{ "shldS", { Ev, Gv, Ib }, 0 },
{ REG_TABLE (REG_0FA6) },
{ REG_TABLE (REG_0FA7) },
/* a8 */
- { "pushT", { gs }, 0 },
- { "popT", { gs }, 0 },
+ { "pushP", { gs }, 0 },
+ { "popP", { gs }, 0 },
{ "rsm", { XX }, 0 },
{ "btsS", { Evh1, Gv }, 0 },
{ "shrdS", { Ev, Gv, Ib }, 0 },
}
vex;
static unsigned char need_vex;
-static unsigned char need_vex_reg;
-static unsigned char vex_w_done;
struct op
{
"%zmm28", "%zmm29", "%zmm30", "%zmm31"
};
+static const char **names_tmm;
+static const char *intel_names_tmm[] = {
+ "tmm0", "tmm1", "tmm2", "tmm3",
+ "tmm4", "tmm5", "tmm6", "tmm7"
+};
+static const char *att_names_tmm[] = {
+ "%tmm0", "%tmm1", "%tmm2", "%tmm3",
+ "%tmm4", "%tmm5", "%tmm6", "%tmm7"
+};
+
static const char **names_mask;
static const char *intel_names_mask[] = {
"k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7"
},
/* REG_8F */
{
- { "popU", { stackEv }, 0 },
+ { "pop{P|}", { stackEv }, 0 },
{ XOP_8F_TABLE (XOP_09) },
{ Bad_Opcode },
{ Bad_Opcode },
{
{ "incQ", { Evh1 }, 0 },
{ "decQ", { Evh1 }, 0 },
- { "call{&|}", { NOTRACK, indirEv, BND }, 0 },
+ { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
{ MOD_TABLE (MOD_FF_REG_3) },
- { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 },
+ { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
{ MOD_TABLE (MOD_FF_REG_5) },
- { "pushU", { stackEv }, 0 },
+ { "push{P|}", { stackEv }, 0 },
{ Bad_Opcode },
},
/* REG_0F00 */
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
- /* REG_0F1C_MOD_0 */
+ /* REG_0F1C_P_0_MOD_0 */
{
{ "cldemote", { Mb }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
},
- /* REG_0F1E_MOD_3 */
+ /* REG_0F1E_P_1_MOD_3 */
{
{ "nopQ", { Ev }, 0 },
- { "rdsspK", { Rdq }, PREFIX_OPCODE },
+ { "rdsspK", { Edq }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
+ { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
+ },
+ /* REG_0F38D8_PREFIX_1 */
+ {
+ { "aesencwide128kl", { M }, 0 },
+ { "aesdecwide128kl", { M }, 0 },
+ { "aesencwide256kl", { M }, 0 },
+ { "aesdecwide256kl", { M }, 0 },
+ },
+ /* REG_0F3A0F_PREFIX_1_MOD_3 */
+ {
+ { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) },
},
/* REG_0F71 */
{
{ MOD_TABLE (MOD_VEX_0FAE_REG_2) },
{ MOD_TABLE (MOD_VEX_0FAE_REG_3) },
},
- /* REG_VEX_0F38F3 */
- {
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) },
- { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) },
- { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) },
- },
- /* REG_XOP_LWPCB */
+ /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */
{
- { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 },
- { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 },
+ { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) },
},
- /* REG_XOP_LWP */
+ /* REG_VEX_0F38F3 */
{
- { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
- { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) },
},
- /* REG_XOP_TBM_01 */
+ /* REG_0FXOP_09_01_L_0 */
{
{ Bad_Opcode },
- { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 },
- { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 },
- { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 },
- { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
- { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 },
- { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 },
- { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blcfill", { VexGdq, Edq }, 0 },
+ { "blsfill", { VexGdq, Edq }, 0 },
+ { "blcs", { VexGdq, Edq }, 0 },
+ { "tzmsk", { VexGdq, Edq }, 0 },
+ { "blcic", { VexGdq, Edq }, 0 },
+ { "blsic", { VexGdq, Edq }, 0 },
+ { "t1mskc", { VexGdq, Edq }, 0 },
},
- /* REG_XOP_TBM_02 */
+ /* REG_0FXOP_09_02_L_0 */
{
{ Bad_Opcode },
- { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blcmsk", { VexGdq, Edq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "blci", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blci", { VexGdq, Edq }, 0 },
+ },
+ /* REG_0FXOP_09_12_M_1_L_0 */
+ {
+ { "llwpcb", { Edq }, 0 },
+ { "slwpcb", { Edq }, 0 },
+ },
+ /* REG_0FXOP_0A_12_L_0 */
+ {
+ { "lwpins", { VexGdq, Ed, Id }, 0 },
+ { "lwpval", { VexGdq, Ed, Id }, 0 },
},
#include "i386-dis-evex-reg.h"
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
- /* PREFIX_MOD_0_0F01_REG_5 */
+ /* PREFIX_0F01_REG_1_RM_4 */
{
{ Bad_Opcode },
- { "rstorssp", { Mq }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { "tdcall", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_0F01_REG_1_RM_5 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_0F01_REG_1_RM_6 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_0F01_REG_1_RM_7 */
+ {
+ { "encls", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
+ { Bad_Opcode },
+ },
+
+ /* PREFIX_0F01_REG_3_RM_1 */
+ {
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmgexit", { Skip_MODRM }, 0 },
+ { Bad_Opcode },
+ { "vmgexit", { Skip_MODRM }, 0 },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
+ /* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
+ { "rstorssp", { Mq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
+ {
+ { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
+ /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
{
{ Bad_Opcode },
{ "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
},
+ /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
+ {
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
+ {
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
+ {
+ { "rdpkru", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
+ {
+ { "wrpkru", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
+ },
+
+ /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
+ {
+ { "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mcommit", { Skip_MODRM }, 0 },
+ },
+
+ /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
+ {
+ { "invlpgb", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
+ { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
+ },
+
+ /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
+ {
+ { "tlbsync", { Skip_MODRM }, 0 },
+ { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
+ { Bad_Opcode },
+ { "pvalidate", { Skip_MODRM }, 0 },
+ },
+
/* PREFIX_0F09 */
{
{ "wbinvd", { XX }, 0 },
{
{ MOD_TABLE (MOD_0F12_PREFIX_0) },
{ "movsldup", { XM, EXx }, PREFIX_OPCODE },
- { "movlpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F12_PREFIX_2) },
{ "movddup", { XM, EXq }, PREFIX_OPCODE },
},
{
{ MOD_TABLE (MOD_0F16_PREFIX_0) },
{ "movshdup", { XM, EXx }, PREFIX_OPCODE },
- { "movhpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F16_PREFIX_2) },
},
/* PREFIX_0F1A */
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
+ { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
{ "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2sd%LQ", { XM, Edq }, 0 },
+ { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
},
/* PREFIX_0F2B */
{ "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
},
- /* PREFIX_0F6C */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE },
- },
-
- /* PREFIX_0F6D */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE },
- },
-
/* PREFIX_0F6F */
{
{ "movq", { MX, EM }, PREFIX_OPCODE },
{ "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
},
- /* PREFIX_0F73_REG_3 */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { "psrldq", { XS, Ib }, 0 },
- },
-
- /* PREFIX_0F73_REG_7 */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { "pslldq", { XS, Ib }, 0 },
- },
-
/* PREFIX_0F78 */
{
{"vmread", { Em, Gm }, 0 },
{ "movdqa", { EXxS, XM }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_0 */
+ /* PREFIX_0FAE_REG_0_MOD_3 */
{
{ Bad_Opcode },
{ "rdfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_1 */
+ /* PREFIX_0FAE_REG_1_MOD_3 */
{
{ Bad_Opcode },
{ "rdgsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_2 */
+ /* PREFIX_0FAE_REG_2_MOD_3 */
{
{ Bad_Opcode },
{ "wrfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_3 */
+ /* PREFIX_0FAE_REG_3_MOD_3 */
{
{ Bad_Opcode },
{ "wrgsbase", { Ev }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_0 */
{
{ "xsave", { FXSAVE }, 0 },
- { "ptwrite%LQ", { Edq }, 0 },
+ { "ptwrite{%LQ|}", { Edq }, 0 },
},
- /* PREFIX_MOD_3_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_3 */
{
{ Bad_Opcode },
- { "ptwrite%LQ", { Edq }, 0 },
+ { "ptwrite{%LQ|}", { Edq }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_5 */
- {
- { "xrstor", { FXSAVE }, PREFIX_OPCODE },
- },
-
- /* PREFIX_MOD_3_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_3 */
{
{ "lfence", { Skip_MODRM }, 0 },
- { "incsspK", { Rdq }, PREFIX_OPCODE },
+ { "incsspK", { Edq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_0 */
{
{ "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
{ "clrssbsy", { Mq }, PREFIX_OPCODE },
{ "clwb", { Mb }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_1_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_3 */
{
- { RM_TABLE (RM_0FAE_REG_6) },
+ { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
{ "umonitor", { Eva }, PREFIX_OPCODE },
{ "tpause", { Edq }, PREFIX_OPCODE },
{ "umwait", { Edq }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_7 */
+ /* PREFIX_0FAE_REG_7_MOD_0 */
{
{ "clflush", { Mb }, 0 },
{ Bad_Opcode },
{ "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC3 */
- {
- { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
- },
-
- /* PREFIX_MOD_0_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_0 */
{
{ "vmptrld",{ Mq }, 0 },
{ "vmxon", { Mq }, 0 },
{ "vmclear",{ Mq }, 0 },
},
- /* PREFIX_MOD_3_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_3 */
{
{ "rdrand", { Ev }, 0 },
- { Bad_Opcode },
+ { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
{ "rdrand", { Ev }, 0 }
},
- /* PREFIX_MOD_3_0FC7_REG_7 */
+ /* PREFIX_0FC7_REG_7_MOD_3 */
{
{ "rdseed", { Ev }, 0 },
{ "rdpid", { Em }, 0 },
{ "maskmovdqu", { XM, XS }, PREFIX_OPCODE },
},
- /* PREFIX_0F3810 */
+ /* PREFIX_0F38D8 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE },
+ { REG_TABLE (REG_0F38D8_PREFIX_1) },
},
- /* PREFIX_0F3814 */
+ /* PREFIX_0F38DC */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
+ { "aesenc", { XM, EXx }, 0 },
},
- /* PREFIX_0F3815 */
+ /* PREFIX_0F38DD */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38DD_PREFIX_1) },
+ { "aesenclast", { XM, EXx }, 0 },
},
- /* PREFIX_0F3817 */
+ /* PREFIX_0F38DE */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "ptest", { XM, EXx }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38DE_PREFIX_1) },
+ { "aesdec", { XM, EXx }, 0 },
},
- /* PREFIX_0F3820 */
+ /* PREFIX_0F38DF */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38DF_PREFIX_1) },
+ { "aesdeclast", { XM, EXx }, 0 },
},
- /* PREFIX_0F3821 */
+ /* PREFIX_0F38F0 */
{
+ { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE },
+ { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
+ { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
},
- /* PREFIX_0F3822 */
+ /* PREFIX_0F38F1 */
{
+ { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE },
+ { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
+ { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
},
- /* PREFIX_0F3823 */
+ /* PREFIX_0F38F6 */
{
+ { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
+ { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
+ { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE },
},
- /* PREFIX_0F3824 */
+ /* PREFIX_0F38F8 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
},
-
- /* PREFIX_0F3825 */
+ /* PREFIX_0F38FA */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38FA_PREFIX_1) },
},
- /* PREFIX_0F3828 */
+ /* PREFIX_0F38FB */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmuldq", { XM, EXx }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F38FB_PREFIX_1) },
},
- /* PREFIX_0F3829 */
+ /* PREFIX_0F3A0F */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F3A0F_PREFIX_1)},
},
- /* PREFIX_0F382A */
+ /* PREFIX_VEX_0F10 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { MOD_TABLE (MOD_0F382A_PREFIX_2) },
+ { "vmovups", { XM, EXx }, 0 },
+ { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 },
+ { "vmovupd", { XM, EXx }, 0 },
+ { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 },
},
- /* PREFIX_0F382B */
+ /* PREFIX_VEX_0F11 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "packusdw", { XM, EXx }, PREFIX_OPCODE },
+ { "vmovups", { EXxS, XM }, 0 },
+ { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 },
+ { "vmovupd", { EXxS, XM }, 0 },
+ { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 },
},
- /* PREFIX_0F3830 */
+ /* PREFIX_VEX_0F12 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
+ { "vmovsldup", { XM, EXx }, 0 },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
+ { "vmovddup", { XM, EXymmq }, 0 },
},
- /* PREFIX_0F3831 */
+ /* PREFIX_VEX_0F16 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
+ { "vmovshdup", { XM, EXx }, 0 },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
},
- /* PREFIX_0F3832 */
+ /* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
+ { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
{ Bad_Opcode },
- { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE },
+ { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 },
},
- /* PREFIX_0F3833 */
+ /* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
+ { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 },
{ Bad_Opcode },
- { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE },
+ { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 },
},
- /* PREFIX_0F3834 */
+ /* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
+ { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 },
{ Bad_Opcode },
- { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE },
+ { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 },
},
- /* PREFIX_0F3835 */
+ /* PREFIX_VEX_0F2E */
{
+ { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE },
+ { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
},
- /* PREFIX_0F3837 */
+ /* PREFIX_VEX_0F2F */
{
+ { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE },
+ { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE },
},
- /* PREFIX_0F3838 */
+ /* PREFIX_VEX_0F41 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pminsb", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
},
- /* PREFIX_0F3839 */
+ /* PREFIX_VEX_0F42 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pminsd", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
},
- /* PREFIX_0F383A */
+ /* PREFIX_VEX_0F44 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pminuw", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
},
- /* PREFIX_0F383B */
+ /* PREFIX_VEX_0F45 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pminud", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
},
- /* PREFIX_0F383C */
+ /* PREFIX_VEX_0F46 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmaxsb", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
},
- /* PREFIX_0F383D */
+ /* PREFIX_VEX_0F47 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmaxsd", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
},
- /* PREFIX_0F383E */
+ /* PREFIX_VEX_0F4A */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmaxuw", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
},
- /* PREFIX_0F383F */
+ /* PREFIX_VEX_0F4B */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pmaxud", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
},
- /* PREFIX_0F3840 */
+ /* PREFIX_VEX_0F51 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pmulld", { XM, EXx }, PREFIX_OPCODE },
+ { "vsqrtps", { XM, EXx }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsqrtpd", { XM, EXx }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F3841 */
+ /* PREFIX_VEX_0F52 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "phminposuw", { XM, EXx }, PREFIX_OPCODE },
+ { "vrsqrtps", { XM, EXx }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 },
},
- /* PREFIX_0F3880 */
+ /* PREFIX_VEX_0F53 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "invept", { Gm, Mo }, PREFIX_OPCODE },
+ { "vrcpps", { XM, EXx }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 },
},
- /* PREFIX_0F3881 */
+ /* PREFIX_VEX_0F58 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "invvpid", { Gm, Mo }, PREFIX_OPCODE },
+ { "vaddps", { XM, Vex, EXx }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vaddpd", { XM, Vex, EXx }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F3882 */
+ /* PREFIX_VEX_0F59 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "invpcid", { Gm, M }, PREFIX_OPCODE },
+ { "vmulps", { XM, Vex, EXx }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmulpd", { XM, Vex, EXx }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F38C8 */
+ /* PREFIX_VEX_0F5A */
{
- { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
+ { "vcvtps2pd", { XM, EXxmmq }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F38C9 */
+ /* PREFIX_VEX_0F5B */
{
- { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
+ { "vcvtdq2ps", { XM, EXx }, 0 },
+ { "vcvttps2dq", { XM, EXx }, 0 },
+ { "vcvtps2dq", { XM, EXx }, 0 },
},
- /* PREFIX_0F38CA */
+ /* PREFIX_VEX_0F5C */
{
- { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
+ { "vsubps", { XM, Vex, EXx }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vsubpd", { XM, Vex, EXx }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F38CB */
+ /* PREFIX_VEX_0F5D */
{
- { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
+ { "vminps", { XM, Vex, EXx }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vminpd", { XM, Vex, EXx }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F38CC */
+ /* PREFIX_VEX_0F5E */
{
- { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
+ { "vdivps", { XM, Vex, EXx }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vdivpd", { XM, Vex, EXx }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F38CD */
+ /* PREFIX_VEX_0F5F */
{
- { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
+ { "vmaxps", { XM, Vex, EXx }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 },
+ { "vmaxpd", { XM, Vex, EXx }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 },
},
- /* PREFIX_0F38CF */
+ /* PREFIX_VEX_0F6F */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE },
+ { "vmovdqu", { XM, EXx }, 0 },
+ { "vmovdqa", { XM, EXx }, 0 },
},
- /* PREFIX_0F38DB */
+ /* PREFIX_VEX_0F70 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "aesimc", { XM, EXx }, PREFIX_OPCODE },
- },
-
- /* PREFIX_0F38DC */
- {
- { Bad_Opcode },
- { Bad_Opcode },
- { "aesenc", { XM, EXx }, PREFIX_OPCODE },
+ { "vpshufhw", { XM, EXx, Ib }, 0 },
+ { "vpshufd", { XM, EXx, Ib }, 0 },
+ { "vpshuflw", { XM, EXx, Ib }, 0 },
},
- /* PREFIX_0F38DD */
+ /* PREFIX_VEX_0F7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesenclast", { XM, EXx }, PREFIX_OPCODE },
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
+ { "vhaddps", { XM, Vex, EXx }, 0 },
},
- /* PREFIX_0F38DE */
+ /* PREFIX_VEX_0F7D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "aesdec", { XM, EXx }, PREFIX_OPCODE },
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
+ { "vhsubps", { XM, Vex, EXx }, 0 },
},
- /* PREFIX_0F38DF */
+ /* PREFIX_VEX_0F7E */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "aesdeclast", { XM, EXx }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
+ { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
},
- /* PREFIX_0F38F0 */
+ /* PREFIX_VEX_0F7F */
{
- { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE },
- { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE },
+ { "vmovdqu", { EXxS, XM }, 0 },
+ { "vmovdqa", { EXxS, XM }, 0 },
},
- /* PREFIX_0F38F1 */
+ /* PREFIX_VEX_0F90 */
{
- { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
{ Bad_Opcode },
- { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE },
- { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
},
- /* PREFIX_0F38F5 */
+ /* PREFIX_VEX_0F91 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { MOD_TABLE (MOD_0F38F5_PREFIX_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
},
- /* PREFIX_0F38F6 */
+ /* PREFIX_VEX_0F92 */
{
- { MOD_TABLE (MOD_0F38F6_PREFIX_0) },
- { "adoxS", { Gdq, Edq}, PREFIX_OPCODE },
- { "adcxS", { Gdq, Edq}, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
},
- /* PREFIX_0F38F8 */
+ /* PREFIX_VEX_0F93 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
{ Bad_Opcode },
- { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
- { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
- { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
},
- /* PREFIX_0F38F9 */
+ /* PREFIX_VEX_0F98 */
{
- { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
},
- /* PREFIX_0F3A08 */
+ /* PREFIX_VEX_0F99 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
},
- /* PREFIX_0F3A09 */
+ /* PREFIX_VEX_0FC2 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "vcmpps", { XM, Vex, EXx, CMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 },
+ { "vcmppd", { XM, Vex, EXx, CMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 },
},
- /* PREFIX_0F3A0A */
+ /* PREFIX_VEX_0FD0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE },
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
},
- /* PREFIX_0F3A0B */
+ /* PREFIX_VEX_0FE6 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE },
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
},
- /* PREFIX_0F3A0C */
+ /* PREFIX_VEX_0FF0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
},
- /* PREFIX_0F3A0D */
+ /* PREFIX_VEX_0F3849_X86_64 */
{
+ { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) },
},
- /* PREFIX_0F3A0E */
+ /* PREFIX_VEX_0F384B_X86_64 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) },
+ { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) },
},
- /* PREFIX_0F3A14 */
+ /* PREFIX_VEX_0F385C_X86_64 */
{
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) },
{ Bad_Opcode },
- { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE },
},
- /* PREFIX_0F3A15 */
+ /* PREFIX_VEX_0F385E_X86_64 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) },
+ { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) },
},
- /* PREFIX_0F3A16 */
+ /* PREFIX_VEX_0F38F5 */
{
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
{ Bad_Opcode },
- { Bad_Opcode },
- { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
},
- /* PREFIX_0F3A17 */
+ /* PREFIX_VEX_0F38F6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
},
- /* PREFIX_0F3A20 */
+ /* PREFIX_VEX_0F38F7 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
},
- /* PREFIX_0F3A21 */
+ /* PREFIX_VEX_0F3AF0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
},
- /* PREFIX_0F3A22 */
+#include "i386-dis-evex-prefix.h"
+};
+
+static const struct dis386 x86_64_table[][2] = {
+ /* X86_64_06 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE },
+ { "pushP", { es }, 0 },
},
- /* PREFIX_0F3A40 */
+ /* X86_64_07 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "popP", { es }, 0 },
},
- /* PREFIX_0F3A41 */
+ /* X86_64_0E */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "pushP", { cs }, 0 },
},
- /* PREFIX_0F3A42 */
+ /* X86_64_16 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "pushP", { ss }, 0 },
},
- /* PREFIX_0F3A44 */
+ /* X86_64_17 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE },
+ { "popP", { ss }, 0 },
},
- /* PREFIX_0F3A60 */
+ /* X86_64_1E */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
+ { "pushP", { ds }, 0 },
},
- /* PREFIX_0F3A61 */
+ /* X86_64_1F */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE },
+ { "popP", { ds }, 0 },
},
- /* PREFIX_0F3A62 */
+ /* X86_64_27 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "daa", { XX }, 0 },
},
- /* PREFIX_0F3A63 */
+ /* X86_64_2F */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "das", { XX }, 0 },
},
- /* PREFIX_0F3ACC */
+ /* X86_64_37 */
{
- { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
+ { "aaa", { XX }, 0 },
},
- /* PREFIX_0F3ACE */
+ /* X86_64_3F */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
+ { "aas", { XX }, 0 },
},
- /* PREFIX_0F3ACF */
+ /* X86_64_60 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE },
+ { "pushaP", { XX }, 0 },
},
- /* PREFIX_0F3ADF */
+ /* X86_64_61 */
{
- { Bad_Opcode },
- { Bad_Opcode },
- { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE },
+ { "popaP", { XX }, 0 },
},
- /* PREFIX_VEX_0F10 */
+ /* X86_64_62 */
{
- { "vmovups", { XM, EXx }, 0 },
- { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
- { "vmovupd", { XM, EXx }, 0 },
- { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
+ { MOD_TABLE (MOD_62_32BIT) },
+ { EVEX_TABLE (EVEX_0F) },
},
- /* PREFIX_VEX_0F11 */
+ /* X86_64_63 */
{
- { "vmovups", { EXxS, XM }, 0 },
- { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
- { "vmovupd", { EXxS, XM }, 0 },
- { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
+ { "arpl", { Ew, Gw }, 0 },
+ { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
- /* PREFIX_VEX_0F12 */
+ /* X86_64_6D */
{
- { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
- { "vmovsldup", { XM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
- { "vmovddup", { XM, EXymmq }, 0 },
+ { "ins{R|}", { Yzr, indirDX }, 0 },
+ { "ins{G|}", { Yzr, indirDX }, 0 },
},
- /* PREFIX_VEX_0F16 */
+ /* X86_64_6F */
{
- { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
- { "vmovshdup", { XM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
+ { "outs{R|}", { indirDXr, Xz }, 0 },
+ { "outs{G|}", { indirDXr, Xz }, 0 },
},
- /* PREFIX_VEX_0F2A */
+ /* X86_64_82 */
{
- { Bad_Opcode },
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
- { Bad_Opcode },
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
+ /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
+ { REG_TABLE (REG_80) },
},
- /* PREFIX_VEX_0F2C */
+ /* X86_64_9A */
{
- { Bad_Opcode },
- { "vcvttss2si", { Gdq, EXdScalar }, 0 },
- { Bad_Opcode },
- { "vcvttsd2si", { Gdq, EXqScalar }, 0 },
+ { "{l|}call{P|}", { Ap }, 0 },
},
- /* PREFIX_VEX_0F2D */
+ /* X86_64_C2 */
{
- { Bad_Opcode },
- { "vcvtss2si", { Gdq, EXdScalar }, 0 },
- { Bad_Opcode },
- { "vcvtsd2si", { Gdq, EXqScalar }, 0 },
+ { "retP", { Iw, BND }, 0 },
+ { "ret@", { Iw, BND }, 0 },
},
- /* PREFIX_VEX_0F2E */
+ /* X86_64_C3 */
{
- { "vucomiss", { XMScalar, EXdScalar }, 0 },
- { Bad_Opcode },
- { "vucomisd", { XMScalar, EXqScalar }, 0 },
+ { "retP", { BND }, 0 },
+ { "ret@", { BND }, 0 },
},
- /* PREFIX_VEX_0F2F */
+ /* X86_64_C4 */
{
- { "vcomiss", { XMScalar, EXdScalar }, 0 },
- { Bad_Opcode },
- { "vcomisd", { XMScalar, EXqScalar }, 0 },
+ { MOD_TABLE (MOD_C4_32BIT) },
+ { VEX_C4_TABLE (VEX_0F) },
},
- /* PREFIX_VEX_0F41 */
+ /* X86_64_C5 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) },
+ { MOD_TABLE (MOD_C5_32BIT) },
+ { VEX_C5_TABLE (VEX_0F) },
},
- /* PREFIX_VEX_0F42 */
+ /* X86_64_CE */
{
- { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) },
+ { "into", { XX }, 0 },
},
- /* PREFIX_VEX_0F44 */
+ /* X86_64_D4 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) },
+ { "aam", { Ib }, 0 },
},
- /* PREFIX_VEX_0F45 */
+ /* X86_64_D5 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) },
+ { "aad", { Ib }, 0 },
},
- /* PREFIX_VEX_0F46 */
+ /* X86_64_E8 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) },
+ { "callP", { Jv, BND }, 0 },
+ { "call@", { Jv, BND }, 0 }
},
- /* PREFIX_VEX_0F47 */
+ /* X86_64_E9 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) },
+ { "jmpP", { Jv, BND }, 0 },
+ { "jmp@", { Jv, BND }, 0 }
},
- /* PREFIX_VEX_0F4A */
+ /* X86_64_EA */
{
- { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) },
+ { "{l|}jmp{P|}", { Ap }, 0 },
},
- /* PREFIX_VEX_0F4B */
+ /* X86_64_0F01_REG_0 */
{
- { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) },
- { Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) },
+ { "sgdt{Q|Q}", { M }, 0 },
+ { "sgdt", { M }, 0 },
},
- /* PREFIX_VEX_0F51 */
+ /* X86_64_0F01_REG_1 */
{
- { "vsqrtps", { XM, EXx }, 0 },
- { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vsqrtpd", { XM, EXx }, 0 },
- { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "sidt{Q|Q}", { M }, 0 },
+ { "sidt", { M }, 0 },
},
- /* PREFIX_VEX_0F52 */
+ /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
{
- { "vrsqrtps", { XM, EXx }, 0 },
- { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { Bad_Opcode },
+ { "seamret", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F53 */
+ /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
{
- { "vrcpps", { XM, EXx }, 0 },
- { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { Bad_Opcode },
+ { "seamops", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F58 */
+ /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
{
- { "vaddps", { XM, Vex, EXx }, 0 },
- { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vaddpd", { XM, Vex, EXx }, 0 },
- { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { Bad_Opcode },
+ { "seamcall", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F59 */
+ /* X86_64_0F01_REG_2 */
{
- { "vmulps", { XM, Vex, EXx }, 0 },
- { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vmulpd", { XM, Vex, EXx }, 0 },
- { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "lgdt{Q|Q}", { M }, 0 },
+ { "lgdt", { M }, 0 },
},
- /* PREFIX_VEX_0F5A */
+ /* X86_64_0F01_REG_3 */
{
- { "vcvtps2pd", { XM, EXxmmq }, 0 },
- { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
- { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { "lidt{Q|Q}", { M }, 0 },
+ { "lidt", { M }, 0 },
},
- /* PREFIX_VEX_0F5B */
{
- { "vcvtdq2ps", { XM, EXx }, 0 },
- { "vcvttps2dq", { XM, EXx }, 0 },
- { "vcvtps2dq", { XM, EXx }, 0 },
+ /* X86_64_0F24 */
+ { "movZ", { Em, Td }, 0 },
},
- /* PREFIX_VEX_0F5C */
{
- { "vsubps", { XM, Vex, EXx }, 0 },
- { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vsubpd", { XM, Vex, EXx }, 0 },
- { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* X86_64_0F26 */
+ { "movZ", { Td, Em }, 0 },
},
- /* PREFIX_VEX_0F5D */
+ /* X86_64_VEX_0F3849 */
{
- { "vminps", { XM, Vex, EXx }, 0 },
- { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vminpd", { XM, Vex, EXx }, 0 },
- { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) },
},
- /* PREFIX_VEX_0F5E */
+ /* X86_64_VEX_0F384B */
{
- { "vdivps", { XM, Vex, EXx }, 0 },
- { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vdivpd", { XM, Vex, EXx }, 0 },
- { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) },
},
- /* PREFIX_VEX_0F5F */
+ /* X86_64_VEX_0F385C */
{
- { "vmaxps", { XM, Vex, EXx }, 0 },
- { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
- { "vmaxpd", { XM, Vex, EXx }, 0 },
- { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) },
},
- /* PREFIX_VEX_0F60 */
+ /* X86_64_VEX_0F385E */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpunpcklbw", { XM, Vex, EXx }, 0 },
+ { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) },
},
- /* PREFIX_VEX_0F61 */
+ /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpunpcklwd", { XM, Vex, EXx }, 0 },
+ { "uiret", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F62 */
+ /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpunpckldq", { XM, Vex, EXx }, 0 },
+ { "testui", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F63 */
+ /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpacksswb", { XM, Vex, EXx }, 0 },
+ { "clui", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F64 */
+ /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpcmpgtb", { XM, Vex, EXx }, 0 },
+ { "stui", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F65 */
+ /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpcmpgtw", { XM, Vex, EXx }, 0 },
+ { "rmpadjust", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F66 */
+ /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpcmpgtd", { XM, Vex, EXx }, 0 },
+ { "rmpupdate", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F67 */
+ /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpackuswb", { XM, Vex, EXx }, 0 },
+ { "psmash", { Skip_MODRM }, 0 },
},
- /* PREFIX_VEX_0F68 */
+ /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
{
{ Bad_Opcode },
- { Bad_Opcode },
- { "vpunpckhbw", { XM, Vex, EXx }, 0 },
+ { "senduipi", { Eq }, 0 },
},
+};
- /* PREFIX_VEX_0F69 */
+static const struct dis386 three_byte_table[][256] = {
+
+ /* THREE_BYTE_0F38 */
{
+ /* 00 */
+ { "pshufb", { MX, EM }, PREFIX_OPCODE },
+ { "phaddw", { MX, EM }, PREFIX_OPCODE },
+ { "phaddd", { MX, EM }, PREFIX_OPCODE },
+ { "phaddsw", { MX, EM }, PREFIX_OPCODE },
+ { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
+ { "phsubw", { MX, EM }, PREFIX_OPCODE },
+ { "phsubd", { MX, EM }, PREFIX_OPCODE },
+ { "phsubsw", { MX, EM }, PREFIX_OPCODE },
+ /* 08 */
+ { "psignb", { MX, EM }, PREFIX_OPCODE },
+ { "psignw", { MX, EM }, PREFIX_OPCODE },
+ { "psignd", { MX, EM }, PREFIX_OPCODE },
+ { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpunpckhwd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F6A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpunpckhdq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F6B */
- {
+ /* 10 */
+ { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpackssdw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F6C */
- {
{ Bad_Opcode },
+ { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
+ { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F6D */
- {
+ { "ptest", { XM, EXx }, PREFIX_DATA },
+ /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F6E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) },
- },
-
- /* PREFIX_VEX_0F6F */
- {
+ { "pabsb", { MX, EM }, PREFIX_OPCODE },
+ { "pabsw", { MX, EM }, PREFIX_OPCODE },
+ { "pabsd", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
- { "vmovdqu", { XM, EXx }, 0 },
- { "vmovdqa", { XM, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F70 */
- {
+ /* 20 */
+ { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
+ { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
+ { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
+ { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
+ { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
+ { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpshufhw", { XM, EXx, Ib }, 0 },
- { "vpshufd", { XM, EXx, Ib }, 0 },
- { "vpshuflw", { XM, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F71_REG_2 */
- {
{ Bad_Opcode },
+ /* 28 */
+ { "pmuldq", { XM, EXx }, PREFIX_DATA },
+ { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
+ { MOD_TABLE (MOD_0F382A) },
+ { "packusdw", { XM, EXx }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpsrlw", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F71_REG_4 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsraw", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F71_REG_6 */
- {
{ Bad_Opcode },
+ /* 30 */
+ { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
+ { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
+ { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
+ { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
+ { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
+ { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
+ { Bad_Opcode },
+ { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
+ /* 38 */
+ { "pminsb", { XM, EXx }, PREFIX_DATA },
+ { "pminsd", { XM, EXx }, PREFIX_DATA },
+ { "pminuw", { XM, EXx }, PREFIX_DATA },
+ { "pminud", { XM, EXx }, PREFIX_DATA },
+ { "pmaxsb", { XM, EXx }, PREFIX_DATA },
+ { "pmaxsd", { XM, EXx }, PREFIX_DATA },
+ { "pmaxuw", { XM, EXx }, PREFIX_DATA },
+ { "pmaxud", { XM, EXx }, PREFIX_DATA },
+ /* 40 */
+ { "pmulld", { XM, EXx }, PREFIX_DATA },
+ { "phminposuw", { XM, EXx }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpsllw", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F72_REG_2 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrld", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F72_REG_4 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrad", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F72_REG_6 */
- {
{ Bad_Opcode },
+ /* 48 */
{ Bad_Opcode },
- { "vpslld", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F73_REG_2 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrlq", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F73_REG_3 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrldq", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F73_REG_6 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsllq", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F73_REG_7 */
- {
{ Bad_Opcode },
+ /* 50 */
{ Bad_Opcode },
- { "vpslldq", { Vex, XS, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F74 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpeqb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F75 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpeqw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F76 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpeqd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F77 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
- },
-
- /* PREFIX_VEX_0F7C */
- {
{ Bad_Opcode },
+ /* 58 */
{ Bad_Opcode },
- { "vhaddpd", { XM, Vex, EXx }, 0 },
- { "vhaddps", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F7D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vhsubpd", { XM, Vex, EXx }, 0 },
- { "vhsubps", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F7E */
- {
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
- },
-
- /* PREFIX_VEX_0F7F */
- {
{ Bad_Opcode },
- { "vmovdqu", { EXxS, XM }, 0 },
- { "vmovdqa", { EXxS, XM }, 0 },
- },
-
- /* PREFIX_VEX_0F90 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) },
- },
-
- /* PREFIX_VEX_0F91 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) },
- },
-
- /* PREFIX_VEX_0F92 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) },
- },
-
- /* PREFIX_VEX_0F93 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) },
+ /* 60 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) },
- },
-
- /* PREFIX_VEX_0F98 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) },
- },
-
- /* PREFIX_VEX_0F99 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) },
- },
-
- /* PREFIX_VEX_0FC2 */
- {
- { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
- { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
- { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
- { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
- },
-
- /* PREFIX_VEX_0FC4 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) },
- },
-
- /* PREFIX_VEX_0FC5 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) },
- },
-
- /* PREFIX_VEX_0FD0 */
- {
{ Bad_Opcode },
+ /* 68 */
{ Bad_Opcode },
- { "vaddsubpd", { XM, Vex, EXx }, 0 },
- { "vaddsubps", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FD1 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrlw", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FD2 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrld", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FD3 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrlq", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FD4 */
- {
{ Bad_Opcode },
+ /* 70 */
{ Bad_Opcode },
- { "vpaddq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FD5 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmullw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FD6 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) },
- },
-
- /* PREFIX_VEX_0FD7 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0FD8 */
- {
{ Bad_Opcode },
+ /* 78 */
{ Bad_Opcode },
- { "vpsubusb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FD9 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubusw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FDA */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpminub", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FDB */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpand", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FDC */
- {
{ Bad_Opcode },
+ /* 80 */
+ { "invept", { Gm, Mo }, PREFIX_DATA },
+ { "invvpid", { Gm, Mo }, PREFIX_DATA },
+ { "invpcid", { Gm, M }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpaddusb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FDD */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpaddusw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FDE */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaxub", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FDF */
- {
+ /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpandn", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE0 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpavgb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE1 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsraw", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FE2 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsrad", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FE3 */
- {
+ /* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpavgw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE4 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmulhuw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE5 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmulhw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE6 */
- {
{ Bad_Opcode },
- { "vcvtdq2pd", { XM, EXxmmq }, 0 },
- { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
- { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE7 */
- {
{ Bad_Opcode },
+ /* 98 */
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0FE8 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubsb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FE9 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FEA */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpminsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FEB */
- {
{ Bad_Opcode },
+ /* a0 */
{ Bad_Opcode },
- { "vpor", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FEC */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpaddsb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FED */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpaddsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FEE */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaxsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FEF */
- {
{ Bad_Opcode },
+ /* a8 */
{ Bad_Opcode },
- { "vpxor", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FF0 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) },
- },
-
- /* PREFIX_VEX_0FF1 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsllw", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FF2 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpslld", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FF3 */
- {
+ /* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsllq", { XM, Vex, EXxmm }, 0 },
- },
-
- /* PREFIX_VEX_0FF4 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmuludq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FF5 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaddwd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FF6 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsadbw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FF7 */
- {
+ /* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) },
- },
-
- /* PREFIX_VEX_0FF8 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FF9 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FFA */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FFB */
- {
+ /* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsubq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FFC */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpaddb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FFD */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpaddw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0FFE */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpaddd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3800 */
- {
+ /* c8 */
+ { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
+ { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
+ { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
+ { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
+ { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
+ { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
{ Bad_Opcode },
+ { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
+ /* d0 */
{ Bad_Opcode },
- { "vpshufb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3801 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3802 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3803 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3804 */
- {
{ Bad_Opcode },
+ /* d8 */
+ { PREFIX_TABLE (PREFIX_0F38D8) },
{ Bad_Opcode },
- { "vpmaddubsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3805 */
- {
{ Bad_Opcode },
+ { "aesimc", { XM, EXx }, PREFIX_DATA },
+ { PREFIX_TABLE (PREFIX_0F38DC) },
+ { PREFIX_TABLE (PREFIX_0F38DD) },
+ { PREFIX_TABLE (PREFIX_0F38DE) },
+ { PREFIX_TABLE (PREFIX_0F38DF) },
+ /* e0 */
{ Bad_Opcode },
- { "vphsubw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3806 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphsubd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3807 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphsubsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3808 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsignb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3809 */
- {
{ Bad_Opcode },
+ /* e8 */
{ Bad_Opcode },
- { "vpsignw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F380A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsignd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F380B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmulhrsw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F380C */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380C_P_2) },
- },
-
- /* PREFIX_VEX_0F380D */
- {
{ Bad_Opcode },
+ /* f0 */
+ { PREFIX_TABLE (PREFIX_0F38F0) },
+ { PREFIX_TABLE (PREFIX_0F38F1) },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380D_P_2) },
- },
-
- /* PREFIX_VEX_0F380E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380E_P_2) },
- },
-
- /* PREFIX_VEX_0F380F */
- {
+ { MOD_TABLE (MOD_0F38F5) },
+ { PREFIX_TABLE (PREFIX_0F38F6) },
+ { Bad_Opcode },
+ /* f8 */
+ { PREFIX_TABLE (PREFIX_0F38F8) },
+ { MOD_TABLE (MOD_0F38F9) },
+ { PREFIX_TABLE (PREFIX_0F38FA) },
+ { PREFIX_TABLE (PREFIX_0F38FB) },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380F_P_2) },
- },
-
- /* PREFIX_VEX_0F3813 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtph2ps", { XM, EXxmmq }, 0 },
},
-
- /* PREFIX_VEX_0F3816 */
+ /* THREE_BYTE_0F3A */
{
+ /* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) },
- },
-
- /* PREFIX_VEX_0F3817 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vptest", { XM, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3818 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3818_P_2) },
- },
-
- /* PREFIX_VEX_0F3819 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) },
- },
-
- /* PREFIX_VEX_0F381A */
- {
+ /* 08 */
+ { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
+ { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
+ { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
+ { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
+ { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
+ { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
+ { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
+ { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
+ /* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F381C */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpabsb", { XM, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F381D */
- {
+ { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA },
+ { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA },
+ { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
+ { "extractps", { Edqd, XM, Ib }, PREFIX_DATA },
+ /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpabsw", { XM, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F381E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpabsd", { XM, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3820 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovsxbw", { XM, EXxmmq }, 0 },
- },
-
- /* PREFIX_VEX_0F3821 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovsxbd", { XM, EXxmmqd }, 0 },
- },
-
- /* PREFIX_VEX_0F3822 */
- {
+ /* 20 */
+ { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA },
+ { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
+ { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovsxbq", { XM, EXxmmdw }, 0 },
- },
-
- /* PREFIX_VEX_0F3823 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovsxwd", { XM, EXxmmq }, 0 },
- },
-
- /* PREFIX_VEX_0F3824 */
- {
{ Bad_Opcode },
+ /* 28 */
{ Bad_Opcode },
- { "vpmovsxwq", { XM, EXxmmqd }, 0 },
- },
-
- /* PREFIX_VEX_0F3825 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovsxdq", { XM, EXxmmq }, 0 },
- },
-
- /* PREFIX_VEX_0F3828 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmuldq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3829 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpeqq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F382A */
- {
{ Bad_Opcode },
+ /* 30 */
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F382B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpackusdw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F382C */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F382D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F382E */
- {
{ Bad_Opcode },
+ /* 38 */
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F382F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F3830 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovzxbw", { XM, EXxmmq }, 0 },
- },
-
- /* PREFIX_VEX_0F3831 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovzxbd", { XM, EXxmmqd }, 0 },
- },
-
- /* PREFIX_VEX_0F3832 */
- {
{ Bad_Opcode },
+ /* 40 */
+ { "dpps", { XM, EXx, Ib }, PREFIX_DATA },
+ { "dppd", { XM, EXx, Ib }, PREFIX_DATA },
+ { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpmovzxbq", { XM, EXxmmdw }, 0 },
- },
-
- /* PREFIX_VEX_0F3833 */
- {
+ { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovzxwd", { XM, EXxmmq }, 0 },
- },
-
- /* PREFIX_VEX_0F3834 */
- {
{ Bad_Opcode },
+ /* 48 */
{ Bad_Opcode },
- { "vpmovzxwq", { XM, EXxmmqd }, 0 },
- },
-
- /* PREFIX_VEX_0F3835 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmovzxdq", { XM, EXxmmq }, 0 },
- },
-
- /* PREFIX_VEX_0F3836 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) },
- },
-
- /* PREFIX_VEX_0F3837 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmpgtq", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3838 */
- {
{ Bad_Opcode },
+ /* 50 */
{ Bad_Opcode },
- { "vpminsb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3839 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpminsd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F383A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpminuw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F383B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpminud", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F383C */
- {
{ Bad_Opcode },
+ /* 58 */
{ Bad_Opcode },
- { "vpmaxsb", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F383D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaxsd", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F383E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaxuw", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F383F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmaxud", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3840 */
- {
{ Bad_Opcode },
+ /* 60 */
+ { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
+ { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
+ { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
+ { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
- { "vpmulld", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3841 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) },
- },
-
- /* PREFIX_VEX_0F3845 */
- {
{ Bad_Opcode },
+ /* 68 */
{ Bad_Opcode },
- { "vpsrlv%LW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3846 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3846_P_2) },
- },
-
- /* PREFIX_VEX_0F3847 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpsllv%LW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3858 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3858_P_2) },
- },
-
- /* PREFIX_VEX_0F3859 */
- {
{ Bad_Opcode },
+ /* 70 */
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3859_P_2) },
- },
-
- /* PREFIX_VEX_0F385A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F3878 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3878_P_2) },
- },
-
- /* PREFIX_VEX_0F3879 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3879_P_2) },
- },
-
- /* PREFIX_VEX_0F388C */
- {
{ Bad_Opcode },
+ /* 78 */
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F388E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) },
- },
-
- /* PREFIX_VEX_0F3890 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 },
- },
-
- /* PREFIX_VEX_0F3891 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
- },
-
- /* PREFIX_VEX_0F3892 */
- {
{ Bad_Opcode },
+ /* 80 */
{ Bad_Opcode },
- { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 },
- },
-
- /* PREFIX_VEX_0F3893 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 },
- },
-
- /* PREFIX_VEX_0F3896 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3897 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3898 */
- {
{ Bad_Opcode },
+ /* 88 */
{ Bad_Opcode },
- { "vfmadd132p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F3899 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F389A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub132p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F389B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F389C */
- {
{ Bad_Opcode },
+ /* 90 */
{ Bad_Opcode },
- { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F389D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F389E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F389F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38A6 */
- {
{ Bad_Opcode },
+ /* 98 */
{ Bad_Opcode },
- { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 },
{ Bad_Opcode },
- },
-
- /* PREFIX_VEX_0F38A7 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38A8 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38A9 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38AA */
- {
+ /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub213p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38AB */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38AC */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38AD */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38AE */
- {
+ /* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38AF */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38B6 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38B7 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38B8 */
- {
+ /* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38B9 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38BA */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38BB */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38BC */
- {
+ /* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38BD */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38BE */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38BF */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 },
- },
-
- /* PREFIX_VEX_0F38CF */
- {
+ /* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F38CF_P_2) },
- },
-
- /* PREFIX_VEX_0F38DB */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) },
- },
-
- /* PREFIX_VEX_0F38DC */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vaesenc", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38DD */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vaesenclast", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38DE */
- {
+ /* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vaesdec", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38DF */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vaesdeclast", { XM, Vex, EXx }, 0 },
- },
-
- /* PREFIX_VEX_0F38F2 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) },
- },
-
- /* PREFIX_VEX_0F38F3_REG_1 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) },
- },
-
- /* PREFIX_VEX_0F38F3_REG_2 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) },
- },
-
- /* PREFIX_VEX_0F38F3_REG_3 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) },
- },
-
- /* PREFIX_VEX_0F38F5 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) },
+ { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) },
- },
-
- /* PREFIX_VEX_0F38F6 */
- {
+ { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
+ { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
+ /* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) },
- },
-
- /* PREFIX_VEX_0F38F7 */
- {
- { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) },
- },
-
- /* PREFIX_VEX_0F3A00 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) },
- },
-
- /* PREFIX_VEX_0F3A01 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) },
- },
-
- /* PREFIX_VEX_0F3A02 */
- {
{ Bad_Opcode },
+ /* d8 */
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A02_P_2) },
- },
-
- /* PREFIX_VEX_0F3A04 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A04_P_2) },
- },
-
- /* PREFIX_VEX_0F3A05 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A05_P_2) },
- },
-
- /* PREFIX_VEX_0F3A06 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) },
- },
-
- /* PREFIX_VEX_0F3A08 */
- {
+ { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
+ /* e0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vroundps", { XM, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A09 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vroundpd", { XM, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A0A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A0B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A0C */
- {
+ /* e8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vblendps", { XM, Vex, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A0D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A0E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A0F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A14 */
- {
+ /* f0 */
+ { PREFIX_TABLE (PREFIX_0F3A0F) },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) },
- },
-
- /* PREFIX_VEX_0F3A15 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) },
- },
-
- /* PREFIX_VEX_0F3A16 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) },
- },
-
- /* PREFIX_VEX_0F3A17 */
- {
+ { Bad_Opcode },
+ /* f8 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) },
- },
-
- /* PREFIX_VEX_0F3A18 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) },
- },
-
- /* PREFIX_VEX_0F3A19 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) },
- },
-
- /* PREFIX_VEX_0F3A1D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 },
},
+};
- /* PREFIX_VEX_0F3A20 */
+static const struct dis386 xop_table[][256] = {
+ /* XOP_08 */
{
+ /* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) },
- },
-
- /* PREFIX_VEX_0F3A21 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) },
- },
-
- /* PREFIX_VEX_0F3A22 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) },
- },
-
- /* PREFIX_VEX_0F3A30 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) },
- },
-
- /* PREFIX_VEX_0F3A31 */
- {
+ /* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) },
- },
-
- /* PREFIX_VEX_0F3A32 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) },
- },
-
- /* PREFIX_VEX_0F3A33 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) },
- },
-
- /* PREFIX_VEX_0F3A38 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) },
- },
-
- /* PREFIX_VEX_0F3A39 */
- {
+ /* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) },
- },
-
- /* PREFIX_VEX_0F3A40 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vdpps", { XM, Vex, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A41 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) },
- },
-
- /* PREFIX_VEX_0F3A42 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
- },
-
- /* PREFIX_VEX_0F3A44 */
- {
+ /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 },
- },
-
- /* PREFIX_VEX_0F3A46 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) },
- },
-
- /* PREFIX_VEX_0F3A48 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A48_P_2) },
- },
-
- /* PREFIX_VEX_0F3A49 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A49_P_2) },
- },
-
- /* PREFIX_VEX_0F3A4A */
- {
+ /* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A4A_P_2) },
- },
-
- /* PREFIX_VEX_0F3A4B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A4B_P_2) },
- },
-
- /* PREFIX_VEX_0F3A4C */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A4C_P_2) },
- },
-
- /* PREFIX_VEX_0F3A5C */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A5D */
- {
+ /* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A5E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A5F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A60 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) },
+ /* 30 */
{ Bad_Opcode },
- },
-
- /* PREFIX_VEX_0F3A61 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) },
- },
-
- /* PREFIX_VEX_0F3A62 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) },
- },
-
- /* PREFIX_VEX_0F3A63 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) },
- },
-
- /* PREFIX_VEX_0F3A68 */
- {
{ Bad_Opcode },
+ /* 38 */
{ Bad_Opcode },
- { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A69 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A6A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) },
- },
-
- /* PREFIX_VEX_0F3A6B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) },
- },
-
- /* PREFIX_VEX_0F3A6C */
- {
{ Bad_Opcode },
+ /* 40 */
{ Bad_Opcode },
- { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A6D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A6E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) },
- },
-
- /* PREFIX_VEX_0F3A6F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) },
- },
-
- /* PREFIX_VEX_0F3A78 */
- {
{ Bad_Opcode },
+ /* 48 */
{ Bad_Opcode },
- { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A79 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A7A */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) },
- },
-
- /* PREFIX_VEX_0F3A7B */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) },
- },
-
- /* PREFIX_VEX_0F3A7C */
- {
{ Bad_Opcode },
+ /* 50 */
{ Bad_Opcode },
- { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
{ Bad_Opcode },
- },
-
- /* PREFIX_VEX_0F3A7D */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- },
-
- /* PREFIX_VEX_0F3A7E */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) },
- },
-
- /* PREFIX_VEX_0F3A7F */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) },
- },
-
- /* PREFIX_VEX_0F3ACE */
- {
+ /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3ACE_P_2) },
- },
-
- /* PREFIX_VEX_0F3ACF */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3ACF_P_2) },
- },
-
- /* PREFIX_VEX_0F3ADF */
- {
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) },
- },
-
- /* PREFIX_VEX_0F3AF0 */
- {
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 60 */
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
- },
-
-#include "i386-dis-evex-prefix.h"
-};
-
-static const struct dis386 x86_64_table[][2] = {
- /* X86_64_06 */
- {
- { "pushP", { es }, 0 },
- },
-
- /* X86_64_07 */
- {
- { "popP", { es }, 0 },
- },
-
- /* X86_64_0D */
- {
- { "pushP", { cs }, 0 },
- },
-
- /* X86_64_16 */
- {
- { "pushP", { ss }, 0 },
- },
-
- /* X86_64_17 */
- {
- { "popP", { ss }, 0 },
- },
-
- /* X86_64_1E */
- {
- { "pushP", { ds }, 0 },
- },
-
- /* X86_64_1F */
- {
- { "popP", { ds }, 0 },
- },
-
- /* X86_64_27 */
- {
- { "daa", { XX }, 0 },
- },
-
- /* X86_64_2F */
- {
- { "das", { XX }, 0 },
- },
-
- /* X86_64_37 */
- {
- { "aaa", { XX }, 0 },
- },
-
- /* X86_64_3F */
- {
- { "aas", { XX }, 0 },
- },
-
- /* X86_64_60 */
- {
- { "pushaP", { XX }, 0 },
- },
-
- /* X86_64_61 */
- {
- { "popaP", { XX }, 0 },
- },
-
- /* X86_64_62 */
- {
- { MOD_TABLE (MOD_62_32BIT) },
- { EVEX_TABLE (EVEX_0F) },
- },
-
- /* X86_64_63 */
- {
- { "arpl", { Ew, Gw }, 0 },
- { "movs{lq|xd}", { Gv, Ed }, 0 },
- },
-
- /* X86_64_6D */
- {
- { "ins{R|}", { Yzr, indirDX }, 0 },
- { "ins{G|}", { Yzr, indirDX }, 0 },
- },
-
- /* X86_64_6F */
- {
- { "outs{R|}", { indirDXr, Xz }, 0 },
- { "outs{G|}", { indirDXr, Xz }, 0 },
- },
-
- /* X86_64_82 */
- {
- /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */
- { REG_TABLE (REG_80) },
- },
-
- /* X86_64_9A */
- {
- { "Jcall{T|}", { Ap }, 0 },
- },
-
- /* X86_64_C4 */
- {
- { MOD_TABLE (MOD_C4_32BIT) },
- { VEX_C4_TABLE (VEX_0F) },
- },
-
- /* X86_64_C5 */
- {
- { MOD_TABLE (MOD_C5_32BIT) },
- { VEX_C5_TABLE (VEX_0F) },
- },
-
- /* X86_64_CE */
- {
- { "into", { XX }, 0 },
- },
-
- /* X86_64_D4 */
- {
- { "aam", { Ib }, 0 },
- },
-
- /* X86_64_D5 */
- {
- { "aad", { Ib }, 0 },
- },
-
- /* X86_64_E8 */
- {
- { "callP", { Jv, BND }, 0 },
- { "call@", { Jv, BND }, 0 }
- },
-
- /* X86_64_E9 */
- {
- { "jmpP", { Jv, BND }, 0 },
- { "jmp@", { Jv, BND }, 0 }
- },
-
- /* X86_64_EA */
- {
- { "Jjmp{T|}", { Ap }, 0 },
- },
-
- /* X86_64_0F01_REG_0 */
- {
- { "sgdt{Q|IQ}", { M }, 0 },
- { "sgdt", { M }, 0 },
- },
-
- /* X86_64_0F01_REG_1 */
- {
- { "sidt{Q|IQ}", { M }, 0 },
- { "sidt", { M }, 0 },
- },
-
- /* X86_64_0F01_REG_2 */
- {
- { "lgdt{Q|Q}", { M }, 0 },
- { "lgdt", { M }, 0 },
- },
-
- /* X86_64_0F01_REG_3 */
- {
- { "lidt{Q|Q}", { M }, 0 },
- { "lidt", { M }, 0 },
- },
-};
-
-static const struct dis386 three_byte_table[][256] = {
-
- /* THREE_BYTE_0F38 */
- {
- /* 00 */
- { "pshufb", { MX, EM }, PREFIX_OPCODE },
- { "phaddw", { MX, EM }, PREFIX_OPCODE },
- { "phaddd", { MX, EM }, PREFIX_OPCODE },
- { "phaddsw", { MX, EM }, PREFIX_OPCODE },
- { "pmaddubsw", { MX, EM }, PREFIX_OPCODE },
- { "phsubw", { MX, EM }, PREFIX_OPCODE },
- { "phsubd", { MX, EM }, PREFIX_OPCODE },
- { "phsubsw", { MX, EM }, PREFIX_OPCODE },
- /* 08 */
- { "psignb", { MX, EM }, PREFIX_OPCODE },
- { "psignw", { MX, EM }, PREFIX_OPCODE },
- { "psignd", { MX, EM }, PREFIX_OPCODE },
- { "pmulhrsw", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 10 */
- { PREFIX_TABLE (PREFIX_0F3810) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3814) },
- { PREFIX_TABLE (PREFIX_0F3815) },
+ /* 68 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3817) },
- /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "pabsb", { MX, EM }, PREFIX_OPCODE },
- { "pabsw", { MX, EM }, PREFIX_OPCODE },
- { "pabsd", { MX, EM }, PREFIX_OPCODE },
{ Bad_Opcode },
- /* 20 */
- { PREFIX_TABLE (PREFIX_0F3820) },
- { PREFIX_TABLE (PREFIX_0F3821) },
- { PREFIX_TABLE (PREFIX_0F3822) },
- { PREFIX_TABLE (PREFIX_0F3823) },
- { PREFIX_TABLE (PREFIX_0F3824) },
- { PREFIX_TABLE (PREFIX_0F3825) },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 28 */
- { PREFIX_TABLE (PREFIX_0F3828) },
- { PREFIX_TABLE (PREFIX_0F3829) },
- { PREFIX_TABLE (PREFIX_0F382A) },
- { PREFIX_TABLE (PREFIX_0F382B) },
+ /* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 30 */
- { PREFIX_TABLE (PREFIX_0F3830) },
- { PREFIX_TABLE (PREFIX_0F3831) },
- { PREFIX_TABLE (PREFIX_0F3832) },
- { PREFIX_TABLE (PREFIX_0F3833) },
- { PREFIX_TABLE (PREFIX_0F3834) },
- { PREFIX_TABLE (PREFIX_0F3835) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3837) },
- /* 38 */
- { PREFIX_TABLE (PREFIX_0F3838) },
- { PREFIX_TABLE (PREFIX_0F3839) },
- { PREFIX_TABLE (PREFIX_0F383A) },
- { PREFIX_TABLE (PREFIX_0F383B) },
- { PREFIX_TABLE (PREFIX_0F383C) },
- { PREFIX_TABLE (PREFIX_0F383D) },
- { PREFIX_TABLE (PREFIX_0F383E) },
- { PREFIX_TABLE (PREFIX_0F383F) },
- /* 40 */
- { PREFIX_TABLE (PREFIX_0F3840) },
- { PREFIX_TABLE (PREFIX_0F3841) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) },
+ /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 58 */
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) },
+ /* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) },
+ /* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) },
+ /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 68 */
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) },
{ Bad_Opcode },
+ /* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 70 */
{ Bad_Opcode },
+ /* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) },
{ Bad_Opcode },
- /* 78 */
+ /* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 80 */
- { PREFIX_TABLE (PREFIX_0F3880) },
- { PREFIX_TABLE (PREFIX_0F3881) },
- { PREFIX_TABLE (PREFIX_0F3882) },
+ /* c0 */
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* c8 */
{ Bad_Opcode },
- /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
+ /* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* e0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* e8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
+ /* f0 */
{ Bad_Opcode },
- /* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* f8 */
{ Bad_Opcode },
- /* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ },
+ /* XOP_09 */
+ {
+ /* 00 */
{ Bad_Opcode },
- /* b8 */
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0FXOP_09_12) },
{ Bad_Opcode },
- /* c8 */
- { PREFIX_TABLE (PREFIX_0F38C8) },
- { PREFIX_TABLE (PREFIX_0F38C9) },
- { PREFIX_TABLE (PREFIX_0F38CA) },
- { PREFIX_TABLE (PREFIX_0F38CB) },
- { PREFIX_TABLE (PREFIX_0F38CC) },
- { PREFIX_TABLE (PREFIX_0F38CD) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F38CF) },
- /* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F38DB) },
- { PREFIX_TABLE (PREFIX_0F38DC) },
- { PREFIX_TABLE (PREFIX_0F38DD) },
- { PREFIX_TABLE (PREFIX_0F38DE) },
- { PREFIX_TABLE (PREFIX_0F38DF) },
- /* e0 */
{ Bad_Opcode },
+ /* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* e8 */
{ Bad_Opcode },
+ /* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* f0 */
- { PREFIX_TABLE (PREFIX_0F38F0) },
- { PREFIX_TABLE (PREFIX_0F38F1) },
{ Bad_Opcode },
+ /* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F38F5) },
- { PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
- /* f8 */
- { PREFIX_TABLE (PREFIX_0F38F8) },
- { PREFIX_TABLE (PREFIX_0F38F9) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 38 */
{ Bad_Opcode },
- },
- /* THREE_BYTE_0F3A */
- {
- /* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 40 */
{ Bad_Opcode },
- /* 08 */
- { PREFIX_TABLE (PREFIX_0F3A08) },
- { PREFIX_TABLE (PREFIX_0F3A09) },
- { PREFIX_TABLE (PREFIX_0F3A0A) },
- { PREFIX_TABLE (PREFIX_0F3A0B) },
- { PREFIX_TABLE (PREFIX_0F3A0C) },
- { PREFIX_TABLE (PREFIX_0F3A0D) },
- { PREFIX_TABLE (PREFIX_0F3A0E) },
- { "palignr", { MX, EM, Ib }, PREFIX_OPCODE },
- /* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3A14) },
- { PREFIX_TABLE (PREFIX_0F3A15) },
- { PREFIX_TABLE (PREFIX_0F3A16) },
- { PREFIX_TABLE (PREFIX_0F3A17) },
- /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 20 */
- { PREFIX_TABLE (PREFIX_0F3A20) },
- { PREFIX_TABLE (PREFIX_0F3A21) },
- { PREFIX_TABLE (PREFIX_0F3A22) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 28 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 30 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 38 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 40 */
- { PREFIX_TABLE (PREFIX_0F3A40) },
- { PREFIX_TABLE (PREFIX_0F3A41) },
- { PREFIX_TABLE (PREFIX_0F3A42) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3A44) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 48 */
- { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 60 */
- { PREFIX_TABLE (PREFIX_0F3A60) },
- { PREFIX_TABLE (PREFIX_0F3A61) },
- { PREFIX_TABLE (PREFIX_0F3A62) },
- { PREFIX_TABLE (PREFIX_0F3A63) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 80 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_80) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_81) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_82) },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_83) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 90 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) },
/* 98 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) },
/* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3ACC) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3ACE) },
- { PREFIX_TABLE (PREFIX_0F3ACF) },
- /* d0 */
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* d0 */
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) },
/* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F3ADF) },
/* e0 */
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
-};
-
-static const struct dis386 xop_table[][256] = {
- /* XOP_08 */
+ /* XOP_0A */
{
/* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
+ { "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
/* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
/* 90 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
/* 98 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
/* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
- { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
{ Bad_Opcode },
/* a8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 },
+ { Bad_Opcode },
{ Bad_Opcode },
/* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* c0 */
- { "vprotb", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotw", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotd", { XM, Vex_2src_1, Ib }, 0 },
- { "vprotq", { XM, Vex_2src_1, Ib }, 0 },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
/* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
- /* XOP_09 */
+};
+
+static const struct dis386 vex_table[][256] = {
+ /* VEX_0F */
{
/* 00 */
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_TBM_01) },
- { REG_TABLE (REG_XOP_TBM_02) },
+ { Bad_Opcode },
+ { Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
+ { PREFIX_TABLE (PREFIX_VEX_0F10) },
+ { PREFIX_TABLE (PREFIX_VEX_0F11) },
+ { PREFIX_TABLE (PREFIX_VEX_0F12) },
+ { MOD_TABLE (MOD_VEX_0F13) },
+ { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { PREFIX_TABLE (PREFIX_VEX_0F16) },
+ { MOD_TABLE (MOD_VEX_0F17) },
+ /* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_LWPCB) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 18 */
{ Bad_Opcode },
+ /* 20 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 20 */
{ Bad_Opcode },
+ /* 28 */
+ { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
+ { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
+ { PREFIX_TABLE (PREFIX_VEX_0F2A) },
+ { MOD_TABLE (MOD_VEX_0F2B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F2F) },
+ /* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 28 */
{ Bad_Opcode },
+ /* 38 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 30 */
{ Bad_Opcode },
+ /* 40 */
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F41) },
+ { PREFIX_TABLE (PREFIX_VEX_0F42) },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F44) },
+ { PREFIX_TABLE (PREFIX_VEX_0F45) },
+ { PREFIX_TABLE (PREFIX_VEX_0F46) },
+ { PREFIX_TABLE (PREFIX_VEX_0F47) },
+ /* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F4A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F4B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 38 */
{ Bad_Opcode },
+ /* 50 */
+ { MOD_TABLE (MOD_VEX_0F50) },
+ { PREFIX_TABLE (PREFIX_VEX_0F51) },
+ { PREFIX_TABLE (PREFIX_VEX_0F52) },
+ { PREFIX_TABLE (PREFIX_VEX_0F53) },
+ { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ /* 58 */
+ { PREFIX_TABLE (PREFIX_VEX_0F58) },
+ { PREFIX_TABLE (PREFIX_VEX_0F59) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5A) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5B) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F5F) },
+ /* 60 */
+ { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA },
+ /* 68 */
+ { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0F6E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F6F) },
+ /* 70 */
+ { PREFIX_TABLE (PREFIX_VEX_0F70) },
+ { REG_TABLE (REG_VEX_0F71) },
+ { REG_TABLE (REG_VEX_0F72) },
+ { REG_TABLE (REG_VEX_0F73) },
+ { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0F77) },
+ /* 78 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F7C) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7D) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7E) },
+ { PREFIX_TABLE (PREFIX_VEX_0F7F) },
+ /* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 48 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 90 */
+ { PREFIX_TABLE (PREFIX_VEX_0F90) },
+ { PREFIX_TABLE (PREFIX_VEX_0F91) },
+ { PREFIX_TABLE (PREFIX_VEX_0F92) },
+ { PREFIX_TABLE (PREFIX_VEX_0F93) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 50 */
{ Bad_Opcode },
+ /* 98 */
+ { PREFIX_TABLE (PREFIX_VEX_0F98) },
+ { PREFIX_TABLE (PREFIX_VEX_0F99) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* a0 */
{ Bad_Opcode },
- /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* a8 */
{ Bad_Opcode },
- /* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { REG_TABLE (REG_VEX_0FAE) },
{ Bad_Opcode },
+ /* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 78 */
+ { PREFIX_TABLE (PREFIX_VEX_0FC2) },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0FC4) },
+ { VEX_LEN_TABLE (VEX_LEN_0FC5) },
+ { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
+ /* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 80 */
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) },
- { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) },
- { "vfrczss", { XM, EXd }, 0 },
- { "vfrczsd", { XM, EXq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* d0 */
+ { PREFIX_TABLE (PREFIX_VEX_0FD0) },
+ { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0FD6) },
+ { MOD_TABLE (MOD_VEX_0FD7) },
+ /* d8 */
+ { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpminub", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpand", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpandn", { XM, Vex, EXx }, PREFIX_DATA },
+ /* e0 */
+ { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA },
+ { PREFIX_TABLE (PREFIX_VEX_0FE6) },
+ { MOD_TABLE (MOD_VEX_0FE7) },
+ /* e8 */
+ { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpor", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpxor", { XM, Vex, EXx }, PREFIX_DATA },
+ /* f0 */
+ { PREFIX_TABLE (PREFIX_VEX_0FF0) },
+ { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA },
+ { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0FF7) },
+ /* f8 */
+ { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA },
{ Bad_Opcode },
+ },
+ /* VEX_0F38 */
+ {
+ /* 00 */
+ { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA },
+ /* 08 */
+ { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_W_TABLE (VEX_W_0F380C) },
+ { VEX_W_TABLE (VEX_W_0F380D) },
+ { VEX_W_TABLE (VEX_W_0F380E) },
+ { VEX_W_TABLE (VEX_W_0F380F) },
+ /* 10 */
{ Bad_Opcode },
- /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3813) },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3816) },
+ { "vptest", { XM, EXx }, PREFIX_DATA },
+ /* 18 */
+ { VEX_W_TABLE (VEX_W_0F3818) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3819) },
+ { MOD_TABLE (MOD_VEX_0F381A) },
{ Bad_Opcode },
+ { "vpabsb", { XM, EXx }, PREFIX_DATA },
+ { "vpabsw", { XM, EXx }, PREFIX_DATA },
+ { "vpabsd", { XM, EXx }, PREFIX_DATA },
{ Bad_Opcode },
+ /* 20 */
+ { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA },
+ { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA },
+ { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA },
+ { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA },
+ { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA },
+ { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 90 */
- { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- /* 98 */
- { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
- { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 },
+ /* 28 */
+ { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F382A) },
+ { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA },
+ { MOD_TABLE (MOD_VEX_0F382C) },
+ { MOD_TABLE (MOD_VEX_0F382D) },
+ { MOD_TABLE (MOD_VEX_0F382E) },
+ { MOD_TABLE (MOD_VEX_0F382F) },
+ /* 30 */
+ { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA },
+ { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA },
+ { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA },
+ { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA },
+ { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA },
+ { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0F3836) },
+ { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA },
+ /* 38 */
+ { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpminud", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA },
+ /* 40 */
+ { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0F3841) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
+ { VEX_W_TABLE (VEX_W_0F3846) },
+ { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
+ /* 48 */
{ Bad_Opcode },
- /* a0 */
+ { X86_64_TABLE (X86_64_VEX_0F3849) },
{ Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F384B) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 50 */
+ { VEX_W_TABLE (VEX_W_0F3850) },
+ { VEX_W_TABLE (VEX_W_0F3851) },
+ { VEX_W_TABLE (VEX_W_0F3852) },
+ { VEX_W_TABLE (VEX_W_0F3853) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* a8 */
{ Bad_Opcode },
+ /* 58 */
+ { VEX_W_TABLE (VEX_W_0F3858) },
+ { VEX_W_TABLE (VEX_W_0F3859) },
+ { MOD_TABLE (MOD_VEX_0F385A) },
{ Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F385C) },
{ Bad_Opcode },
+ { X86_64_TABLE (X86_64_VEX_0F385E) },
{ Bad_Opcode },
+ /* 60 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* b0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 68 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* b8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* c0 */
{ Bad_Opcode },
- { "vphaddbw", { XM, EXxmm }, 0 },
- { "vphaddbd", { XM, EXxmm }, 0 },
- { "vphaddbq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddwd", { XM, EXxmm }, 0 },
- { "vphaddwq", { XM, EXxmm }, 0 },
- /* c8 */
{ Bad_Opcode },
+ /* 78 */
+ { VEX_W_TABLE (VEX_W_0F3878) },
+ { VEX_W_TABLE (VEX_W_0F3879) },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphadddq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* d0 */
+ /* 80 */
{ Bad_Opcode },
- { "vphaddubw", { XM, EXxmm }, 0 },
- { "vphaddubd", { XM, EXxmm }, 0 },
- { "vphaddubq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphadduwd", { XM, EXxmm }, 0 },
- { "vphadduwq", { XM, EXxmm }, 0 },
- /* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "vphaddudq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 88 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* e0 */
{ Bad_Opcode },
- { "vphsubbw", { XM, EXxmm }, 0 },
- { "vphsubwd", { XM, EXxmm }, 0 },
- { "vphsubdq", { XM, EXxmm }, 0 },
{ Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F388C) },
{ Bad_Opcode },
+ { MOD_TABLE (MOD_VEX_0F388E) },
{ Bad_Opcode },
+ /* 90 */
+ { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
+ { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
+ { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA },
+ { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
{ Bad_Opcode },
- /* e8 */
{ Bad_Opcode },
+ { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ /* 98 */
+ { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ /* a0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ /* a8 */
+ { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ /* b0 */
{ Bad_Opcode },
- /* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ /* b8 */
+ { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA },
+ /* c0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* f8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* c8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- },
- /* XOP_0A */
- {
- /* 00 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F38CF) },
+ /* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 08 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* d8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
+ { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA },
+ { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA },
+ /* e0 */
{ Bad_Opcode },
- /* 10 */
- { "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
- { REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 18 */
{ Bad_Opcode },
+ /* e8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 20 */
{ Bad_Opcode },
+ /* f0 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
+ { REG_TABLE (REG_VEX_0F38F3) },
{ Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
+ { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
+ /* f8 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ },
+ /* VEX_0F3A */
+ {
+ /* 00 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
+ { VEX_W_TABLE (VEX_W_0F3A02) },
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A04) },
+ { VEX_W_TABLE (VEX_W_0F3A05) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
{ Bad_Opcode },
+ /* 08 */
+ { "vroundps", { XM, EXx, Ib }, PREFIX_DATA },
+ { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA },
+ { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA },
+ { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA },
+ { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+ { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+ { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+ { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+ /* 10 */
{ Bad_Opcode },
{ Bad_Opcode },
- /* 30 */
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
+ /* 18 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A1D) },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 20 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
{ Bad_Opcode },
- /* 38 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 28 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 40 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 30 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 48 */
+ /* 38 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 40 */
+ { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
+ { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA },
{ Bad_Opcode },
+ { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
{ Bad_Opcode },
- /* 50 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
{ Bad_Opcode },
+ /* 48 */
+ { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
+ { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
+ { VEX_W_TABLE (VEX_W_0F3A4A) },
+ { VEX_W_TABLE (VEX_W_0F3A4B) },
+ { VEX_W_TABLE (VEX_W_0F3A4C) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 50 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ /* 58 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
+ { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
/* 60 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
+ { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 68 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
/* 70 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 78 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
+ { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA },
+ { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA },
/* 80 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3ACE) },
+ { VEX_W_TABLE (VEX_W_0F3ACF) },
/* d0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
/* e0 */
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* f0 */
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
},
};
-static const struct dis386 vex_table[][256] = {
- /* VEX_0F */
+#include "i386-dis-evex.h"
+
+static const struct dis386 vex_len_table[][2] = {
+ /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
+ {
+ { "vmovlpX", { XM, Vex, EXq }, 0 },
+ },
+
+ /* VEX_LEN_0F12_P_0_M_1 */
+ {
+ { "vmovhlps", { XM, Vex, EXq }, 0 },
+ },
+
+ /* VEX_LEN_0F13_M_0 */
+ {
+ { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
+ },
+
+ /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
+ {
+ { "vmovhpX", { XM, Vex, EXq }, 0 },
+ },
+
+ /* VEX_LEN_0F16_P_0_M_1 */
+ {
+ { "vmovlhps", { XM, Vex, EXq }, 0 },
+ },
+
+ /* VEX_LEN_0F17_M_0 */
+ {
+ { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
+ },
+
+ /* VEX_LEN_0F41_P_0 */
{
- /* 00 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 08 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 10 */
- { PREFIX_TABLE (PREFIX_VEX_0F10) },
- { PREFIX_TABLE (PREFIX_VEX_0F11) },
- { PREFIX_TABLE (PREFIX_VEX_0F12) },
- { MOD_TABLE (MOD_VEX_0F13) },
- { "vunpcklpX", { XM, Vex, EXx }, 0 },
- { "vunpckhpX", { XM, Vex, EXx }, 0 },
- { PREFIX_TABLE (PREFIX_VEX_0F16) },
- { MOD_TABLE (MOD_VEX_0F17) },
- /* 18 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 20 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 28 */
- { "vmovapX", { XM, EXx }, 0 },
- { "vmovapX", { EXxS, XM }, 0 },
- { PREFIX_TABLE (PREFIX_VEX_0F2A) },
- { MOD_TABLE (MOD_VEX_0F2B) },
- { PREFIX_TABLE (PREFIX_VEX_0F2C) },
- { PREFIX_TABLE (PREFIX_VEX_0F2D) },
- { PREFIX_TABLE (PREFIX_VEX_0F2E) },
- { PREFIX_TABLE (PREFIX_VEX_0F2F) },
- /* 30 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 38 */
- { Bad_Opcode },
- { Bad_Opcode },
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F41_P_2 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F42_P_0 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F42_P_2 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F44_P_0 */
+ {
+ { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
+ },
+ /* VEX_LEN_0F44_P_2 */
+ {
+ { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
+ },
+ /* VEX_LEN_0F45_P_0 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F45_P_2 */
+ {
{ Bad_Opcode },
- /* 40 */
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F41) },
- { PREFIX_TABLE (PREFIX_VEX_0F42) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F44) },
- { PREFIX_TABLE (PREFIX_VEX_0F45) },
- { PREFIX_TABLE (PREFIX_VEX_0F46) },
- { PREFIX_TABLE (PREFIX_VEX_0F47) },
- /* 48 */
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F4A) },
- { PREFIX_TABLE (PREFIX_VEX_0F4B) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 50 */
- { MOD_TABLE (MOD_VEX_0F50) },
- { PREFIX_TABLE (PREFIX_VEX_0F51) },
- { PREFIX_TABLE (PREFIX_VEX_0F52) },
- { PREFIX_TABLE (PREFIX_VEX_0F53) },
- { "vandpX", { XM, Vex, EXx }, 0 },
- { "vandnpX", { XM, Vex, EXx }, 0 },
- { "vorpX", { XM, Vex, EXx }, 0 },
- { "vxorpX", { XM, Vex, EXx }, 0 },
- /* 58 */
- { PREFIX_TABLE (PREFIX_VEX_0F58) },
- { PREFIX_TABLE (PREFIX_VEX_0F59) },
- { PREFIX_TABLE (PREFIX_VEX_0F5A) },
- { PREFIX_TABLE (PREFIX_VEX_0F5B) },
- { PREFIX_TABLE (PREFIX_VEX_0F5C) },
- { PREFIX_TABLE (PREFIX_VEX_0F5D) },
- { PREFIX_TABLE (PREFIX_VEX_0F5E) },
- { PREFIX_TABLE (PREFIX_VEX_0F5F) },
- /* 60 */
- { PREFIX_TABLE (PREFIX_VEX_0F60) },
- { PREFIX_TABLE (PREFIX_VEX_0F61) },
- { PREFIX_TABLE (PREFIX_VEX_0F62) },
- { PREFIX_TABLE (PREFIX_VEX_0F63) },
- { PREFIX_TABLE (PREFIX_VEX_0F64) },
- { PREFIX_TABLE (PREFIX_VEX_0F65) },
- { PREFIX_TABLE (PREFIX_VEX_0F66) },
- { PREFIX_TABLE (PREFIX_VEX_0F67) },
- /* 68 */
- { PREFIX_TABLE (PREFIX_VEX_0F68) },
- { PREFIX_TABLE (PREFIX_VEX_0F69) },
- { PREFIX_TABLE (PREFIX_VEX_0F6A) },
- { PREFIX_TABLE (PREFIX_VEX_0F6B) },
- { PREFIX_TABLE (PREFIX_VEX_0F6C) },
- { PREFIX_TABLE (PREFIX_VEX_0F6D) },
- { PREFIX_TABLE (PREFIX_VEX_0F6E) },
- { PREFIX_TABLE (PREFIX_VEX_0F6F) },
- /* 70 */
- { PREFIX_TABLE (PREFIX_VEX_0F70) },
- { REG_TABLE (REG_VEX_0F71) },
- { REG_TABLE (REG_VEX_0F72) },
- { REG_TABLE (REG_VEX_0F73) },
- { PREFIX_TABLE (PREFIX_VEX_0F74) },
- { PREFIX_TABLE (PREFIX_VEX_0F75) },
- { PREFIX_TABLE (PREFIX_VEX_0F76) },
- { PREFIX_TABLE (PREFIX_VEX_0F77) },
- /* 78 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F7C) },
- { PREFIX_TABLE (PREFIX_VEX_0F7D) },
- { PREFIX_TABLE (PREFIX_VEX_0F7E) },
- { PREFIX_TABLE (PREFIX_VEX_0F7F) },
- /* 80 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 88 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 90 */
- { PREFIX_TABLE (PREFIX_VEX_0F90) },
- { PREFIX_TABLE (PREFIX_VEX_0F91) },
- { PREFIX_TABLE (PREFIX_VEX_0F92) },
- { PREFIX_TABLE (PREFIX_VEX_0F93) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 98 */
- { PREFIX_TABLE (PREFIX_VEX_0F98) },
- { PREFIX_TABLE (PREFIX_VEX_0F99) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* a0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* a8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { REG_TABLE (REG_VEX_0FAE) },
- { Bad_Opcode },
- /* b0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* b8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* c0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0FC2) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0FC4) },
- { PREFIX_TABLE (PREFIX_VEX_0FC5) },
- { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
- { Bad_Opcode },
- /* c8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* d0 */
- { PREFIX_TABLE (PREFIX_VEX_0FD0) },
- { PREFIX_TABLE (PREFIX_VEX_0FD1) },
- { PREFIX_TABLE (PREFIX_VEX_0FD2) },
- { PREFIX_TABLE (PREFIX_VEX_0FD3) },
- { PREFIX_TABLE (PREFIX_VEX_0FD4) },
- { PREFIX_TABLE (PREFIX_VEX_0FD5) },
- { PREFIX_TABLE (PREFIX_VEX_0FD6) },
- { PREFIX_TABLE (PREFIX_VEX_0FD7) },
- /* d8 */
- { PREFIX_TABLE (PREFIX_VEX_0FD8) },
- { PREFIX_TABLE (PREFIX_VEX_0FD9) },
- { PREFIX_TABLE (PREFIX_VEX_0FDA) },
- { PREFIX_TABLE (PREFIX_VEX_0FDB) },
- { PREFIX_TABLE (PREFIX_VEX_0FDC) },
- { PREFIX_TABLE (PREFIX_VEX_0FDD) },
- { PREFIX_TABLE (PREFIX_VEX_0FDE) },
- { PREFIX_TABLE (PREFIX_VEX_0FDF) },
- /* e0 */
- { PREFIX_TABLE (PREFIX_VEX_0FE0) },
- { PREFIX_TABLE (PREFIX_VEX_0FE1) },
- { PREFIX_TABLE (PREFIX_VEX_0FE2) },
- { PREFIX_TABLE (PREFIX_VEX_0FE3) },
- { PREFIX_TABLE (PREFIX_VEX_0FE4) },
- { PREFIX_TABLE (PREFIX_VEX_0FE5) },
- { PREFIX_TABLE (PREFIX_VEX_0FE6) },
- { PREFIX_TABLE (PREFIX_VEX_0FE7) },
- /* e8 */
- { PREFIX_TABLE (PREFIX_VEX_0FE8) },
- { PREFIX_TABLE (PREFIX_VEX_0FE9) },
- { PREFIX_TABLE (PREFIX_VEX_0FEA) },
- { PREFIX_TABLE (PREFIX_VEX_0FEB) },
- { PREFIX_TABLE (PREFIX_VEX_0FEC) },
- { PREFIX_TABLE (PREFIX_VEX_0FED) },
- { PREFIX_TABLE (PREFIX_VEX_0FEE) },
- { PREFIX_TABLE (PREFIX_VEX_0FEF) },
- /* f0 */
- { PREFIX_TABLE (PREFIX_VEX_0FF0) },
- { PREFIX_TABLE (PREFIX_VEX_0FF1) },
- { PREFIX_TABLE (PREFIX_VEX_0FF2) },
- { PREFIX_TABLE (PREFIX_VEX_0FF3) },
- { PREFIX_TABLE (PREFIX_VEX_0FF4) },
- { PREFIX_TABLE (PREFIX_VEX_0FF5) },
- { PREFIX_TABLE (PREFIX_VEX_0FF6) },
- { PREFIX_TABLE (PREFIX_VEX_0FF7) },
- /* f8 */
- { PREFIX_TABLE (PREFIX_VEX_0FF8) },
- { PREFIX_TABLE (PREFIX_VEX_0FF9) },
- { PREFIX_TABLE (PREFIX_VEX_0FFA) },
- { PREFIX_TABLE (PREFIX_VEX_0FFB) },
- { PREFIX_TABLE (PREFIX_VEX_0FFC) },
- { PREFIX_TABLE (PREFIX_VEX_0FFD) },
- { PREFIX_TABLE (PREFIX_VEX_0FFE) },
- { Bad_Opcode },
- },
- /* VEX_0F38 */
- {
- /* 00 */
- { PREFIX_TABLE (PREFIX_VEX_0F3800) },
- { PREFIX_TABLE (PREFIX_VEX_0F3801) },
- { PREFIX_TABLE (PREFIX_VEX_0F3802) },
- { PREFIX_TABLE (PREFIX_VEX_0F3803) },
- { PREFIX_TABLE (PREFIX_VEX_0F3804) },
- { PREFIX_TABLE (PREFIX_VEX_0F3805) },
- { PREFIX_TABLE (PREFIX_VEX_0F3806) },
- { PREFIX_TABLE (PREFIX_VEX_0F3807) },
- /* 08 */
- { PREFIX_TABLE (PREFIX_VEX_0F3808) },
- { PREFIX_TABLE (PREFIX_VEX_0F3809) },
- { PREFIX_TABLE (PREFIX_VEX_0F380A) },
- { PREFIX_TABLE (PREFIX_VEX_0F380B) },
- { PREFIX_TABLE (PREFIX_VEX_0F380C) },
- { PREFIX_TABLE (PREFIX_VEX_0F380D) },
- { PREFIX_TABLE (PREFIX_VEX_0F380E) },
- { PREFIX_TABLE (PREFIX_VEX_0F380F) },
- /* 10 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3813) },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3816) },
- { PREFIX_TABLE (PREFIX_VEX_0F3817) },
- /* 18 */
- { PREFIX_TABLE (PREFIX_VEX_0F3818) },
- { PREFIX_TABLE (PREFIX_VEX_0F3819) },
- { PREFIX_TABLE (PREFIX_VEX_0F381A) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F381C) },
- { PREFIX_TABLE (PREFIX_VEX_0F381D) },
- { PREFIX_TABLE (PREFIX_VEX_0F381E) },
- { Bad_Opcode },
- /* 20 */
- { PREFIX_TABLE (PREFIX_VEX_0F3820) },
- { PREFIX_TABLE (PREFIX_VEX_0F3821) },
- { PREFIX_TABLE (PREFIX_VEX_0F3822) },
- { PREFIX_TABLE (PREFIX_VEX_0F3823) },
- { PREFIX_TABLE (PREFIX_VEX_0F3824) },
- { PREFIX_TABLE (PREFIX_VEX_0F3825) },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 28 */
- { PREFIX_TABLE (PREFIX_VEX_0F3828) },
- { PREFIX_TABLE (PREFIX_VEX_0F3829) },
- { PREFIX_TABLE (PREFIX_VEX_0F382A) },
- { PREFIX_TABLE (PREFIX_VEX_0F382B) },
- { PREFIX_TABLE (PREFIX_VEX_0F382C) },
- { PREFIX_TABLE (PREFIX_VEX_0F382D) },
- { PREFIX_TABLE (PREFIX_VEX_0F382E) },
- { PREFIX_TABLE (PREFIX_VEX_0F382F) },
- /* 30 */
- { PREFIX_TABLE (PREFIX_VEX_0F3830) },
- { PREFIX_TABLE (PREFIX_VEX_0F3831) },
- { PREFIX_TABLE (PREFIX_VEX_0F3832) },
- { PREFIX_TABLE (PREFIX_VEX_0F3833) },
- { PREFIX_TABLE (PREFIX_VEX_0F3834) },
- { PREFIX_TABLE (PREFIX_VEX_0F3835) },
- { PREFIX_TABLE (PREFIX_VEX_0F3836) },
- { PREFIX_TABLE (PREFIX_VEX_0F3837) },
- /* 38 */
- { PREFIX_TABLE (PREFIX_VEX_0F3838) },
- { PREFIX_TABLE (PREFIX_VEX_0F3839) },
- { PREFIX_TABLE (PREFIX_VEX_0F383A) },
- { PREFIX_TABLE (PREFIX_VEX_0F383B) },
- { PREFIX_TABLE (PREFIX_VEX_0F383C) },
- { PREFIX_TABLE (PREFIX_VEX_0F383D) },
- { PREFIX_TABLE (PREFIX_VEX_0F383E) },
- { PREFIX_TABLE (PREFIX_VEX_0F383F) },
- /* 40 */
- { PREFIX_TABLE (PREFIX_VEX_0F3840) },
- { PREFIX_TABLE (PREFIX_VEX_0F3841) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3845) },
- { PREFIX_TABLE (PREFIX_VEX_0F3846) },
- { PREFIX_TABLE (PREFIX_VEX_0F3847) },
- /* 48 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 50 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 58 */
- { PREFIX_TABLE (PREFIX_VEX_0F3858) },
- { PREFIX_TABLE (PREFIX_VEX_0F3859) },
- { PREFIX_TABLE (PREFIX_VEX_0F385A) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 60 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 68 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 70 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 78 */
- { PREFIX_TABLE (PREFIX_VEX_0F3878) },
- { PREFIX_TABLE (PREFIX_VEX_0F3879) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 80 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 88 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F388C) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F388E) },
- { Bad_Opcode },
- /* 90 */
- { PREFIX_TABLE (PREFIX_VEX_0F3890) },
- { PREFIX_TABLE (PREFIX_VEX_0F3891) },
- { PREFIX_TABLE (PREFIX_VEX_0F3892) },
- { PREFIX_TABLE (PREFIX_VEX_0F3893) },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3896) },
- { PREFIX_TABLE (PREFIX_VEX_0F3897) },
- /* 98 */
- { PREFIX_TABLE (PREFIX_VEX_0F3898) },
- { PREFIX_TABLE (PREFIX_VEX_0F3899) },
- { PREFIX_TABLE (PREFIX_VEX_0F389A) },
- { PREFIX_TABLE (PREFIX_VEX_0F389B) },
- { PREFIX_TABLE (PREFIX_VEX_0F389C) },
- { PREFIX_TABLE (PREFIX_VEX_0F389D) },
- { PREFIX_TABLE (PREFIX_VEX_0F389E) },
- { PREFIX_TABLE (PREFIX_VEX_0F389F) },
- /* a0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38A6) },
- { PREFIX_TABLE (PREFIX_VEX_0F38A7) },
- /* a8 */
- { PREFIX_TABLE (PREFIX_VEX_0F38A8) },
- { PREFIX_TABLE (PREFIX_VEX_0F38A9) },
- { PREFIX_TABLE (PREFIX_VEX_0F38AA) },
- { PREFIX_TABLE (PREFIX_VEX_0F38AB) },
- { PREFIX_TABLE (PREFIX_VEX_0F38AC) },
- { PREFIX_TABLE (PREFIX_VEX_0F38AD) },
- { PREFIX_TABLE (PREFIX_VEX_0F38AE) },
- { PREFIX_TABLE (PREFIX_VEX_0F38AF) },
- /* b0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38B6) },
- { PREFIX_TABLE (PREFIX_VEX_0F38B7) },
- /* b8 */
- { PREFIX_TABLE (PREFIX_VEX_0F38B8) },
- { PREFIX_TABLE (PREFIX_VEX_0F38B9) },
- { PREFIX_TABLE (PREFIX_VEX_0F38BA) },
- { PREFIX_TABLE (PREFIX_VEX_0F38BB) },
- { PREFIX_TABLE (PREFIX_VEX_0F38BC) },
- { PREFIX_TABLE (PREFIX_VEX_0F38BD) },
- { PREFIX_TABLE (PREFIX_VEX_0F38BE) },
- { PREFIX_TABLE (PREFIX_VEX_0F38BF) },
- /* c0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* c8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38CF) },
- /* d0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* d8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38DB) },
- { PREFIX_TABLE (PREFIX_VEX_0F38DC) },
- { PREFIX_TABLE (PREFIX_VEX_0F38DD) },
- { PREFIX_TABLE (PREFIX_VEX_0F38DE) },
- { PREFIX_TABLE (PREFIX_VEX_0F38DF) },
- /* e0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* e8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* f0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38F2) },
- { REG_TABLE (REG_VEX_0F38F3) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F38F5) },
- { PREFIX_TABLE (PREFIX_VEX_0F38F6) },
- { PREFIX_TABLE (PREFIX_VEX_0F38F7) },
- /* f8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- },
- /* VEX_0F3A */
- {
- /* 00 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A00) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A01) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A02) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3A04) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A05) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A06) },
- { Bad_Opcode },
- /* 08 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A08) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A09) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A0A) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A0B) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A0C) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A0D) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A0E) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A0F) },
- /* 10 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3A14) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A15) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A16) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A17) },
- /* 18 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A18) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A19) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3A1D) },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 20 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A20) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A21) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A22) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 28 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 30 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A30) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A31) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A32) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A33) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 38 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A38) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A39) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 40 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A40) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A41) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A42) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3A44) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3A46) },
- { Bad_Opcode },
- /* 48 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A48) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A49) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A4A) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A4B) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A4C) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 50 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 58 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3A5C) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A5D) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A5E) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A5F) },
- /* 60 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A60) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A61) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A62) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A63) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 68 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A68) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A69) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A6A) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A6B) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A6C) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A6D) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A6E) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A6F) },
- /* 70 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 78 */
- { PREFIX_TABLE (PREFIX_VEX_0F3A78) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A79) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A7A) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A7B) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A7C) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A7D) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A7E) },
- { PREFIX_TABLE (PREFIX_VEX_0F3A7F) },
- /* 80 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 88 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 90 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* 98 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* a0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* a8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* b0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* b8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* c0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* c8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE(PREFIX_VEX_0F3ACE) },
- { PREFIX_TABLE(PREFIX_VEX_0F3ACF) },
- /* d0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* d8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F3ADF) },
- /* e0 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* e8 */
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* f0 */
- { PREFIX_TABLE (PREFIX_VEX_0F3AF0) },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- /* f8 */
+ { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F46_P_0 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F46_P_2 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F47_P_0 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F47_P_2 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F4A_P_0 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F4A_P_2 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
+ },
+ /* VEX_LEN_0F4B_P_0 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
+ },
+ /* VEX_LEN_0F4B_P_2 */
+ {
{ Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
},
-};
-#include "i386-dis-evex.h"
+ /* VEX_LEN_0F6E */
+ {
+ { "vmovK", { XMScalar, Edq }, PREFIX_DATA },
+ },
-static const struct dis386 vex_len_table[][2] = {
- /* VEX_LEN_0F12_P_0_M_0 */
+ /* VEX_LEN_0F77 */
{
- { "vmovlps", { XM, Vex128, EXq }, 0 },
+ { "vzeroupper", { XX }, 0 },
+ { "vzeroall", { XX }, 0 },
},
- /* VEX_LEN_0F12_P_0_M_1 */
+ /* VEX_LEN_0F7E_P_1 */
{
- { "vmovhlps", { XM, Vex128, EXq }, 0 },
+ { "vmovq", { XMScalar, EXxmm_mq }, 0 },
},
- /* VEX_LEN_0F12_P_2 */
+ /* VEX_LEN_0F7E_P_2 */
{
- { "vmovlpd", { XM, Vex128, EXq }, 0 },
+ { "vmovK", { Edq, XMScalar }, 0 },
},
- /* VEX_LEN_0F13_M_0 */
+ /* VEX_LEN_0F90_P_0 */
{
- { "vmovlpX", { EXq, XM }, 0 },
+ { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
},
- /* VEX_LEN_0F16_P_0_M_0 */
+ /* VEX_LEN_0F90_P_2 */
{
- { "vmovhps", { XM, Vex128, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
},
- /* VEX_LEN_0F16_P_0_M_1 */
+ /* VEX_LEN_0F91_P_0 */
{
- { "vmovlhps", { XM, Vex128, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
},
- /* VEX_LEN_0F16_P_2 */
+ /* VEX_LEN_0F91_P_2 */
{
- { "vmovhpd", { XM, Vex128, EXq }, 0 },
+ { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
},
- /* VEX_LEN_0F17_M_0 */
+ /* VEX_LEN_0F92_P_0 */
{
- { "vmovhpX", { EXq, XM }, 0 },
+ { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
},
- /* VEX_LEN_0F41_P_0 */
+ /* VEX_LEN_0F92_P_2 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
},
- /* VEX_LEN_0F41_P_2 */
+
+ /* VEX_LEN_0F92_P_3 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) },
+ { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
},
- /* VEX_LEN_0F42_P_0 */
+
+ /* VEX_LEN_0F93_P_0 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
},
- /* VEX_LEN_0F42_P_2 */
+
+ /* VEX_LEN_0F93_P_2 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
},
- /* VEX_LEN_0F44_P_0 */
+
+ /* VEX_LEN_0F93_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
},
- /* VEX_LEN_0F44_P_2 */
+
+ /* VEX_LEN_0F98_P_0 */
{
- { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) },
+ { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
},
- /* VEX_LEN_0F45_P_0 */
+
+ /* VEX_LEN_0F98_P_2 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
},
- /* VEX_LEN_0F45_P_2 */
+
+ /* VEX_LEN_0F99_P_0 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
},
- /* VEX_LEN_0F46_P_0 */
+
+ /* VEX_LEN_0F99_P_2 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
},
- /* VEX_LEN_0F46_P_2 */
+
+ /* VEX_LEN_0FAE_R_2_M_0 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) },
+ { "vldmxcsr", { Md }, 0 },
},
- /* VEX_LEN_0F47_P_0 */
+
+ /* VEX_LEN_0FAE_R_3_M_0 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) },
+ { "vstmxcsr", { Md }, 0 },
},
- /* VEX_LEN_0F47_P_2 */
+
+ /* VEX_LEN_0FC4 */
+ {
+ { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0FC5 */
+ {
+ { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0FD6 */
+ {
+ { "vmovq", { EXqS, XMScalar }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0FF7 */
+ {
+ { "vmaskmovdqu", { XM, XS }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0F3816 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F3816_L_1) },
},
- /* VEX_LEN_0F4A_P_0 */
+
+ /* VEX_LEN_0F3819 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F3819_L_1) },
},
- /* VEX_LEN_0F4A_P_2 */
+
+ /* VEX_LEN_0F381A_M_0 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) },
},
- /* VEX_LEN_0F4B_P_0 */
+
+ /* VEX_LEN_0F3836 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F3836) },
},
- /* VEX_LEN_0F4B_P_2 */
+
+ /* VEX_LEN_0F3841 */
+ {
+ { "vphminposuw", { XM, EXx }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */
+ {
+ { "ldtilecfg", { M }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */
+ {
+ { "tilerelease", { Skip_MODRM }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */
+ {
+ { "sttilecfg", { M }, 0 },
+ },
+
+ /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */
+ {
+ { "tilezero", { TMM, Skip_MODRM }, 0 },
+ },
+
+ /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */
+ {
+ { "tilestored", { MVexSIBMEM, TMM }, 0 },
+ },
+ /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */
+ {
+ { "tileloaddt1", { TMM, MVexSIBMEM }, 0 },
+ },
+
+ /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */
+ {
+ { "tileloadd", { TMM, MVexSIBMEM }, 0 },
+ },
+
+ /* VEX_LEN_0F385A_M_0 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
+ { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) },
+ },
+
+ /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */
+ {
+ { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */
+ {
+ { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */
+ {
+ { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */
+ {
+ { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */
+ {
+ { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 },
+ },
+
+ /* VEX_LEN_0F38DB */
+ {
+ { "vaesimc", { XM, EXx }, PREFIX_DATA },
+ },
+
+ /* VEX_LEN_0F38F2 */
+ {
+ { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE },
+ },
+
+ /* VEX_LEN_0F38F3_R_1 */
+ {
+ { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE },
+ },
+
+ /* VEX_LEN_0F38F3_R_2 */
+ {
+ { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE },
+ },
+
+ /* VEX_LEN_0F38F3_R_3 */
+ {
+ { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE },
+ },
+
+ /* VEX_LEN_0F38F5_P_0 */
+ {
+ { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F5_P_1 */
+ {
+ { "pextS", { Gdq, VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F5_P_3 */
+ {
+ { "pdepS", { Gdq, VexGdq, Edq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F6_P_3 */
+ {
+ { "mulxS", { Gdq, VexGdq, Edq }, 0 },
},
- /* VEX_LEN_0F6E_P_2 */
+ /* VEX_LEN_0F38F7_P_0 */
+ {
+ { "bextrS", { Gdq, Edq, VexGdq }, 0 },
+ },
+
+ /* VEX_LEN_0F38F7_P_1 */
{
- { "vmovK", { XMScalar, Edq }, 0 },
+ { "sarxS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0F77_P_1 */
+ /* VEX_LEN_0F38F7_P_2 */
{
- { "vzeroupper", { XX }, 0 },
- { "vzeroall", { XX }, 0 },
+ { "shlxS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0F7E_P_1 */
+ /* VEX_LEN_0F38F7_P_3 */
{
- { "vmovq", { XMScalar, EXqScalar }, 0 },
+ { "shrxS", { Gdq, Edq, VexGdq }, 0 },
},
- /* VEX_LEN_0F7E_P_2 */
+ /* VEX_LEN_0F3A00 */
{
- { "vmovK", { Edq, XMScalar }, 0 },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
},
- /* VEX_LEN_0F90_P_0 */
+ /* VEX_LEN_0F3A01 */
{
- { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
},
- /* VEX_LEN_0F90_P_2 */
+ /* VEX_LEN_0F3A06 */
{
- { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
},
- /* VEX_LEN_0F91_P_0 */
+ /* VEX_LEN_0F3A14 */
{
- { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) },
+ { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F91_P_2 */
+ /* VEX_LEN_0F3A15 */
{
- { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) },
+ { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F92_P_0 */
+ /* VEX_LEN_0F3A16 */
{
- { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) },
+ { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F92_P_2 */
+ /* VEX_LEN_0F3A17 */
{
- { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) },
+ { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F92_P_3 */
+ /* VEX_LEN_0F3A18 */
{
- { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
},
- /* VEX_LEN_0F93_P_0 */
+ /* VEX_LEN_0F3A19 */
{
- { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
},
- /* VEX_LEN_0F93_P_2 */
+ /* VEX_LEN_0F3A20 */
{
- { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) },
+ { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F93_P_3 */
+ /* VEX_LEN_0F3A21 */
{
- { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
+ { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F98_P_0 */
+ /* VEX_LEN_0F3A22 */
{
- { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) },
+ { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F98_P_2 */
+ /* VEX_LEN_0F3A30 */
{
- { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F3A30_L_0) },
},
- /* VEX_LEN_0F99_P_0 */
+ /* VEX_LEN_0F3A31 */
{
- { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F3A31_L_0) },
},
- /* VEX_LEN_0F99_P_2 */
+ /* VEX_LEN_0F3A32 */
{
- { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F3A32_L_0) },
},
- /* VEX_LEN_0FAE_R_2_M_0 */
+ /* VEX_LEN_0F3A33 */
{
- { "vldmxcsr", { Md }, 0 },
+ { MOD_TABLE (MOD_VEX_0F3A33_L_0) },
},
- /* VEX_LEN_0FAE_R_3_M_0 */
+ /* VEX_LEN_0F3A38 */
{
- { "vstmxcsr", { Md }, 0 },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
},
- /* VEX_LEN_0FC4_P_2 */
+ /* VEX_LEN_0F3A39 */
{
- { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
},
- /* VEX_LEN_0FC5_P_2 */
+ /* VEX_LEN_0F3A41 */
{
- { "vpextrw", { Gdq, XS, Ib }, 0 },
+ { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0FD6_P_2 */
+ /* VEX_LEN_0F3A46 */
{
- { "vmovq", { EXqScalarS, XMScalar }, 0 },
+ { Bad_Opcode },
+ { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
},
- /* VEX_LEN_0FF7_P_2 */
+ /* VEX_LEN_0F3A60 */
{
- { "vmaskmovdqu", { XM, XS }, 0 },
+ { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F3816_P_2 */
+ /* VEX_LEN_0F3A61 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3816_P_2) },
+ { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F3819_P_2 */
+ /* VEX_LEN_0F3A62 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3819_P_2) },
+ { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F381A_P_2_M_0 */
+ /* VEX_LEN_0F3A63 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) },
+ { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F3836_P_2 */
+ /* VEX_LEN_0F3ADF */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3836_P_2) },
+ { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
},
- /* VEX_LEN_0F3841_P_2 */
+ /* VEX_LEN_0F3AF0_P_3 */
{
- { "vphminposuw", { XM, EXx }, 0 },
+ { "rorxS", { Gdq, Edq, Ib }, 0 },
},
- /* VEX_LEN_0F385A_P_2_M_0 */
+ /* VEX_LEN_0FXOP_08_85 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) },
},
- /* VEX_LEN_0F38DB_P_2 */
+ /* VEX_LEN_0FXOP_08_86 */
{
- { "vaesimc", { XM, EXx }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) },
},
- /* VEX_LEN_0F38F2_P_0 */
+ /* VEX_LEN_0FXOP_08_87 */
{
- { "andnS", { Gdq, VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) },
},
- /* VEX_LEN_0F38F3_R_1_P_0 */
+ /* VEX_LEN_0FXOP_08_8E */
{
- { "blsrS", { VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) },
},
- /* VEX_LEN_0F38F3_R_2_P_0 */
+ /* VEX_LEN_0FXOP_08_8F */
{
- { "blsmskS", { VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) },
},
- /* VEX_LEN_0F38F3_R_3_P_0 */
+ /* VEX_LEN_0FXOP_08_95 */
{
- { "blsiS", { VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) },
},
- /* VEX_LEN_0F38F5_P_0 */
+ /* VEX_LEN_0FXOP_08_96 */
{
- { "bzhiS", { Gdq, Edq, VexGdq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) },
},
- /* VEX_LEN_0F38F5_P_1 */
+ /* VEX_LEN_0FXOP_08_97 */
{
- { "pextS", { Gdq, VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) },
},
- /* VEX_LEN_0F38F5_P_3 */
+ /* VEX_LEN_0FXOP_08_9E */
{
- { "pdepS", { Gdq, VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) },
},
- /* VEX_LEN_0F38F6_P_3 */
+ /* VEX_LEN_0FXOP_08_9F */
{
- { "mulxS", { Gdq, VexGdq, Edq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) },
},
- /* VEX_LEN_0F38F7_P_0 */
+ /* VEX_LEN_0FXOP_08_A3 */
{
- { "bextrS", { Gdq, Edq, VexGdq }, 0 },
+ { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- /* VEX_LEN_0F38F7_P_1 */
+ /* VEX_LEN_0FXOP_08_A6 */
{
- { "sarxS", { Gdq, Edq, VexGdq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) },
},
- /* VEX_LEN_0F38F7_P_2 */
+ /* VEX_LEN_0FXOP_08_B6 */
{
- { "shlxS", { Gdq, Edq, VexGdq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) },
},
- /* VEX_LEN_0F38F7_P_3 */
+ /* VEX_LEN_0FXOP_08_C0 */
{
- { "shrxS", { Gdq, Edq, VexGdq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) },
},
- /* VEX_LEN_0F3A00_P_2 */
+ /* VEX_LEN_0FXOP_08_C1 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A00_P_2) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) },
},
- /* VEX_LEN_0F3A01_P_2 */
+ /* VEX_LEN_0FXOP_08_C2 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A01_P_2) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) },
},
- /* VEX_LEN_0F3A06_P_2 */
+ /* VEX_LEN_0FXOP_08_C3 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A06_P_2) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) },
},
- /* VEX_LEN_0F3A14_P_2 */
+ /* VEX_LEN_0FXOP_08_CC */
{
- { "vpextrb", { Edqb, XM, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) },
},
- /* VEX_LEN_0F3A15_P_2 */
+ /* VEX_LEN_0FXOP_08_CD */
{
- { "vpextrw", { Edqw, XM, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) },
},
- /* VEX_LEN_0F3A16_P_2 */
+ /* VEX_LEN_0FXOP_08_CE */
{
- { "vpextrK", { Edq, XM, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) },
},
- /* VEX_LEN_0F3A17_P_2 */
+ /* VEX_LEN_0FXOP_08_CF */
{
- { "vextractps", { Edqd, XM, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) },
},
- /* VEX_LEN_0F3A18_P_2 */
+ /* VEX_LEN_0FXOP_08_EC */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A18_P_2) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) },
},
- /* VEX_LEN_0F3A19_P_2 */
+ /* VEX_LEN_0FXOP_08_ED */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A19_P_2) },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) },
},
- /* VEX_LEN_0F3A20_P_2 */
+ /* VEX_LEN_0FXOP_08_EE */
{
- { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) },
},
- /* VEX_LEN_0F3A21_P_2 */
+ /* VEX_LEN_0FXOP_08_EF */
{
- { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) },
},
- /* VEX_LEN_0F3A22_P_2 */
+ /* VEX_LEN_0FXOP_09_01 */
{
- { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 },
+ { REG_TABLE (REG_0FXOP_09_01_L_0) },
},
- /* VEX_LEN_0F3A30_P_2 */
+ /* VEX_LEN_0FXOP_09_02 */
{
- { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) },
+ { REG_TABLE (REG_0FXOP_09_02_L_0) },
},
- /* VEX_LEN_0F3A31_P_2 */
+ /* VEX_LEN_0FXOP_09_12_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) },
+ { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) },
},
- /* VEX_LEN_0F3A32_P_2 */
+ /* VEX_LEN_0FXOP_09_82_W_0 */
{
- { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) },
+ { "vfrczss", { XM, EXd }, 0 },
},
- /* VEX_LEN_0F3A33_P_2 */
+ /* VEX_LEN_0FXOP_09_83_W_0 */
{
- { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) },
+ { "vfrczsd", { XM, EXq }, 0 },
},
- /* VEX_LEN_0F3A38_P_2 */
+ /* VEX_LEN_0FXOP_09_90 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A38_P_2) },
+ { "vprotb", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A39_P_2 */
+ /* VEX_LEN_0FXOP_09_91 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A39_P_2) },
+ { "vprotw", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A41_P_2 */
+ /* VEX_LEN_0FXOP_09_92 */
{
- { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
+ { "vprotd", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A46_P_2 */
+ /* VEX_LEN_0FXOP_09_93 */
{
- { Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A46_P_2) },
+ { "vprotq", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A60_P_2 */
+ /* VEX_LEN_0FXOP_09_94 */
{
- { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
+ { "vpshlb", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A61_P_2 */
+ /* VEX_LEN_0FXOP_09_95 */
{
- { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 },
+ { "vpshlw", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A62_P_2 */
+ /* VEX_LEN_0FXOP_09_96 */
{
- { "vpcmpistrm", { XM, EXx, Ib }, 0 },
+ { "vpshld", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A63_P_2 */
+ /* VEX_LEN_0FXOP_09_97 */
{
- { "vpcmpistri", { XM, EXx, Ib }, 0 },
+ { "vpshlq", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A6A_P_2 */
+ /* VEX_LEN_0FXOP_09_98 */
{
- { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { "vpshab", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A6B_P_2 */
+ /* VEX_LEN_0FXOP_09_99 */
{
- { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { "vpshaw", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A6E_P_2 */
+ /* VEX_LEN_0FXOP_09_9A */
{
- { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { "vpshad", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A6F_P_2 */
+ /* VEX_LEN_0FXOP_09_9B */
{
- { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { "vpshaq", { XM, EXx, VexW }, 0 },
},
- /* VEX_LEN_0F3A7A_P_2 */
+ /* VEX_LEN_0FXOP_09_C1 */
{
- { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) },
},
- /* VEX_LEN_0F3A7B_P_2 */
+ /* VEX_LEN_0FXOP_09_C2 */
{
- { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) },
},
- /* VEX_LEN_0F3A7E_P_2 */
+ /* VEX_LEN_0FXOP_09_C3 */
{
- { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) },
},
- /* VEX_LEN_0F3A7F_P_2 */
+ /* VEX_LEN_0FXOP_09_C6 */
{
- { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) },
},
- /* VEX_LEN_0F3ADF_P_2 */
+ /* VEX_LEN_0FXOP_09_C7 */
{
- { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) },
},
- /* VEX_LEN_0F3AF0_P_3 */
+ /* VEX_LEN_0FXOP_09_CB */
{
- { "rorxS", { Gdq, Edq, Ib }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) },
},
- /* VEX_LEN_0FXOP_08_CC */
+ /* VEX_LEN_0FXOP_09_D1 */
{
- { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) },
},
- /* VEX_LEN_0FXOP_08_CD */
+ /* VEX_LEN_0FXOP_09_D2 */
{
- { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) },
},
- /* VEX_LEN_0FXOP_08_CE */
+ /* VEX_LEN_0FXOP_09_D3 */
{
- { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) },
},
- /* VEX_LEN_0FXOP_08_CF */
+ /* VEX_LEN_0FXOP_09_D6 */
{
- { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) },
},
- /* VEX_LEN_0FXOP_08_EC */
+ /* VEX_LEN_0FXOP_09_D7 */
{
- { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) },
},
- /* VEX_LEN_0FXOP_08_ED */
+ /* VEX_LEN_0FXOP_09_DB */
{
- { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) },
},
- /* VEX_LEN_0FXOP_08_EE */
+ /* VEX_LEN_0FXOP_09_E1 */
{
- { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) },
},
- /* VEX_LEN_0FXOP_08_EF */
+ /* VEX_LEN_0FXOP_09_E2 */
{
- { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) },
},
- /* VEX_LEN_0FXOP_09_80 */
+ /* VEX_LEN_0FXOP_09_E3 */
{
- { "vfrczps", { XM, EXxmm }, 0 },
- { "vfrczps", { XM, EXymmq }, 0 },
+ { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) },
},
- /* VEX_LEN_0FXOP_09_81 */
+ /* VEX_LEN_0FXOP_0A_12 */
{
- { "vfrczpd", { XM, EXxmm }, 0 },
- { "vfrczpd", { XM, EXymmq }, 0 },
+ { REG_TABLE (REG_0FXOP_0A_12_L_0) },
},
};
{ MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
},
{
- /* VEX_W_0F380C_P_2 */
- { "vpermilps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F380C */
+ { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F380D_P_2 */
- { "vpermilpd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F380D */
+ { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F380E_P_2 */
- { "vtestps", { XM, EXx }, 0 },
+ /* VEX_W_0F380E */
+ { "vtestps", { XM, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F380F_P_2 */
- { "vtestpd", { XM, EXx }, 0 },
+ /* VEX_W_0F380F */
+ { "vtestpd", { XM, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F3816_P_2 */
- { "vpermps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3813 */
+ { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
},
{
- /* VEX_W_0F3818_P_2 */
- { "vbroadcastss", { XM, EXxmm_md }, 0 },
+ /* VEX_W_0F3816_L_1 */
+ { "vpermps", { XM, Vex, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F3819_P_2 */
- { "vbroadcastsd", { XM, EXxmm_mq }, 0 },
+ /* VEX_W_0F3818 */
+ { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA },
},
{
- /* VEX_W_0F381A_P_2_M_0 */
- { "vbroadcastf128", { XM, Mxmm }, 0 },
+ /* VEX_W_0F3819_L_1 */
+ { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA },
},
{
- /* VEX_W_0F382C_P_2_M_0 */
- { "vmaskmovps", { XM, Vex, Mx }, 0 },
+ /* VEX_W_0F381A_M_0_L_1 */
+ { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
},
{
- /* VEX_W_0F382D_P_2_M_0 */
- { "vmaskmovpd", { XM, Vex, Mx }, 0 },
+ /* VEX_W_0F382C_M_0 */
+ { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA },
},
{
- /* VEX_W_0F382E_P_2_M_0 */
- { "vmaskmovps", { Mx, Vex, XM }, 0 },
+ /* VEX_W_0F382D_M_0 */
+ { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA },
},
{
- /* VEX_W_0F382F_P_2_M_0 */
- { "vmaskmovpd", { Mx, Vex, XM }, 0 },
+ /* VEX_W_0F382E_M_0 */
+ { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA },
},
{
- /* VEX_W_0F3836_P_2 */
- { "vpermd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F382F_M_0 */
+ { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA },
},
{
- /* VEX_W_0F3846_P_2 */
- { "vpsravd", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F3836 */
+ { "vpermd", { XM, Vex, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F3858_P_2 */
- { "vpbroadcastd", { XM, EXxmm_md }, 0 },
+ /* VEX_W_0F3846 */
+ { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F3859_P_2 */
- { "vpbroadcastq", { XM, EXxmm_mq }, 0 },
+ /* VEX_W_0F3849_X86_64_P_0 */
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) },
},
{
- /* VEX_W_0F385A_P_2_M_0 */
- { "vbroadcasti128", { XM, Mxmm }, 0 },
+ /* VEX_W_0F3849_X86_64_P_2 */
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) },
},
{
- /* VEX_W_0F3878_P_2 */
- { "vpbroadcastb", { XM, EXxmm_mb }, 0 },
+ /* VEX_W_0F3849_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) },
},
{
- /* VEX_W_0F3879_P_2 */
- { "vpbroadcastw", { XM, EXxmm_mw }, 0 },
+ /* VEX_W_0F384B_X86_64_P_1 */
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) },
},
{
- /* VEX_W_0F38CF_P_2 */
- { "vgf2p8mulb", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F384B_X86_64_P_2 */
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) },
},
{
- /* VEX_W_0F3A00_P_2 */
- { Bad_Opcode },
- { "vpermq", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F384B_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) },
},
{
- /* VEX_W_0F3A01_P_2 */
- { Bad_Opcode },
- { "vpermpd", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F3850 */
+ { "%XV vpdpbusd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3851 */
+ { "%XV vpdpbusds", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3852 */
+ { "%XV vpdpwssd", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3853 */
+ { "%XV vpdpwssds", { XM, Vex, EXx }, 0 },
+ },
+ {
+ /* VEX_W_0F3858 */
+ { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA },
+ },
+ {
+ /* VEX_W_0F3859 */
+ { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA },
+ },
+ {
+ /* VEX_W_0F385A_M_0_L_0 */
+ { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
+ },
+ {
+ /* VEX_W_0F385C_X86_64_P_1 */
+ { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) },
+ },
+ {
+ /* VEX_W_0F385E_X86_64_P_0 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) },
+ },
+ {
+ /* VEX_W_0F385E_X86_64_P_1 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) },
+ },
+ {
+ /* VEX_W_0F385E_X86_64_P_2 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) },
+ },
+ {
+ /* VEX_W_0F385E_X86_64_P_3 */
+ { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) },
},
{
- /* VEX_W_0F3A02_P_2 */
- { "vpblendd", { XM, Vex, EXx, Ib }, 0 },
+ /* VEX_W_0F3878 */
+ { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A04_P_2 */
- { "vpermilps", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F3879 */
+ { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A05_P_2 */
- { "vpermilpd", { XM, EXx, Ib }, 0 },
+ /* VEX_W_0F38CF */
+ { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A06_P_2 */
- { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
+ /* VEX_W_0F3A00_L_1 */
+ { Bad_Opcode },
+ { "vpermq", { XM, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A18_P_2 */
- { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
+ /* VEX_W_0F3A01_L_1 */
+ { Bad_Opcode },
+ { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A19_P_2 */
- { "vextractf128", { EXxmm, XM, Ib }, 0 },
+ /* VEX_W_0F3A02 */
+ { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A30_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) },
+ /* VEX_W_0F3A04 */
+ { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A31_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) },
+ /* VEX_W_0F3A05 */
+ { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A32_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) },
+ /* VEX_W_0F3A06_L_1 */
+ { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A33_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) },
+ /* VEX_W_0F3A18_L_1 */
+ { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A38_P_2 */
- { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 },
+ /* VEX_W_0F3A19_L_1 */
+ { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A39_P_2 */
- { "vextracti128", { EXxmm, XM, Ib }, 0 },
+ /* VEX_W_0F3A1D */
+ { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A46_P_2 */
- { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
+ /* VEX_W_0F3A38_L_1 */
+ { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A48_P_2 */
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ /* VEX_W_0F3A39_L_1 */
+ { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A49_P_2 */
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
- { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 },
+ /* VEX_W_0F3A46_L_1 */
+ { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A4A_P_2 */
- { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 },
+ /* VEX_W_0F3A4A */
+ { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A4B_P_2 */
- { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ /* VEX_W_0F3A4B */
+ { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
},
{
- /* VEX_W_0F3A4C_P_2 */
- { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
+ /* VEX_W_0F3A4C */
+ { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
},
{
- /* VEX_W_0F3ACE_P_2 */
+ /* VEX_W_0F3ACE */
{ Bad_Opcode },
- { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 },
+ { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
},
{
- /* VEX_W_0F3ACF_P_2 */
+ /* VEX_W_0F3ACF */
{ Bad_Opcode },
- { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
+ { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
+ },
+ /* VEX_W_0FXOP_08_85_L_0 */
+ {
+ { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_86_L_0 */
+ {
+ { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_87_L_0 */
+ {
+ { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_8E_L_0 */
+ {
+ { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_8F_L_0 */
+ {
+ { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_95_L_0 */
+ {
+ { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_96_L_0 */
+ {
+ { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_97_L_0 */
+ {
+ { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_9E_L_0 */
+ {
+ { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_9F_L_0 */
+ {
+ { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_A6_L_0 */
+ {
+ { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_B6_L_0 */
+ {
+ { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 },
+ },
+ /* VEX_W_0FXOP_08_C0_L_0 */
+ {
+ { "vprotb", { XM, EXx, Ib }, 0 },
+ },
+ /* VEX_W_0FXOP_08_C1_L_0 */
+ {
+ { "vprotw", { XM, EXx, Ib }, 0 },
+ },
+ /* VEX_W_0FXOP_08_C2_L_0 */
+ {
+ { "vprotd", { XM, EXx, Ib }, 0 },
+ },
+ /* VEX_W_0FXOP_08_C3_L_0 */
+ {
+ { "vprotq", { XM, EXx, Ib }, 0 },
+ },
+ /* VEX_W_0FXOP_08_CC_L_0 */
+ {
+ { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_CD_L_0 */
+ {
+ { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_CE_L_0 */
+ {
+ { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_CF_L_0 */
+ {
+ { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_EC_L_0 */
+ {
+ { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_ED_L_0 */
+ {
+ { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_EE_L_0 */
+ {
+ { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_08_EF_L_0 */
+ {
+ { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 },
+ },
+ /* VEX_W_0FXOP_09_80 */
+ {
+ { "vfrczps", { XM, EXx }, 0 },
+ },
+ /* VEX_W_0FXOP_09_81 */
+ {
+ { "vfrczpd", { XM, EXx }, 0 },
+ },
+ /* VEX_W_0FXOP_09_82 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) },
+ },
+ /* VEX_W_0FXOP_09_83 */
+ {
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) },
+ },
+ /* VEX_W_0FXOP_09_C1_L_0 */
+ {
+ { "vphaddbw", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_C2_L_0 */
+ {
+ { "vphaddbd", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_C3_L_0 */
+ {
+ { "vphaddbq", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_C6_L_0 */
+ {
+ { "vphaddwd", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_C7_L_0 */
+ {
+ { "vphaddwq", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_CB_L_0 */
+ {
+ { "vphadddq", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_D1_L_0 */
+ {
+ { "vphaddubw", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_D2_L_0 */
+ {
+ { "vphaddubd", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_D3_L_0 */
+ {
+ { "vphaddubq", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_D6_L_0 */
+ {
+ { "vphadduwd", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_D7_L_0 */
+ {
+ { "vphadduwq", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_DB_L_0 */
+ {
+ { "vphaddudq", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_E1_L_0 */
+ {
+ { "vphsubbw", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_E2_L_0 */
+ {
+ { "vphsubwd", { XM, EXxmm }, 0 },
+ },
+ /* VEX_W_0FXOP_09_E3_L_0 */
+ {
+ { "vphsubdq", { XM, EXxmm }, 0 },
},
#include "i386-dis-evex-w.h"
},
{
/* MOD_FF_REG_3 */
- { "Jcall^", { indirEp }, 0 },
+ { "{l|}call^", { indirEp }, 0 },
},
{
/* MOD_FF_REG_5 */
- { "Jjmp^", { indirEp }, 0 },
+ { "{l|}jmp^", { indirEp }, 0 },
},
{
/* MOD_0F01_REG_0 */
},
{
/* MOD_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
- { RM_TABLE (RM_0F01_REG_5) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
+ { RM_TABLE (RM_0F01_REG_5_MOD_3) },
},
{
/* MOD_0F01_REG_7 */
{ "invlpg", { Mb }, 0 },
- { RM_TABLE (RM_0F01_REG_7) },
+ { RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
/* MOD_0F12_PREFIX_0 */
- { "movlps", { XM, EXq }, PREFIX_OPCODE },
- { "movhlps", { XM, EXq }, PREFIX_OPCODE },
+ { "movlpX", { XM, EXq }, 0 },
+ { "movhlps", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F12_PREFIX_2 */
+ { "movlpX", { XM, EXq }, 0 },
},
{
/* MOD_0F13 */
},
{
/* MOD_0F16_PREFIX_0 */
- { "movhps", { XM, EXq }, 0 },
+ { "movhpX", { XM, EXq }, 0 },
{ "movlhps", { XM, EXq }, 0 },
},
+ {
+ /* MOD_0F16_PREFIX_2 */
+ { "movhpX", { XM, EXq }, 0 },
+ },
{
/* MOD_0F17 */
{ "movhpX", { EXq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F1C_PREFIX_0 */
- { REG_TABLE (REG_0F1C_MOD_0) },
+ { REG_TABLE (REG_0F1C_P_0_MOD_0) },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1E_PREFIX_1 */
{ "nopQ", { Ev }, 0 },
- { REG_TABLE (REG_0F1E_MOD_3) },
- },
- {
- /* MOD_0F24 */
- { Bad_Opcode },
- { "movL", { Rd, Td }, 0 },
- },
- {
- /* MOD_0F26 */
- { Bad_Opcode },
- { "movL", { Td, Rd }, 0 },
+ { REG_TABLE (REG_0F1E_P_1_MOD_3) },
},
{
/* MOD_0F2B_PREFIX_0 */
{"movntsd", { Mq, XM }, PREFIX_OPCODE },
},
{
- /* MOD_0F51 */
+ /* MOD_0F50 */
{ Bad_Opcode },
{ "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
/* MOD_0F71_REG_2 */
{ Bad_Opcode },
- { "psrlw", { MS, Ib }, 0 },
+ { "psrlw", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F71_REG_4 */
{ Bad_Opcode },
- { "psraw", { MS, Ib }, 0 },
+ { "psraw", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F71_REG_6 */
{ Bad_Opcode },
- { "psllw", { MS, Ib }, 0 },
+ { "psllw", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F72_REG_2 */
{ Bad_Opcode },
- { "psrld", { MS, Ib }, 0 },
+ { "psrld", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F72_REG_4 */
{ Bad_Opcode },
- { "psrad", { MS, Ib }, 0 },
+ { "psrad", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F72_REG_6 */
{ Bad_Opcode },
- { "pslld", { MS, Ib }, 0 },
+ { "pslld", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F73_REG_2 */
{ Bad_Opcode },
- { "psrlq", { MS, Ib }, 0 },
+ { "psrlq", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F73_REG_3 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F73_REG_3) },
+ { "psrldq", { XS, Ib }, PREFIX_DATA },
},
{
/* MOD_0F73_REG_6 */
{ Bad_Opcode },
- { "psllq", { MS, Ib }, 0 },
+ { "psllq", { MS, Ib }, PREFIX_OPCODE },
},
{
/* MOD_0F73_REG_7 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_0F73_REG_7) },
+ { "pslldq", { XS, Ib }, PREFIX_DATA },
},
{
/* MOD_0FAE_REG_0 */
{ "fxsave", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
},
{
/* MOD_0FAE_REG_1 */
{ "fxrstor", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
},
{
/* MOD_0FAE_REG_2 */
{ "ldmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
},
{
/* MOD_0FAE_REG_3 */
{ "stmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
},
{
/* MOD_0FAE_REG_4 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
},
{
/* MOD_0FAE_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
+ { "xrstor", { FXSAVE }, PREFIX_OPCODE },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
},
{
/* MOD_0FAE_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
},
{
/* MOD_0FAE_REG_7 */
- { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
- { RM_TABLE (RM_0FAE_REG_7) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
+ { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
},
{
/* MOD_0FB2 */
},
{
/* MOD_0FC3 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
+ { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
},
{
/* MOD_0FC7_REG_3 */
},
{
/* MOD_0FC7_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
},
{
/* MOD_0FC7_REG_7 */
{ "vmptrst", { Mq }, 0 },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
+ { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
},
{
/* MOD_0FD7 */
{ "lddqu", { XM, M }, 0 },
},
{
- /* MOD_0F382A_PREFIX_2 */
- { "movntdqa", { XM, Mx }, 0 },
+ /* MOD_0F382A */
+ { "movntdqa", { XM, Mx }, PREFIX_DATA },
+ },
+ {
+ /* MOD_0F38DC_PREFIX_1 */
+ { "aesenc128kl", { XM, M }, 0 },
+ { "loadiwkey", { XM, EXx }, 0 },
},
{
- /* MOD_0F38F5_PREFIX_2 */
- { "wrussK", { M, Gdq }, PREFIX_OPCODE },
+ /* MOD_0F38DD_PREFIX_1 */
+ { "aesdec128kl", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F38DE_PREFIX_1 */
+ { "aesenc256kl", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F38DF_PREFIX_1 */
+ { "aesdec256kl", { XM, M }, 0 },
+ },
+ {
+ /* MOD_0F38F5 */
+ { "wrussK", { M, Gdq }, PREFIX_DATA },
},
{
/* MOD_0F38F6_PREFIX_0 */
{ "enqcmd", { Gva, M }, PREFIX_OPCODE },
},
{
- /* MOD_0F38F9_PREFIX_0 */
- { "movdiri", { Em, Gv }, PREFIX_OPCODE },
+ /* MOD_0F38F9 */
+ { "movdiri", { Edq, Gdq }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38FA_PREFIX_1 */
+ { Bad_Opcode },
+ { "encodekey128", { Gd, Ed }, 0 },
+ },
+ {
+ /* MOD_0F38FB_PREFIX_1 */
+ { Bad_Opcode },
+ { "encodekey256", { Gd, Ed }, 0 },
+ },
+ {
+ /* MOD_0F3A0F_PREFIX_1 */
+ { Bad_Opcode },
+ { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) },
},
{
/* MOD_62_32BIT */
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
},
+ {
+ /* MOD_VEX_0F12_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
+ },
{
/* MOD_VEX_0F13 */
{ VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
},
+ {
+ /* MOD_VEX_0F16_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
+ },
{
/* MOD_VEX_0F17 */
{ VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
},
{
/* MOD_VEX_0F2B */
- { "vmovntpX", { Mx, XM }, 0 },
+ { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
},
{
/* MOD_VEX_W_0_0F41_P_0_LEN_1 */
{ Bad_Opcode },
- { "kandw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F41_P_0_LEN_1 */
{ Bad_Opcode },
- { "kandq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F41_P_2_LEN_1 */
{ Bad_Opcode },
- { "kandb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandb", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F41_P_2_LEN_1 */
{ Bad_Opcode },
- { "kandd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandd", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F42_P_0_LEN_1 */
{ Bad_Opcode },
- { "kandnw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandnw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F42_P_0_LEN_1 */
{ Bad_Opcode },
- { "kandnq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandnq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F42_P_2_LEN_1 */
{ Bad_Opcode },
- { "kandnb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandnb", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F42_P_2_LEN_1 */
{ Bad_Opcode },
- { "kandnd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kandnd", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F44_P_0_LEN_0 */
{ Bad_Opcode },
- { "knotw", { MaskG, MaskR }, 0 },
+ { "knotw", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F44_P_0_LEN_0 */
{ Bad_Opcode },
- { "knotq", { MaskG, MaskR }, 0 },
+ { "knotq", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F44_P_2_LEN_0 */
{ Bad_Opcode },
- { "knotb", { MaskG, MaskR }, 0 },
+ { "knotb", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F44_P_2_LEN_0 */
{ Bad_Opcode },
- { "knotd", { MaskG, MaskR }, 0 },
+ { "knotd", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F45_P_0_LEN_1 */
{ Bad_Opcode },
- { "korw", { MaskG, MaskVex, MaskR }, 0 },
+ { "korw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F45_P_0_LEN_1 */
{ Bad_Opcode },
- { "korq", { MaskG, MaskVex, MaskR }, 0 },
+ { "korq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F45_P_2_LEN_1 */
{ Bad_Opcode },
- { "korb", { MaskG, MaskVex, MaskR }, 0 },
+ { "korb", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F45_P_2_LEN_1 */
{ Bad_Opcode },
- { "kord", { MaskG, MaskVex, MaskR }, 0 },
+ { "kord", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F46_P_0_LEN_1 */
{ Bad_Opcode },
- { "kxnorw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnorw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F46_P_0_LEN_1 */
{ Bad_Opcode },
- { "kxnorq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnorq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F46_P_2_LEN_1 */
{ Bad_Opcode },
- { "kxnorb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnorb", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F46_P_2_LEN_1 */
{ Bad_Opcode },
- { "kxnord", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxnord", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F47_P_0_LEN_1 */
{ Bad_Opcode },
- { "kxorw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxorw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F47_P_0_LEN_1 */
{ Bad_Opcode },
- { "kxorq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxorq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F47_P_2_LEN_1 */
{ Bad_Opcode },
- { "kxorb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxorb", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F47_P_2_LEN_1 */
{ Bad_Opcode },
- { "kxord", { MaskG, MaskVex, MaskR }, 0 },
+ { "kxord", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F4A_P_0_LEN_1 */
{ Bad_Opcode },
- { "kaddw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kaddw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F4A_P_0_LEN_1 */
{ Bad_Opcode },
- { "kaddq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kaddq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F4A_P_2_LEN_1 */
{ Bad_Opcode },
- { "kaddb", { MaskG, MaskVex, MaskR }, 0 },
+ { "kaddb", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F4A_P_2_LEN_1 */
{ Bad_Opcode },
- { "kaddd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kaddd", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F4B_P_0_LEN_1 */
{ Bad_Opcode },
- { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 },
+ { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F4B_P_0_LEN_1 */
{ Bad_Opcode },
- { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 },
+ { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F4B_P_2_LEN_1 */
{ Bad_Opcode },
- { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 },
+ { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 },
},
{
/* MOD_VEX_0F50 */
{ Bad_Opcode },
- { "vmovmskpX", { Gdq, XS }, 0 },
+ { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
/* MOD_VEX_0F71_REG_2 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) },
+ { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F71_REG_4 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) },
+ { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F71_REG_6 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) },
+ { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F72_REG_2 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) },
+ { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F72_REG_4 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) },
+ { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F72_REG_6 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) },
+ { "vpslld", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F73_REG_2 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) },
+ { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F73_REG_3 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) },
+ { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F73_REG_6 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) },
+ { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_0F73_REG_7 */
{ Bad_Opcode },
- { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) },
+ { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA },
},
{
/* MOD_VEX_W_0_0F91_P_0_LEN_0 */
{
/* MOD_VEX_W_0_0F92_P_0_LEN_0 */
{ Bad_Opcode },
- { "kmovw", { MaskG, Rdq }, 0 },
+ { "kmovw", { MaskG, Edq }, 0 },
},
{
/* MOD_VEX_W_0_0F92_P_2_LEN_0 */
{ Bad_Opcode },
- { "kmovb", { MaskG, Rdq }, 0 },
+ { "kmovb", { MaskG, Edq }, 0 },
},
{
/* MOD_VEX_0F92_P_3_LEN_0 */
{ Bad_Opcode },
- { "kmovK", { MaskG, Rdq }, 0 },
+ { "kmovK", { MaskG, Edq }, 0 },
},
{
/* MOD_VEX_W_0_0F93_P_0_LEN_0 */
{ Bad_Opcode },
- { "kmovw", { Gdq, MaskR }, 0 },
+ { "kmovw", { Gdq, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F93_P_2_LEN_0 */
{ Bad_Opcode },
- { "kmovb", { Gdq, MaskR }, 0 },
+ { "kmovb", { Gdq, MaskE }, 0 },
},
{
/* MOD_VEX_0F93_P_3_LEN_0 */
{ Bad_Opcode },
- { "kmovK", { Gdq, MaskR }, 0 },
+ { "kmovK", { Gdq, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F98_P_0_LEN_0 */
{ Bad_Opcode },
- { "kortestw", { MaskG, MaskR }, 0 },
+ { "kortestw", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F98_P_0_LEN_0 */
{ Bad_Opcode },
- { "kortestq", { MaskG, MaskR }, 0 },
+ { "kortestq", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F98_P_2_LEN_0 */
{ Bad_Opcode },
- { "kortestb", { MaskG, MaskR }, 0 },
+ { "kortestb", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F98_P_2_LEN_0 */
{ Bad_Opcode },
- { "kortestd", { MaskG, MaskR }, 0 },
+ { "kortestd", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F99_P_0_LEN_0 */
{ Bad_Opcode },
- { "ktestw", { MaskG, MaskR }, 0 },
+ { "ktestw", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F99_P_0_LEN_0 */
{ Bad_Opcode },
- { "ktestq", { MaskG, MaskR }, 0 },
+ { "ktestq", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_0_0F99_P_2_LEN_0 */
{ Bad_Opcode },
- { "ktestb", { MaskG, MaskR }, 0 },
+ { "ktestb", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_W_1_0F99_P_2_LEN_0 */
{ Bad_Opcode },
- { "ktestd", { MaskG, MaskR }, 0 },
+ { "ktestd", { MaskG, MaskE }, 0 },
},
{
/* MOD_VEX_0FAE_REG_2 */
{ VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) },
},
{
- /* MOD_VEX_0FD7_PREFIX_2 */
+ /* MOD_VEX_0FD7 */
{ Bad_Opcode },
- { "vpmovmskb", { Gdq, XS }, 0 },
+ { "vpmovmskb", { Gdq, XS }, PREFIX_DATA },
},
{
- /* MOD_VEX_0FE7_PREFIX_2 */
- { "vmovntdq", { Mx, XM }, 0 },
+ /* MOD_VEX_0FE7 */
+ { "vmovntdq", { Mx, XM }, PREFIX_DATA },
},
{
/* MOD_VEX_0FF0_PREFIX_3 */
{ "vlddqu", { XM, M }, 0 },
},
{
- /* MOD_VEX_0F381A_PREFIX_2 */
- { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) },
+ /* MOD_VEX_0F381A */
+ { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382A */
+ { "vmovntdqa", { XM, Mx }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F382C */
+ { VEX_W_TABLE (VEX_W_0F382C_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382D */
+ { VEX_W_TABLE (VEX_W_0F382D_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382E */
+ { VEX_W_TABLE (VEX_W_0F382E_M_0) },
+ },
+ {
+ /* MOD_VEX_0F382F */
+ { VEX_W_TABLE (VEX_W_0F382F_M_0) },
+ },
+ {
+ /* MOD_VEX_0F3849_X86_64_P_0_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) },
+ { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) },
},
{
- /* MOD_VEX_0F382A_PREFIX_2 */
- { "vmovntdqa", { XM, Mx }, 0 },
+ /* MOD_VEX_0F3849_X86_64_P_2_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) },
},
{
- /* MOD_VEX_0F382C_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) },
+ /* MOD_VEX_0F3849_X86_64_P_3_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) },
},
{
- /* MOD_VEX_0F382D_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) },
+ /* MOD_VEX_0F384B_X86_64_P_1_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) },
},
{
- /* MOD_VEX_0F382E_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) },
+ /* MOD_VEX_0F384B_X86_64_P_2_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) },
},
{
- /* MOD_VEX_0F382F_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) },
+ /* MOD_VEX_0F384B_X86_64_P_3_W_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) },
},
{
- /* MOD_VEX_0F385A_PREFIX_2 */
- { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) },
+ /* MOD_VEX_0F385A */
+ { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) },
},
{
- /* MOD_VEX_0F388C_PREFIX_2 */
- { "vpmaskmov%LW", { XM, Vex, Mx }, 0 },
+ /* MOD_VEX_0F385C_X86_64_P_1_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) },
},
{
- /* MOD_VEX_0F388E_PREFIX_2 */
- { "vpmaskmov%LW", { Mx, Vex, XM }, 0 },
+ /* MOD_VEX_0F385E_X86_64_P_0_W_0 */
+ { Bad_Opcode },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) },
},
{
- /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */
+ /* MOD_VEX_0F385E_X86_64_P_1_W_0 */
{ Bad_Opcode },
- { "kshiftrb", { MaskG, MaskR, Ib }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) },
},
{
- /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */
+ /* MOD_VEX_0F385E_X86_64_P_2_W_0 */
{ Bad_Opcode },
- { "kshiftrw", { MaskG, MaskR, Ib }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) },
},
{
- /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */
+ /* MOD_VEX_0F385E_X86_64_P_3_W_0 */
{ Bad_Opcode },
- { "kshiftrd", { MaskG, MaskR, Ib }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) },
+ },
+ {
+ /* MOD_VEX_0F388C */
+ { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA },
},
{
- /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */
+ /* MOD_VEX_0F388E */
+ { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA },
+ },
+ {
+ /* MOD_VEX_0F3A30_L_0 */
{ Bad_Opcode },
- { "kshiftrq", { MaskG, MaskR, Ib }, 0 },
+ { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
},
{
- /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */
+ /* MOD_VEX_0F3A31_L_0 */
{ Bad_Opcode },
- { "kshiftlb", { MaskG, MaskR, Ib }, 0 },
+ { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
},
{
- /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */
+ /* MOD_VEX_0F3A32_L_0 */
{ Bad_Opcode },
- { "kshiftlw", { MaskG, MaskR, Ib }, 0 },
+ { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA },
},
{
- /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */
+ /* MOD_VEX_0F3A33_L_0 */
{ Bad_Opcode },
- { "kshiftld", { MaskG, MaskR, Ib }, 0 },
+ { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA },
},
{
- /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */
+ /* MOD_VEX_0FXOP_09_12 */
{ Bad_Opcode },
- { "kshiftlq", { MaskG, MaskR, Ib }, 0 },
+ { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) },
},
#include "i386-dis-evex-mod.h"
},
{
/* RM_C7_REG_7 */
- { "xbeginT", { Skip_MODRM, Jv }, 0 },
+ { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
},
{
/* RM_0F01_REG_0 */
{ "mwait", { { OP_Mwait, 0 } }, 0 },
{ "clac", { Skip_MODRM }, 0 },
{ "stac", { Skip_MODRM }, 0 },
- { Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { "encls", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
},
{
/* RM_0F01_REG_2 */
{
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM }, 0 },
- { "vmmcall", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
{ "vmload", { Skip_MODRM }, 0 },
{ "vmsave", { Skip_MODRM }, 0 },
{ "stgi", { Skip_MODRM }, 0 },
{ "invlpga", { Skip_MODRM }, 0 },
},
{
- /* RM_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
+ /* RM_0F01_REG_5_MOD_3 */
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
{ Bad_Opcode },
- { Bad_Opcode },
- { Bad_Opcode },
- { "rdpkru", { Skip_MODRM }, 0 },
- { "wrpkru", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
},
{
- /* RM_0F01_REG_7 */
+ /* RM_0F01_REG_7_MOD_3 */
{ "swapgs", { Skip_MODRM }, 0 },
{ "rdtscp", { Skip_MODRM }, 0 },
- { "monitorx", { { OP_Monitor, 0 } }, 0 },
- { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
+ { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
{ "clzero", { Skip_MODRM }, 0 },
+ { "rdpru", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
},
{
- /* RM_0F1E_MOD_3_REG_7 */
+ /* RM_0F1E_P_1_MOD_3_REG_7 */
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
},
{
- /* RM_0FAE_REG_6 */
+ /* RM_0F3A0F_P_1_MOD_3_REG_0 */
+ { "hreset", { Skip_MODRM, Ib }, 0 },
+ },
+ {
+ /* RM_0FAE_REG_6_MOD_3 */
{ "mfence", { Skip_MODRM }, 0 },
},
{
- /* RM_0FAE_REG_7 */
+ /* RM_0FAE_REG_7_MOD_3 */
{ "sfence", { Skip_MODRM }, 0 },
},
+ {
+ /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */
+ { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) },
+ },
};
#define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
#define BND_PREFIX (0xf2 | 0x400)
#define NOTRACK_PREFIX (0x3e | 0x100)
+/* Remember if the current op is a jump instruction. */
+static bfd_boolean op_is_jump = FALSE;
+
static int
ckprefix (void)
{
int newrex, i, length;
rex = 0;
- rex_ignored = 0;
prefixes = 0;
used_prefixes = 0;
rex_used = 0;
case 0x2e:
prefixes |= PREFIX_CS;
last_seg_prefix = i;
- active_seg_prefix = PREFIX_CS;
+
+ if (address_mode != mode_64bit)
+ active_seg_prefix = PREFIX_CS;
+
break;
case 0x36:
prefixes |= PREFIX_SS;
last_seg_prefix = i;
- active_seg_prefix = PREFIX_SS;
+
+ if (address_mode != mode_64bit)
+ active_seg_prefix = PREFIX_SS;
+
break;
case 0x3e:
prefixes |= PREFIX_DS;
last_seg_prefix = i;
- active_seg_prefix = PREFIX_DS;
+
+ if (address_mode != mode_64bit)
+ active_seg_prefix = PREFIX_DS;
+
break;
case 0x26:
prefixes |= PREFIX_ES;
last_seg_prefix = i;
- active_seg_prefix = PREFIX_ES;
+
+ if (address_mode != mode_64bit)
+ active_seg_prefix = PREFIX_ES;
+
break;
case 0x64:
prefixes |= PREFIX_FS;
enum x86_64_isa
{
- amd64 = 0,
+ amd64 = 1,
intel64
};
case USE_XOP_8F_TABLE:
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
/* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
break;
}
need_vex = 1;
- need_vex_reg = 1;
codep++;
vindex = *codep++;
dp = &xop_table[vex_table_index][vindex];
modrm.mod = (*codep >> 6) & 3;
modrm.reg = (*codep >> 3) & 7;
modrm.rm = *codep & 7;
+
+ /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
+ having to decode the bits for every otherwise valid encoding. */
+ if (vex.prefix)
+ return &bad_opcode;
break;
case USE_VEX_C4_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
switch ((*codep & 0x1f))
{
break;
}
need_vex = 1;
- need_vex_reg = 1;
codep++;
vindex = *codep++;
dp = &vex_table[vex_table_index][vindex];
case USE_VEX_C5_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 2);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = (*codep & 0x80) ? 0 : REX_R;
/* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
break;
}
need_vex = 1;
- need_vex_reg = 1;
codep++;
vindex = *codep++;
dp = &vex_table[dp->op[1].bytemode][vindex];
/* EVEX prefix. */
vex.evex = 1;
FETCH_DATA (info, codep + 4);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
/* The first byte after 0x62. */
rex = ~(*codep >> 5) & 0x7;
vex.r = *codep & 0x10;
}
need_vex = 1;
- need_vex_reg = 1;
codep++;
vindex = *codep++;
dp = &evex_table[vex_table_index][vindex];
else if (CONST_STRNEQ (p, "x86-64"))
{
address_mode = mode_64bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
else if (CONST_STRNEQ (p, "i386"))
{
address_mode = mode_32bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
else if (CONST_STRNEQ (p, "i8086"))
{
address_mode = mode_16bit;
- priv.orig_sizeflag = 0;
+ priv.orig_sizeflag &= ~(AFLAG | DFLAG);
}
else if (CONST_STRNEQ (p, "intel"))
{
names_xmm = intel_names_xmm;
names_ymm = intel_names_ymm;
names_zmm = intel_names_zmm;
+ names_tmm = intel_names_tmm;
index64 = intel_index64;
index32 = intel_index32;
names_mask = intel_names_mask;
names_xmm = att_names_xmm;
names_ymm = att_names_ymm;
names_zmm = att_names_zmm;
+ names_tmm = att_names_tmm;
index64 = att_index64;
index32 = att_index32;
names_mask = att_names_mask;
FETCH_DATA (info, codep + 1);
threebyte = *codep;
dp = &dis386_twobyte[threebyte];
- need_modrm = twobyte_has_modrm[*codep];
+ need_modrm = twobyte_has_modrm[threebyte];
codep++;
}
else
modrm.reg = (*codep >> 3) & 7;
modrm.rm = *codep & 7;
}
+ else
+ memset (&modrm, 0, sizeof (modrm));
need_vex = 0;
- need_vex_reg = 0;
- vex_w_done = 0;
memset (&vex, 0, sizeof (vex));
if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
}
}
+ /* Clear instruction information. */
+ if (the_info)
+ {
+ the_info->insn_info_valid = 0;
+ the_info->branch_delay_insns = 0;
+ the_info->data_size = 0;
+ the_info->insn_type = dis_noninsn;
+ the_info->target = 0;
+ the_info->target2 = 0;
+ }
+
+ /* Reset jump operation indicator. */
+ op_is_jump = FALSE;
+
+ {
+ int jump_detection = 0;
+
+ /* Extract flags. */
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ if ((dp->op[i].rtn == OP_J)
+ || (dp->op[i].rtn == OP_indirE))
+ jump_detection |= 1;
+ else if ((dp->op[i].rtn == BND_Fixup)
+ || (!dp->op[i].rtn && !dp->op[i].bytemode))
+ jump_detection |= 2;
+ else if ((dp->op[i].bytemode == cond_jump_mode)
+ || (dp->op[i].bytemode == loop_jcxz_mode))
+ jump_detection |= 4;
+ }
+
+ /* Determine if this is a jump or branch. */
+ if ((jump_detection & 0x3) == 0x3)
+ {
+ op_is_jump = TRUE;
+ if (jump_detection & 0x4)
+ the_info->insn_type = dis_condbranch;
+ else
+ the_info->insn_type =
+ (dp->name && !strncmp(dp->name, "call", 4))
+ ? dis_jsr : dis_branch;
+ }
+ }
+
/* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
are all 0s in inverted form. */
if (need_vex && vex.register_specifier != 0)
return end_codep - priv.the_buffer;
}
+ switch (dp->prefix_requirement)
+ {
+ case PREFIX_DATA:
+ /* If only the data prefix is marked as mandatory, its absence renders
+ the encoding invalid. Most other PREFIX_OPCODE rules still apply. */
+ if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA))
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+ used_prefixes |= PREFIX_DATA;
+ /* Fall through. */
+ case PREFIX_OPCODE:
+ /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
+ unused, opcode is invalid. Since the PREFIX_DATA prefix may be
+ used by putop and MMX/SSE operand and may be overridden by the
+ PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
+ separately. */
+ if (((need_vex
+ ? vex.prefix == REPE_PREFIX_OPCODE
+ || vex.prefix == REPNE_PREFIX_OPCODE
+ : (prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
+ && (used_prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
+ || (((need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : ((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+ == PREFIX_DATA))
+ && (used_prefixes & PREFIX_DATA) == 0))
+ || (vex.evex && dp->prefix_requirement != PREFIX_DATA
+ && !vex.w != !(used_prefixes & PREFIX_DATA)))
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+ break;
+ }
+
/* Check if the REX prefix is used. */
- if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
+ if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
all_prefixes[last_rex_prefix] = 0;
/* Check if the SEG prefix is used. */
/* Check if the DATA prefix is used. */
if ((prefixes & PREFIX_DATA) != 0
- && (used_prefixes & PREFIX_DATA) != 0)
+ && (used_prefixes & PREFIX_DATA) != 0
+ && !need_vex)
all_prefixes[last_data_prefix] = 0;
/* Print the extra prefixes. */
(*info->fprintf_func) (info->stream, "%s ", name);
}
- /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
- unused, opcode is invalid. Since the PREFIX_DATA prefix may be
- used by putop and MMX/SSE operand and may be overriden by the
- PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
- separately. */
- if (dp->prefix_requirement == PREFIX_OPCODE
- && dp != &bad_opcode
- && (((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
- && (used_prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
- || ((((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
- == PREFIX_DATA)
- && (used_prefixes & PREFIX_DATA) == 0))))
- {
- (*info->fprintf_func) (info->stream, "(bad)");
- return end_codep - priv.the_buffer;
- }
-
/* Check maximum code length. */
if ((codep - start_codep) > MAX_CODE_LENGTH)
{
if (needcomma)
(*info->fprintf_func) (info->stream, ",");
if (op_index[i] != -1 && !op_riprel[i])
- (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
+ {
+ bfd_vma target = (bfd_vma) op_address[op_index[i]];
+
+ if (the_info && op_is_jump)
+ {
+ the_info->insn_info_valid = 1;
+ the_info->branch_delay_insns = 0;
+ the_info->data_size = 0;
+ the_info->target = target;
+ the_info->target2 = 0;
+ }
+ (*info->print_address_func) (target, info);
+ }
else
(*info->fprintf_func) (info->stream, "%s", op_txt[i]);
needcomma = 1;
"(bad)",
"fst{s|}",
"fstp{s|}",
- "fldenvIC",
+ "fldenv{C|C}",
"fldcw",
- "fNstenvIC",
+ "fNstenv{C|C}",
"fNstcw",
/* da */
"fiadd{l|}",
"fist{l|}",
"fistp{l|}",
"(bad)",
- "fld{t||t|}",
+ "fld{t|}",
"(bad)",
- "fstp{t||t|}",
+ "fstp{t|}",
/* dc */
"fadd{l|}",
"fmul{l|}",
"fisttp{ll|}",
"fst{l||}",
"fstp{l|}",
- "frstorIC",
+ "frstor{C|C}",
"(bad)",
- "fNsaveIC",
+ "fNsave{C|C}",
"fNstsw",
/* de */
"fiadd{s|}",
const char *p;
int alt = 0;
int cond = 1;
- unsigned int l = 0, len = 1;
+ unsigned int l = 0, len = 0;
char last[4];
-#define SAVE_LAST(c) \
- if (l < len && l < sizeof (last)) \
- last[l++] = c; \
- else \
- abort ();
-
for (p = in_template; *p; p++)
{
+ if (len > l)
+ {
+ if (l >= sizeof (last) || !ISUPPER (*p))
+ abort ();
+ last[l++] = *p;
+ continue;
+ }
switch (*p)
{
default:
while (*++p != '|')
if (*p == '}' || *p == '\0')
abort ();
+ alt = 1;
}
- /* Fall through. */
- case 'I':
- alt = 1;
- continue;
+ break;
case '|':
while (*++p != '}')
{
}
break;
case '}':
+ alt = 0;
break;
case 'A':
if (intel_syntax)
break;
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ if ((need_modrm && modrm.mod != 3)
+ || (sizeflag & SUFFIX_ALWAYS))
*obufp++ = 'b';
break;
case 'B':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_B:
+ case_B:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'b';
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if (address_mode == mode_64bit
&& !(prefixes & PREFIX_ADDR))
{
goto case_B;
}
+ else
+ abort ();
break;
case 'C':
if (intel_syntax && !alt)
used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS);
*obufp++ = ',';
*obufp++ = 'p';
+
+ /* Set active_seg_prefix even if not set in 64-bit mode
+ because here it is a valid branch hint. */
if (prefixes & PREFIX_DS)
- *obufp++ = 't';
+ {
+ active_seg_prefix = PREFIX_DS;
+ *obufp++ = 't';
+ }
else
- *obufp++ = 'n';
+ {
+ active_seg_prefix = PREFIX_CS;
+ *obufp++ = 'n';
+ }
}
break;
- case 'J':
- if (intel_syntax)
- break;
- *obufp++ = 'l';
- break;
case 'K':
USED_REX (REX_W);
if (rex & REX_W)
else
*obufp++ = 'd';
break;
- case 'Z':
- if (l != 0 || len != 1)
- {
- if (l != 1 || len != 2 || last[0] != 'X')
- {
- SAVE_LAST (*p);
- break;
- }
- if (!need_vex || !vex.evex)
- abort ();
- if (intel_syntax
- || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
- break;
- switch (vex.length)
- {
- case 128:
- *obufp++ = 'x';
- break;
- case 256:
- *obufp++ = 'y';
- break;
- case 512:
- *obufp++ = 'z';
- break;
- default:
- abort ();
- }
- break;
- }
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS))
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- goto case_L;
case 'L':
- if (l != 0 || len != 1)
- {
- SAVE_LAST (*p);
- break;
- }
-case_L:
- if (intel_syntax)
- break;
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'l';
- break;
+ abort ();
case 'M':
if (intel_mnemonic != cond)
*obufp++ = 'r';
if (!(rex & REX_W))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
- case '&':
- if (!intel_syntax
- && address_mode == mode_64bit
- && isa64 == intel64)
- {
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- case 'T':
- if (!intel_syntax
- && address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
+ case '@':
+ if (address_mode == mode_64bit
+ && (isa64 == intel64 || (rex & REX_W)
+ || !(prefixes & PREFIX_DATA)))
{
- *obufp++ = 'q';
+ if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'q';
break;
}
/* Fall through. */
- goto case_P;
case 'P':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_P:
- if (intel_syntax)
- {
- if ((rex & REX_W) == 0
- && (prefixes & PREFIX_DATA))
- {
- if ((sizeflag & DFLAG) == 0)
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- }
- if ((prefixes & PREFIX_DATA)
- || (rex & REX_W)
- || (sizeflag & SUFFIX_ALWAYS))
+ if ((modrm.mod == 3 || !cond)
+ && !(sizeflag & SUFFIX_ALWAYS))
+ break;
+ /* Fall through. */
+ case 'T':
+ if ((!(rex & REX_W) && (prefixes & PREFIX_DATA))
+ || ((sizeflag & SUFFIX_ALWAYS)
+ && address_mode != mode_64bit))
{
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *obufp++ = 'l';
- else
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ *obufp++ = (sizeflag & DFLAG) ?
+ intel_syntax ? 'd' : 'l' : 'w';
+ used_prefixes |= (prefixes & PREFIX_DATA);
}
+ else if (sizeflag & SUFFIX_ALWAYS)
+ *obufp++ = 'q';
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1 || len != 2 || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if ((prefixes & PREFIX_DATA)
|| (rex & REX_W)
|| (sizeflag & SUFFIX_ALWAYS))
}
}
}
+ else
+ abort ();
break;
- case 'U':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
- {
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
- *obufp++ = 'q';
- break;
- }
- /* Fall through. */
- goto case_Q;
case 'Q':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_Q:
if (intel_syntax && !alt)
break;
USED_REX (REX_W);
- if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS))
+ if ((need_modrm && modrm.mod != 3)
+ || (sizeflag & SUFFIX_ALWAYS))
{
if (rex & REX_W)
*obufp++ = 'q';
}
}
}
- else
+ else if (l == 1 && last[0] == 'D')
+ *obufp++ = vex.w ? 'q' : 'd';
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1 || len != 2 || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
- if (intel_syntax
- || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
+ if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
+ : address_mode != mode_64bit)
break;
if ((rex & REX_W))
{
USED_REX (REX_W);
*obufp++ = 'q';
}
- else
- *obufp++ = 'l';
- }
- break;
- case 'R':
- USED_REX (REX_W);
- if (rex & REX_W)
- *obufp++ = 'q';
- else if (sizeflag & DFLAG)
- {
- if (intel_syntax)
- *obufp++ = 'd';
- else
- *obufp++ = 'l';
+ else if((address_mode == mode_64bit && cond)
+ || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = intel_syntax? 'd' : 'l';
}
else
- *obufp++ = 'w';
- if (intel_syntax && !p[1]
- && ((rex & REX_W) || (sizeflag & DFLAG)))
- *obufp++ = 'e';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
+ abort ();
break;
- case 'V':
- if (l == 0 && len == 1)
- {
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit
- && ((sizeflag & DFLAG) || (rex & REX_W)))
- {
- if (sizeflag & SUFFIX_ALWAYS)
- *obufp++ = 'q';
- break;
- }
- }
- else
- {
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
- if (rex & REX_W)
- {
- *obufp++ = 'a';
- *obufp++ = 'b';
- *obufp++ = 's';
- }
+ case 'R':
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ *obufp++ = 'q';
+ else if (sizeflag & DFLAG)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
}
- /* Fall through. */
- goto case_S;
+ else
+ *obufp++ = 'w';
+ if (intel_syntax && !p[1]
+ && ((rex & REX_W) || (sizeflag & DFLAG)))
+ *obufp++ = 'e';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
case 'S':
- if (l == 0 && len == 1)
+ if (l == 0)
{
-case_S:
+ case_S:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
}
}
}
- else
+ else if (l == 1 && last[0] == 'L')
{
- if (l != 1
- || len != 2
- || last[0] != 'L')
- {
- SAVE_LAST (*p);
- break;
- }
-
if (address_mode == mode_64bit
&& !(prefixes & PREFIX_ADDR))
{
goto case_S;
}
+ else
+ abort ();
break;
- case 'X':
- if (l != 0 || len != 1)
+ case 'V':
+ if (l == 0)
+ abort ();
+ else if (l == 1
+ && (last[0] == 'L' || last[0] == 'X'))
{
- SAVE_LAST (*p);
- break;
+ if (last[0] == 'X')
+ {
+ *obufp++ = '{';
+ *obufp++ = 'v';
+ *obufp++ = 'e';
+ *obufp++ = 'x';
+ *obufp++ = '}';
+ }
+ else if (rex & REX_W)
+ {
+ *obufp++ = 'a';
+ *obufp++ = 'b';
+ *obufp++ = 's';
+ }
}
- if (need_vex && vex.prefix)
+ else
+ abort ();
+ goto case_S;
+ case 'W':
+ if (l == 0)
{
- if (vex.prefix == DATA_PREFIX_OPCODE)
- *obufp++ = 'd';
+ /* operand size flag for cwtl, cbtw */
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ if (intel_syntax)
+ *obufp++ = 'd';
+ else
+ *obufp++ = 'l';
+ }
+ else if (sizeflag & DFLAG)
+ *obufp++ = 'w';
else
- *obufp++ = 's';
+ *obufp++ = 'b';
+ if (!(rex & REX_W))
+ used_prefixes |= (prefixes & PREFIX_DATA);
}
- else
+ else if (l == 1)
{
- if (prefixes & PREFIX_DATA)
- *obufp++ = 'd';
+ if (!need_vex)
+ abort ();
+ if (last[0] == 'X')
+ *obufp++ = vex.w ? 'd': 's';
+ else if (last[0] == 'B')
+ *obufp++ = vex.w ? 'w': 'b';
else
- *obufp++ = 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
+ abort ();
}
+ else
+ abort ();
break;
- case 'Y':
- if (l == 0 && len == 1)
+ case 'X':
+ if (l != 0)
abort ();
+ if (need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : prefixes & PREFIX_DATA)
+ {
+ *obufp++ = 'd';
+ used_prefixes |= PREFIX_DATA;
+ }
else
+ *obufp++ = 's';
+ break;
+ case 'Y':
+ if (l == 1 && last[0] == 'X')
{
- if (l != 1 || len != 2 || last[0] != 'X')
- {
- SAVE_LAST (*p);
- break;
- }
if (!need_vex)
abort ();
if (intel_syntax
abort ();
}
}
+ else
+ abort ();
break;
- case 'W':
- if (l == 0 && len == 1)
+ case 'Z':
+ if (l == 0)
{
- /* operand size flag for cwtl, cbtw */
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- if (intel_syntax)
- *obufp++ = 'd';
- else
- *obufp++ = 'l';
- }
- else if (sizeflag & DFLAG)
- *obufp++ = 'w';
- else
- *obufp++ = 'b';
- if (!(rex & REX_W))
- used_prefixes |= (prefixes & PREFIX_DATA);
+ /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */
+ modrm.mod = 3;
+ if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = address_mode == mode_64bit ? 'q' : 'l';
}
- else
+ else if (l == 1 && last[0] == 'X')
{
- if (l != 1
- || len != 2
- || (last[0] != 'X'
- && last[0] != 'L'))
+ if (!need_vex || !vex.evex)
+ abort ();
+ if (intel_syntax
+ || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS)))
+ break;
+ switch (vex.length)
{
- SAVE_LAST (*p);
+ case 128:
+ *obufp++ = 'x';
break;
+ case 256:
+ *obufp++ = 'y';
+ break;
+ case 512:
+ *obufp++ = 'z';
+ break;
+ default:
+ abort ();
}
- if (!need_vex)
- abort ();
- if (last[0] == 'X')
- *obufp++ = vex.w ? 'd': 's';
- else
- *obufp++ = vex.w ? 'q': 'd';
}
+ else
+ abort ();
break;
case '^':
if (intel_syntax)
break;
+ if (isa64 == intel64 && (rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ break;
+ }
if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & DFLAG)
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
- case '@':
- if (intel_syntax)
- break;
- if (address_mode == mode_64bit
- && (isa64 == intel64
- || ((sizeflag & DFLAG) || (rex & REX_W))))
- *obufp++ = 'q';
- else if ((prefixes & PREFIX_DATA))
- {
- if (!(sizeflag & DFLAG))
- *obufp++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
}
- alt = 0;
+
+ if (len == l)
+ len = l = 0;
}
*obufp = 0;
mnemonicendp = obufp;
USED_REX (REX_W);
if (rex & REX_W)
oappend ("QWORD PTR ");
+ else if (bytemode == dq_mode)
+ oappend ("DWORD PTR ");
else
{
- if ((sizeflag & DFLAG) || bytemode == dq_mode)
+ if (sizeflag & DFLAG)
oappend ("DWORD PTR ");
else
oappend ("WORD PTR ");
oappend ("DWORD PTR ");
used_prefixes |= (prefixes & PREFIX_DATA);
break;
+ case movsxd_mode:
+ if (!(sizeflag & DFLAG) && isa64 == intel64)
+ oappend ("WORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
case d_mode:
- case d_scalar_mode:
- case d_scalar_swap_mode:
case d_swap_mode:
case dqd_mode:
oappend ("DWORD PTR ");
break;
case q_mode:
- case q_scalar_mode:
- case q_scalar_swap_mode:
case q_swap_mode:
oappend ("QWORD PTR ");
break;
case x_swap_mode:
case evex_x_gscat_mode:
case evex_x_nobcst_mode:
- case b_scalar_mode:
- case w_scalar_mode:
+ case bw_unit_mode:
if (need_vex)
{
switch (vex.length)
case o_mode:
oappend ("OWORD PTR ");
break;
- case xmm_mdq_mode:
- case vex_w_dq_mode:
case vex_scalar_w_dq_mode:
if (!need_vex)
abort ();
{
case b_mode:
case b_swap_mode:
- USED_REX (0);
+ if (reg & 4)
+ USED_REX (0);
if (rex)
names = names8rex;
else
USED_REX (REX_W);
if (rex & REX_W)
names = names64;
+ else if (bytemode != v_mode && bytemode != v_swap_mode)
+ names = names32;
else
{
- if ((sizeflag & DFLAG)
- || (bytemode != v_mode
- && bytemode != v_swap_mode))
+ if (sizeflag & DFLAG)
names = names32;
else
names = names16;
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case movsxd_mode:
+ if (!(sizeflag & DFLAG) && isa64 == intel64)
+ names = names16;
+ else
+ names = names32;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
case va_mode:
names = (address_mode == mode_64bit
? names64 : names32);
{
case dqw_mode:
case dw_mode:
+ case xmm_mw_mode:
shift = 1;
break;
case dqb_mode:
case db_mode:
+ case xmm_mb_mode:
shift = 0;
break;
case dq_mode:
if (address_mode != mode_64bit)
{
+ case dqd_mode:
+ case xmm_md_mode:
+ case d_mode:
+ case d_swap_mode:
shift = 2;
break;
}
/* fall through */
+ case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
case vex_vsib_q_w_d_mode:
case evex_x_gscat_mode:
- case xmm_mdq_mode:
shift = vex.w ? 3 : 2;
break;
case x_mode:
default:
abort ();
}
+ /* Make necessary corrections to shift for modes that need it. */
+ if (bytemode == xmmq_mode
+ || bytemode == evex_half_bcst_xmmq_mode
+ || (bytemode == ymmq_mode && vex.length == 128))
+ shift -= 1;
+ else if (bytemode == xmmqd_mode)
+ shift -= 2;
+ else if (bytemode == xmmdw_mode)
+ shift -= 3;
break;
case ymm_mode:
shift = 5;
break;
case xmm_mq_mode:
case q_mode:
- case q_scalar_mode:
case q_swap_mode:
- case q_scalar_swap_mode:
shift = 3;
break;
- case dqd_mode:
- case xmm_md_mode:
- case d_mode:
- case d_scalar_mode:
- case d_swap_mode:
- case d_scalar_swap_mode:
- shift = 2;
- break;
- case w_scalar_mode:
- case xmm_mw_mode:
- shift = 1;
- break;
- case b_scalar_mode:
- case xmm_mb_mode:
- shift = 0;
+ case bw_unit_mode:
+ shift = vex.w ? 1 : 0;
break;
default:
abort ();
}
- /* Make necessary corrections to shift for modes that need it.
- For these modes we currently have shift 4, 5 or 6 depending on
- vex.length (it corresponds to xmmword, ymmword or zmmword
- operand). We might want to make it 3, 4 or 5 (e.g. for
- xmmq_mode). In case of broadcast enabled the corrections
- aren't needed, as element size is always 32 or 64 bits. */
- if (!vex.b
- && (bytemode == xmmq_mode
- || bytemode == evex_half_bcst_xmmq_mode))
- shift -= 1;
- else if (bytemode == xmmqd_mode)
- shift -= 2;
- else if (bytemode == xmmdw_mode)
- shift -= 3;
- else if (bytemode == ymmq_mode && vex.length == 128)
- shift -= 1;
}
else
shift = 0;
base = sib.base;
codep++;
}
+ else
+ {
+ /* mandatory non-vector SIB must have sib */
+ if (bytemode == vex_sibmem_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ }
rbase = base + add;
switch (modrm.mod)
{
if (address_mode == mode_64bit)
{
- /* Display eiz instead of addr32. */
- needindex = addr32flag;
+ if (addr32flag)
+ {
+ /* Without base nor index registers, zero-extend the
+ lower 32-bit displacement to 64 bits. */
+ disp = (unsigned int) disp;
+ needindex = 1;
+ }
needaddr32 = 1;
}
else
}
if ((havebase || haveindex || needindex || needaddr32 || riprel)
- && (bytemode != v_bnd_mode)
- && (bytemode != v_bndmk_mode)
- && (bytemode != bnd_mode)
- && (bytemode != bnd_swap_mode))
+ && (address_mode != mode_64bit
+ || ((bytemode != v_bnd_mode)
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
{
*obufp++ = '-';
*obufp = '\0';
- disp = - (bfd_signed_vma) disp;
+ disp = -disp;
}
if (havedisp)
}
}
}
+ else if (bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
else
{
/* 16 bit address mode */
{
*obufp++ = '-';
*obufp = '\0';
- disp = - (bfd_signed_vma) disp;
+ disp = -disp;
}
print_displacement (scratchbuf, disp);
switch (bytemode)
{
case b_mode:
- USED_REX (0);
+ if (modrm.reg & 4)
+ USED_REX (0);
if (rex)
oappend (names8rex[modrm.reg + add]);
else
case dqb_mode:
case dqd_mode:
case dqw_mode:
+ case movsxd_mode:
USED_REX (REX_W);
if (rex & REX_W)
oappend (names64[modrm.reg + add]);
+ else if (bytemode != v_mode && bytemode != movsxd_mode)
+ oappend (names32[modrm.reg + add]);
else
{
- if ((sizeflag & DFLAG) || bytemode != v_mode)
+ if (sizeflag & DFLAG)
oappend (names32[modrm.reg + add]);
else
oappend (names16[modrm.reg + add]);
static bfd_signed_vma
get32 (void)
{
- bfd_signed_vma x = 0;
+ bfd_vma x = 0;
FETCH_DATA (the_info, codep + 4);
- x = *codep++ & (bfd_signed_vma) 0xff;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
+ x = *codep++ & (bfd_vma) 0xff;
+ x |= (*codep++ & (bfd_vma) 0xff) << 8;
+ x |= (*codep++ & (bfd_vma) 0xff) << 16;
+ x |= (*codep++ & (bfd_vma) 0xff) << 24;
return x;
}
static bfd_signed_vma
get32s (void)
{
- bfd_signed_vma x = 0;
+ bfd_vma x = 0;
FETCH_DATA (the_info, codep + 4);
- x = *codep++ & (bfd_signed_vma) 0xff;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 8;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 16;
- x |= (*codep++ & (bfd_signed_vma) 0xff) << 24;
+ x = *codep++ & (bfd_vma) 0xff;
+ x |= (*codep++ & (bfd_vma) 0xff) << 8;
+ x |= (*codep++ & (bfd_vma) 0xff) << 16;
+ x |= (*codep++ & (bfd_vma) 0xff) << 24;
- x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31);
+ x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
return x;
}
case sp_reg: case bp_reg: case si_reg: case di_reg:
s = names16[code - ax_reg + add];
break;
- case al_reg: case ah_reg: case cl_reg: case ch_reg:
- case dl_reg: case dh_reg: case bl_reg: case bh_reg:
+ case ah_reg: case ch_reg: case dh_reg: case bh_reg:
USED_REX (0);
+ /* Fall through. */
+ case al_reg: case cl_reg: case dl_reg: case bl_reg:
if (rex)
s = names8rex[code - al_reg + add];
else
else
s = "(%dx)";
break;
- case ax_reg: case cx_reg: case dx_reg: case bx_reg:
- case sp_reg: case bp_reg: case si_reg: case di_reg:
- s = names16[code - ax_reg];
- break;
- case es_reg: case ss_reg: case cs_reg:
- case ds_reg: case fs_reg: case gs_reg:
- s = names_seg[code - es_reg];
- break;
- case al_reg: case ah_reg: case cl_reg: case ch_reg:
- case dl_reg: case dh_reg: case bl_reg: case bh_reg:
- USED_REX (0);
- if (rex)
- s = names8rex[code - al_reg];
- else
- s = names8[code - al_reg];
+ case al_reg: case cl_reg:
+ s = names8[code - al_reg];
break;
- case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
- case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
+ case eAX_reg:
USED_REX (REX_W);
if (rex & REX_W)
- s = names64[code - eAX_reg];
- else
{
- if (sizeflag & DFLAG)
- s = names32[code - eAX_reg];
- else
- s = names16[code - eAX_reg];
- used_prefixes |= (prefixes & PREFIX_DATA);
+ s = *names64;
+ break;
}
- break;
+ /* Fall through. */
case z_mode_ax_reg:
if ((rex & REX_W) || (sizeflag & DFLAG))
s = *names32;
disp -= 0x100;
break;
case v_mode:
- if (isa64 == amd64)
- USED_REX (REX_W);
+ case dqw_mode:
if ((sizeflag & DFLAG)
|| (address_mode == mode_64bit
- && (isa64 != amd64 || (rex & REX_W))))
+ && ((isa64 == intel64 && bytemode != dqw_mode)
+ || (rex & REX_W))))
disp = get32s ();
else
{
& ~((bfd_vma) 0xffff));
}
if (address_mode != mode_64bit
- || (isa64 == amd64 && !(rex & REX_W)))
+ || (isa64 != intel64 && !(rex & REX_W)))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
default:
else
add = 0;
if (intel_syntax)
- sprintf (scratchbuf, "db%d", modrm.reg + add);
+ sprintf (scratchbuf, "dr%d", modrm.reg + add);
else
sprintf (scratchbuf, "%%db%d", modrm.reg + add);
oappend (scratchbuf);
oappend_maybe_intel (scratchbuf);
}
-static void
-OP_R (int bytemode, int sizeflag)
-{
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- OP_E_register (bytemode, sizeflag);
-}
-
static void
OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
+ && bytemode != tmm_mode
&& bytemode != scalar_mode)
{
switch (vex.length)
abort ();
}
}
+ else if (bytemode == tmm_mode)
+ {
+ modrm.reg = reg;
+ if (reg >= 8)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_tmm;
+ }
else if (bytemode == ymm_mode)
names = names_ymm;
else
if ((sizeflag & SUFFIX_ALWAYS)
&& (bytemode == x_swap_mode
|| bytemode == d_swap_mode
- || bytemode == d_scalar_swap_mode
- || bytemode == q_swap_mode
- || bytemode == q_scalar_swap_mode))
+ || bytemode == q_swap_mode))
swap_operand ();
if (need_vex
&& bytemode != xmm_mw_mode
&& bytemode != xmm_md_mode
&& bytemode != xmm_mq_mode
- && bytemode != xmm_mdq_mode
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
- && bytemode != d_scalar_mode
- && bytemode != d_scalar_swap_mode
- && bytemode != q_scalar_mode
- && bytemode != q_scalar_swap_mode
+ && bytemode != tmm_mode
&& bytemode != vex_scalar_w_dq_mode)
{
switch (vex.length)
abort ();
}
}
+ else if (bytemode == tmm_mode)
+ {
+ modrm.rm = reg;
+ if (reg >= 8)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_tmm;
+ }
else if (bytemode == ymm_mode)
names = names_ymm;
else
mnemonicendp = obufp;
}
-static struct op simd_cmp_op[] =
+static const struct op simd_cmp_op[] =
{
{ STRING_COMMA_LEN ("eq") },
{ STRING_COMMA_LEN ("lt") },
{ STRING_COMMA_LEN ("ord") }
};
+static const struct op vex_cmp_op[] =
+{
+ { STRING_COMMA_LEN ("eq_uq") },
+ { STRING_COMMA_LEN ("nge") },
+ { STRING_COMMA_LEN ("ngt") },
+ { STRING_COMMA_LEN ("false") },
+ { STRING_COMMA_LEN ("neq_oq") },
+ { STRING_COMMA_LEN ("ge") },
+ { STRING_COMMA_LEN ("gt") },
+ { STRING_COMMA_LEN ("true") },
+ { STRING_COMMA_LEN ("eq_os") },
+ { STRING_COMMA_LEN ("lt_oq") },
+ { STRING_COMMA_LEN ("le_oq") },
+ { STRING_COMMA_LEN ("unord_s") },
+ { STRING_COMMA_LEN ("neq_us") },
+ { STRING_COMMA_LEN ("nlt_uq") },
+ { STRING_COMMA_LEN ("nle_uq") },
+ { STRING_COMMA_LEN ("ord_s") },
+ { STRING_COMMA_LEN ("eq_us") },
+ { STRING_COMMA_LEN ("nge_uq") },
+ { STRING_COMMA_LEN ("ngt_uq") },
+ { STRING_COMMA_LEN ("false_os") },
+ { STRING_COMMA_LEN ("neq_os") },
+ { STRING_COMMA_LEN ("ge_oq") },
+ { STRING_COMMA_LEN ("gt_oq") },
+ { STRING_COMMA_LEN ("true_us") },
+};
+
static void
CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
mnemonicendp += simd_cmp_op[cmp_type].len;
}
+ else if (need_vex
+ && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
+ {
+ char suffix [3];
+ char *p = mnemonicendp - 2;
+ suffix[0] = p[0];
+ suffix[1] = p[1];
+ suffix[2] = '\0';
+ cmp_type -= ARRAY_SIZE (simd_cmp_op);
+ sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
+ mnemonicendp += vex_cmp_op[cmp_type].len;
+ }
else
{
/* We have a reserved extension byte. Output it directly. */
}
static void
-OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- /* mwaitx %eax,%ecx,%ebx */
- if (!intel_syntax)
- {
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[3]);
- two_source_ops = 1;
- }
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-}
-
-static void
-OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
+OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- /* mwait %eax,%ecx */
+ /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
if (!intel_syntax)
{
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
+ strcpy (op_out[0], names32[0]);
+ strcpy (op_out[1], names32[1]);
+ if (bytemode == eBX_reg)
+ strcpy (op_out[2], names32[3]);
two_source_ops = 1;
}
/* Skip mod/rm byte. */
OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
int sizeflag ATTRIBUTE_UNUSED)
{
- /* monitor %eax,%ecx,%edx" */
+ /* monitor %{e,r,}ax,%ecx,%edx" */
if (!intel_syntax)
{
- const char **op1_names;
const char **names = (address_mode == mode_64bit
? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- op1_names = (address_mode == mode_16bit
- ? names16 : names);
- else
+ if (prefixes & PREFIX_ADDR)
{
/* Remove "addr16/addr32". */
all_prefixes[last_addr_prefix] = 0;
- op1_names = (address_mode != mode_32bit
- ? names32 : names16);
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
used_prefixes |= PREFIX_ADDR;
}
- strcpy (op_out[0], op1_names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[2]);
+ else if (address_mode == mode_16bit)
+ names = names16;
+ strcpy (op_out[0], names[0]);
+ strcpy (op_out[1], names32[1]);
+ strcpy (op_out[2], names32[2]);
two_source_ops = 1;
}
/* Skip mod/rm byte. */
{
/* Throw away prefixes and 1st. opcode byte. */
codep = insn_codep + 1;
- oappend ("(bad)");
-}
-
-static void
-REP_Fixup (int bytemode, int sizeflag)
-{
- /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
- lods and stos. */
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = REP_PREFIX;
-
- switch (bytemode)
- {
- case al_reg:
- case eAX_reg:
- case indir_dx_reg:
- OP_IMREG (bytemode, sizeflag);
- break;
- case eDI_reg:
- OP_ESreg (bytemode, sizeflag);
- break;
- case eSI_reg:
- OP_DSreg (bytemode, sizeflag);
- break;
- default:
- abort ();
- break;
- }
-}
-
-/* For BND-prefixed instructions 0xF2 prefix should be displayed as
- "bnd". */
-
-static void
-BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = BND_PREFIX;
-}
-
-/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
- "notrack". */
-
-static void
-NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- if (active_seg_prefix == PREFIX_DS
- && (address_mode != mode_64bit || last_data_prefix < 0))
- {
- /* NOTRACK prefix is only valid on indirect branch instructions.
- NB: DATA prefix is unsupported for Intel64. */
- active_seg_prefix = 0;
- all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
- }
-}
-
-/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
- "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
- */
-
-static void
-HLE_Fixup1 (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3
- && (prefixes & PREFIX_LOCK) != 0)
- {
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
- }
-
- OP_E (bytemode, sizeflag);
-}
-
-/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
- "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
- */
-
-static void
-HLE_Fixup2 (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3)
- {
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
- }
-
- OP_E (bytemode, sizeflag);
-}
-
-/* Similar to OP_E. But the 0xf3 prefixes should be displayed as
- "xrelease" for memory operand. No check for LOCK prefix. */
-
-static void
-HLE_Fixup3 (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3
- && last_repz_prefix > last_repnz_prefix
- && (prefixes & PREFIX_REPZ) != 0)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
-
- OP_E (bytemode, sizeflag);
-}
-
-static void
-CMPXCHG8B_Fixup (int bytemode, int sizeflag)
-{
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- /* Change cmpxchg8b to cmpxchg16b. */
- char *p = mnemonicendp - 2;
- mnemonicendp = stpcpy (p, "16b");
- bytemode = o_mode;
- }
- else if ((prefixes & PREFIX_LOCK) != 0)
- {
- if (prefixes & PREFIX_REPZ)
- all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- if (prefixes & PREFIX_REPNZ)
- all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
- }
-
- OP_M (bytemode, sizeflag);
-}
-
-static void
-XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
-{
- const char **names;
-
- if (need_vex)
- {
- switch (vex.length)
- {
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- default:
- abort ();
- }
- }
- else
- names = names_xmm;
- oappend (names[reg]);
-}
-
-static void
-CRC32_Fixup (int bytemode, int sizeflag)
-{
- /* Add proper suffix to "crc32". */
- char *p = mnemonicendp;
-
- switch (bytemode)
- {
- case b_mode:
- if (intel_syntax)
- goto skip;
-
- *p++ = 'b';
- break;
- case v_mode:
- if (intel_syntax)
- goto skip;
-
- USED_REX (REX_W);
- if (rex & REX_W)
- *p++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *p++ = 'l';
- else
- *p++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- break;
- }
- mnemonicendp = p;
- *p = '\0';
-
-skip:
- if (modrm.mod == 3)
- {
- int add;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- USED_REX (REX_B);
- add = (rex & REX_B) ? 8 : 0;
- if (bytemode == b_mode)
- {
- USED_REX (0);
- if (rex)
- oappend (names8rex[modrm.rm + add]);
- else
- oappend (names8[modrm.rm + add]);
- }
- else
- {
- USED_REX (REX_W);
- if (rex & REX_W)
- oappend (names64[modrm.rm + add]);
- else if ((prefixes & PREFIX_DATA))
- oappend (names16[modrm.rm + add]);
- else
- oappend (names32[modrm.rm + add]);
- }
- }
- else
- OP_E (bytemode, sizeflag);
-}
-
-static void
-FXSAVE_Fixup (int bytemode, int sizeflag)
-{
- /* Add proper suffix to "fxsave" and "fxrstor". */
- USED_REX (REX_W);
- if (rex & REX_W)
- {
- char *p = mnemonicendp;
- *p++ = '6';
- *p++ = '4';
- *p = '\0';
- mnemonicendp = p;
- }
- OP_M (bytemode, sizeflag);
-}
-
-static void
-PCMPESTR_Fixup (int bytemode, int sizeflag)
-{
- /* Add proper suffix to "{,v}pcmpestr{i,m}". */
- if (!intel_syntax)
- {
- char *p = mnemonicendp;
-
- USED_REX (REX_W);
- if (rex & REX_W)
- *p++ = 'q';
- else if (sizeflag & SUFFIX_ALWAYS)
- *p++ = 'l';
-
- *p = '\0';
- mnemonicendp = p;
- }
-
- OP_EX (bytemode, sizeflag);
+ oappend ("(bad)");
}
-/* Display the destination register operand for instructions with
- VEX. */
-
static void
-OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+REP_Fixup (int bytemode, int sizeflag)
{
- int reg;
- const char **names;
-
- if (!need_vex)
- abort ();
-
- if (!need_vex_reg)
- return;
-
- reg = vex.register_specifier;
- vex.register_specifier = 0;
- if (address_mode != mode_64bit)
- reg &= 7;
- else if (vex.evex && !vex.v)
- reg += 16;
-
- if (bytemode == vex_scalar_mode)
- {
- oappend (names_xmm[reg]);
- return;
- }
+ /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
+ lods and stos. */
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = REP_PREFIX;
- switch (vex.length)
+ switch (bytemode)
{
- case 128:
- switch (bytemode)
- {
- case vex_mode:
- case vex128_mode:
- case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
- names = names_xmm;
- break;
- case dq_mode:
- if (rex & REX_W)
- names = names64;
- else
- names = names32;
- break;
- case mask_bd_mode:
- case mask_mode:
- if (reg > 0x7)
- {
- oappend ("(bad)");
- return;
- }
- names = names_mask;
- break;
- default:
- abort ();
- return;
- }
+ case al_reg:
+ case eAX_reg:
+ case indir_dx_reg:
+ OP_IMREG (bytemode, sizeflag);
break;
- case 256:
- switch (bytemode)
- {
- case vex_mode:
- case vex256_mode:
- names = names_ymm;
- break;
- case vex_vsib_q_w_dq_mode:
- case vex_vsib_q_w_d_mode:
- names = vex.w ? names_ymm : names_xmm;
- break;
- case mask_bd_mode:
- case mask_mode:
- if (reg > 0x7)
- {
- oappend ("(bad)");
- return;
- }
- names = names_mask;
- break;
- default:
- /* See PR binutils/20893 for a reproducer. */
- oappend ("(bad)");
- return;
- }
+ case eDI_reg:
+ OP_ESreg (bytemode, sizeflag);
break;
- case 512:
- names = names_zmm;
+ case eSI_reg:
+ OP_DSreg (bytemode, sizeflag);
break;
default:
abort ();
break;
}
- oappend (names[reg]);
}
-/* Get the VEX immediate byte without moving codep. */
-
-static unsigned char
-get_vex_imm8 (int sizeflag, int opnum)
+static void
+SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
- int bytes_before_imm = 0;
-
- if (modrm.mod != 3)
- {
- /* There are SIB/displacement bytes. */
- if ((sizeflag & AFLAG) || address_mode == mode_64bit)
- {
- /* 32/64 bit address mode */
- int base = modrm.rm;
-
- /* Check SIB byte. */
- if (base == 4)
- {
- FETCH_DATA (the_info, codep + 1);
- base = *codep & 7;
- /* When decoding the third source, don't increase
- bytes_before_imm as this has already been incremented
- by one in OP_E_memory while decoding the second
- source operand. */
- if (opnum == 0)
- bytes_before_imm++;
- }
+ if ( isa64 != amd64 )
+ return;
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 5 or modrm.rm == 4 and base in
- SIB == 5, there is a 4 byte displacement. */
- if (base != 5)
- /* No displacement. */
- break;
- /* Fall through. */
- case 2:
- /* 4 byte displacement. */
- bytes_before_imm += 4;
- break;
- case 1:
- /* 1 byte displacement. */
- bytes_before_imm++;
- break;
- }
- }
- }
- else
- {
- /* 16 bit address mode */
- /* Don't increase bytes_before_imm when decoding the third source,
- it has already been incremented by OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- {
- switch (modrm.mod)
- {
- case 0:
- /* When modrm.rm == 6, there is a 2 byte displacement. */
- if (modrm.rm != 6)
- /* No displacement. */
- break;
- /* Fall through. */
- case 2:
- /* 2 byte displacement. */
- bytes_before_imm += 2;
- break;
- case 1:
- /* 1 byte displacement: when decoding the third source,
- don't increase bytes_before_imm as this has already
- been incremented by one in OP_E_memory while decoding
- the second source operand. */
- if (opnum == 0)
- bytes_before_imm++;
+ obufp = obuf;
+ BadOp ();
+ mnemonicendp = obufp;
+ ++codep;
+}
- break;
- }
- }
- }
- }
+/* For BND-prefixed instructions 0xF2 prefix should be displayed as
+ "bnd". */
- FETCH_DATA (the_info, codep + bytes_before_imm + 1);
- return codep [bytes_before_imm];
+static void
+BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = BND_PREFIX;
}
+/* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
+ "notrack". */
+
static void
-OP_EX_VexReg (int bytemode, int sizeflag, int reg)
+NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
{
- const char **names;
- if (reg == -1 && modrm.mod != 3)
- {
- OP_E_memory (bytemode, sizeflag);
- return;
- }
- else
+ /* Since active_seg_prefix is not set in 64-bit mode, check whether
+ we've seen a PREFIX_DS. */
+ if ((prefixes & PREFIX_DS) != 0
+ && (address_mode != mode_64bit || last_data_prefix < 0))
{
- if (reg == -1)
- {
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- }
- if (address_mode != mode_64bit)
- reg &= 7;
+ /* NOTRACK prefix is only valid on indirect branch instructions.
+ NB: DATA prefix is unsupported for Intel64. */
+ active_seg_prefix = 0;
+ all_prefixes[last_seg_prefix] = NOTRACK_PREFIX;
}
+}
- switch (vex.length)
+/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
+ "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
+ */
+
+static void
+HLE_Fixup1 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3
+ && (prefixes & PREFIX_LOCK) != 0)
{
- case 128:
- names = names_xmm;
- break;
- case 256:
- names = names_ymm;
- break;
- default:
- abort ();
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
}
- oappend (names[reg]);
+
+ OP_E (bytemode, sizeflag);
}
+/* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as
+ "xacquire"/"xrelease" for memory operand. No check for LOCK prefix.
+ */
+
static void
-OP_EX_VexImmW (int bytemode, int sizeflag)
+HLE_Fixup2 (int bytemode, int sizeflag)
{
- int reg = -1;
- static unsigned char vex_imm8;
-
- if (vex_w_done == 0)
+ if (modrm.mod != 3)
{
- vex_w_done = 1;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- vex_imm8 = get_vex_imm8 (sizeflag, 0);
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
+ }
- if (vex.w)
- reg = vex_imm8 >> 4;
+ OP_E (bytemode, sizeflag);
+}
- OP_EX_VexReg (bytemode, sizeflag, reg);
- }
- else if (vex_w_done == 1)
- {
- vex_w_done = 2;
+/* Similar to OP_E. But the 0xf3 prefixes should be displayed as
+ "xrelease" for memory operand. No check for LOCK prefix. */
- if (!vex.w)
- reg = vex_imm8 >> 4;
+static void
+HLE_Fixup3 (int bytemode, int sizeflag)
+{
+ if (modrm.mod != 3
+ && last_repz_prefix > last_repnz_prefix
+ && (prefixes & PREFIX_REPZ) != 0)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
- OP_EX_VexReg (bytemode, sizeflag, reg);
- }
- else
- {
- /* Output the imm8 directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
- codep++;
- }
+ OP_E (bytemode, sizeflag);
}
static void
-OP_Vex_2src (int bytemode, int sizeflag)
+CMPXCHG8B_Fixup (int bytemode, int sizeflag)
{
- if (modrm.mod == 3)
+ USED_REX (REX_W);
+ if (rex & REX_W)
{
- int reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
- oappend (names_xmm[reg]);
+ /* Change cmpxchg8b to cmpxchg16b. */
+ char *p = mnemonicendp - 2;
+ mnemonicendp = stpcpy (p, "16b");
+ bytemode = o_mode;
}
- else
+ else if ((prefixes & PREFIX_LOCK) != 0)
{
- if (intel_syntax
- && (bytemode == v_mode || bytemode == v_swap_mode))
- {
- bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode;
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- OP_E (bytemode, sizeflag);
+ if (prefixes & PREFIX_REPZ)
+ all_prefixes[last_repz_prefix] = XRELEASE_PREFIX;
+ if (prefixes & PREFIX_REPNZ)
+ all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX;
}
+
+ OP_M (bytemode, sizeflag);
}
static void
-OP_Vex_2src_1 (int bytemode, int sizeflag)
+XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED)
{
- if (modrm.mod == 3)
- {
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
- }
+ const char **names;
- if (vex.w)
+ if (need_vex)
{
- unsigned int reg = vex.register_specifier;
- vex.register_specifier = 0;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names_xmm[reg]);
+ switch (vex.length)
+ {
+ case 128:
+ names = names_xmm;
+ break;
+ case 256:
+ names = names_ymm;
+ break;
+ default:
+ abort ();
+ }
}
else
- OP_Vex_2src (bytemode, sizeflag);
+ names = names_xmm;
+ oappend (names[reg]);
}
static void
-OP_Vex_2src_2 (int bytemode, int sizeflag)
+FXSAVE_Fixup (int bytemode, int sizeflag)
{
- if (vex.w)
- OP_Vex_2src (bytemode, sizeflag);
- else
+ /* Add proper suffix to "fxsave" and "fxrstor". */
+ USED_REX (REX_W);
+ if (rex & REX_W)
{
- unsigned int reg = vex.register_specifier;
- vex.register_specifier = 0;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names_xmm[reg]);
+ char *p = mnemonicendp;
+ *p++ = '6';
+ *p++ = '4';
+ *p = '\0';
+ mnemonicendp = p;
}
+ OP_M (bytemode, sizeflag);
}
-static void
-OP_EX_VexW (int bytemode, int sizeflag)
-{
- int reg = -1;
-
- if (!vex_w_done)
- {
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (vex.w)
- reg = get_vex_imm8 (sizeflag, 0) >> 4;
- }
- else
- {
- if (!vex.w)
- reg = get_vex_imm8 (sizeflag, 1) >> 4;
- }
-
- OP_EX_VexReg (bytemode, sizeflag, reg);
-
- if (vex_w_done)
- codep++;
- vex_w_done = 1;
-}
+/* Display the destination register operand for instructions with
+ VEX. */
static void
-OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
+OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
int reg;
const char **names;
- FETCH_DATA (the_info, codep + 1);
- reg = *codep++;
-
- if (bytemode != x_mode)
+ if (!need_vex)
abort ();
- reg >>= 4;
+ reg = vex.register_specifier;
+ vex.register_specifier = 0;
if (address_mode != mode_64bit)
reg &= 7;
+ else if (vex.evex && !vex.v)
+ reg += 16;
+
+ if (bytemode == vex_scalar_mode)
+ {
+ oappend (names_xmm[reg]);
+ return;
+ }
+
+ if (bytemode == tmm_mode)
+ {
+ /* All 3 TMM registers must be distinct. */
+ if (reg >= 8)
+ oappend ("(bad)");
+ else
+ {
+ /* This must be the 3rd operand. */
+ if (obufp != op_out[2])
+ abort ();
+ oappend (names_tmm[reg]);
+ if (reg == modrm.reg || reg == modrm.rm)
+ strcpy (obufp, "/(bad)");
+ }
+
+ if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg)
+ {
+ if (modrm.reg <= 8
+ && (modrm.reg == modrm.rm || modrm.reg == reg))
+ strcat (op_out[0], "/(bad)");
+ if (modrm.rm <= 8
+ && (modrm.rm == modrm.reg || modrm.rm == reg))
+ strcat (op_out[1], "/(bad)");
+ }
+
+ return;
+ }
switch (vex.length)
{
case 128:
- names = names_xmm;
+ switch (bytemode)
+ {
+ case vex_mode:
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ names = names_xmm;
+ break;
+ case dq_mode:
+ if (rex & REX_W)
+ names = names64;
+ else
+ names = names32;
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_mask;
+ break;
+ default:
+ abort ();
+ return;
+ }
break;
case 256:
- names = names_ymm;
+ switch (bytemode)
+ {
+ case vex_mode:
+ names = names_ymm;
+ break;
+ case vex_vsib_q_w_dq_mode:
+ case vex_vsib_q_w_d_mode:
+ names = vex.w ? names_ymm : names_xmm;
+ break;
+ case mask_bd_mode:
+ case mask_mode:
+ if (reg > 0x7)
+ {
+ oappend ("(bad)");
+ return;
+ }
+ names = names_mask;
+ break;
+ default:
+ /* See PR binutils/20893 for a reproducer. */
+ oappend ("(bad)");
+ return;
+ }
+ break;
+ case 512:
+ names = names_zmm;
break;
default:
abort ();
+ break;
}
oappend (names[reg]);
}
static void
-OP_XMM_VexW (int bytemode, int sizeflag)
+OP_VexR (int bytemode, int sizeflag)
{
- /* Turn off the REX.W bit since it is used for swapping operands
- now. */
- rex &= ~REX_W;
- OP_XMM (bytemode, sizeflag);
+ if (modrm.mod == 3)
+ OP_VEX (bytemode, sizeflag);
}
static void
-OP_EX_Vex (int bytemode, int sizeflag)
+OP_VexW (int bytemode, int sizeflag)
{
- if (modrm.mod != 3)
- need_vex_reg = 0;
- OP_EX (bytemode, sizeflag);
-}
+ OP_VEX (bytemode, sizeflag);
-static void
-OP_XMM_Vex (int bytemode, int sizeflag)
-{
- if (modrm.mod != 3)
- need_vex_reg = 0;
- OP_XMM (bytemode, sizeflag);
+ if (vex.w)
+ {
+ /* Swap 2nd and 3rd operands. */
+ strcpy (scratchbuf, op_out[2]);
+ strcpy (op_out[2], op_out[1]);
+ strcpy (op_out[1], scratchbuf);
+ }
}
-static struct op vex_cmp_op[] =
-{
- { STRING_COMMA_LEN ("eq") },
- { STRING_COMMA_LEN ("lt") },
- { STRING_COMMA_LEN ("le") },
- { STRING_COMMA_LEN ("unord") },
- { STRING_COMMA_LEN ("neq") },
- { STRING_COMMA_LEN ("nlt") },
- { STRING_COMMA_LEN ("nle") },
- { STRING_COMMA_LEN ("ord") },
- { STRING_COMMA_LEN ("eq_uq") },
- { STRING_COMMA_LEN ("nge") },
- { STRING_COMMA_LEN ("ngt") },
- { STRING_COMMA_LEN ("false") },
- { STRING_COMMA_LEN ("neq_oq") },
- { STRING_COMMA_LEN ("ge") },
- { STRING_COMMA_LEN ("gt") },
- { STRING_COMMA_LEN ("true") },
- { STRING_COMMA_LEN ("eq_os") },
- { STRING_COMMA_LEN ("lt_oq") },
- { STRING_COMMA_LEN ("le_oq") },
- { STRING_COMMA_LEN ("unord_s") },
- { STRING_COMMA_LEN ("neq_us") },
- { STRING_COMMA_LEN ("nlt_uq") },
- { STRING_COMMA_LEN ("nle_uq") },
- { STRING_COMMA_LEN ("ord_s") },
- { STRING_COMMA_LEN ("eq_us") },
- { STRING_COMMA_LEN ("nge_uq") },
- { STRING_COMMA_LEN ("ngt_uq") },
- { STRING_COMMA_LEN ("false_os") },
- { STRING_COMMA_LEN ("neq_os") },
- { STRING_COMMA_LEN ("ge_oq") },
- { STRING_COMMA_LEN ("gt_oq") },
- { STRING_COMMA_LEN ("true_us") },
-};
-
static void
-VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- unsigned int cmp_type;
+ int reg;
+ const char **names = names_xmm;
FETCH_DATA (the_info, codep + 1);
- cmp_type = *codep++ & 0xff;
- if (cmp_type < ARRAY_SIZE (vex_cmp_op))
- {
- char suffix [3];
- char *p = mnemonicendp - 2;
- suffix[0] = p[0];
- suffix[1] = p[1];
- suffix[2] = '\0';
- sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
- mnemonicendp += vex_cmp_op[cmp_type].len;
- }
- else
+ reg = *codep++;
+
+ if (bytemode != x_mode && bytemode != scalar_mode)
+ abort ();
+
+ reg >>= 4;
+ if (address_mode != mode_64bit)
+ reg &= 7;
+
+ if (bytemode == x_mode && vex.length == 256)
+ names = names_ymm;
+
+ oappend (names[reg]);
+
+ if (vex.w)
{
- /* We have a reserved extension byte. Output it directly. */
- scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, cmp_type);
- oappend_maybe_intel (scratchbuf);
- scratchbuf[0] = '\0';
+ /* Swap 3rd and 4th operands. */
+ strcpy (scratchbuf, op_out[3]);
+ strcpy (op_out[3], op_out[2]);
+ strcpy (op_out[2], scratchbuf);
}
}
+static void
+OP_VexI4 (int bytemode ATTRIBUTE_UNUSED,
+ int sizeflag ATTRIBUTE_UNUSED)
+{
+ scratchbuf[0] = '$';
+ print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf);
+ oappend_maybe_intel (scratchbuf);
+}
+
static void
VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED,
int sizeflag ATTRIBUTE_UNUSED)
}
static void
-MOVBE_Fixup (int bytemode, int sizeflag)
+MOVSXD_Fixup (int bytemode, int sizeflag)
{
- /* Add proper suffix to "movbe". */
+ /* Add proper suffix to "movsxd". */
char *p = mnemonicendp;
switch (bytemode)
{
- case v_mode:
+ case movsxd_mode:
if (intel_syntax)
- goto skip;
+ {
+ *p++ = 'x';
+ *p++ = 'd';
+ goto skip;
+ }
USED_REX (REX_W);
- if (sizeflag & SUFFIX_ALWAYS)
+ if (rex & REX_W)
{
- if (rex & REX_W)
- *p++ = 'q';
- else
- {
- if (sizeflag & DFLAG)
- *p++ = 'l';
- else
- *p++ = 'w';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ *p++ = 'l';
+ *p++ = 'q';
+ }
+ else
+ {
+ *p++ = 'x';
+ *p++ = 'd';
}
break;
default:
oappend (INTERNAL_DISASSEMBLER_ERROR);
break;
}
+
+ skip:
mnemonicendp = p;
*p = '\0';
-
-skip:
- OP_M (bytemode, sizeflag);
-}
-
-static void
-OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- int reg;
- const char **names;
-
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-
- if (rex & REX_W)
- names = names64;
- else
- names = names32;
-
- reg = modrm.rm;
- USED_REX (REX_B);
- if (rex & REX_B)
- reg += 8;
-
- oappend (names[reg]);
-}
-
-static void
-OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- const char **names;
- unsigned int reg = vex.register_specifier;
- vex.register_specifier = 0;
-
- if (rex & REX_W)
- names = names64;
- else
- names = names32;
-
- if (address_mode != mode_64bit)
- reg &= 7;
- oappend (names[reg]);
+ OP_E (bytemode, sizeflag);
}
static void
static void
OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- if (!vex.evex
- || (bytemode != evex_rounding_mode
- && bytemode != evex_rounding_64_mode
- && bytemode != evex_sae_mode))
- abort ();
if (modrm.mod == 3 && vex.b)
switch (bytemode)
{
oappend ("{sae}");
break;
default:
+ abort ();
break;
}
}
projects / thirdparty / binutils-gdb.git / blobdiff