/* Print i386 instructions for GDB, the GNU debugger.
- Copyright (C) 1988-2017 Free Software Foundation, Inc.
+ Copyright (C) 1988-2020 Free Software Foundation, Inc.
This file is part of the GNU opcodes library.
static void OP_Rounding (int, int);
static void OP_REG_VexI4 (int, int);
static void PCLMUL_Fixup (int, int);
-static void VZERO_Fixup (int, int);
static void VCMP_Fixup (int, int);
static void VPCMP_Fixup (int, int);
static void VPCOM_Fixup (int, int);
static void OP_0f07 (int, int);
static void OP_Monitor (int, int);
static void OP_Mwait (int, int);
-static void OP_Mwaitx (int, int);
static void NOP_Fixup1 (int, int);
static void NOP_Fixup2 (int, int);
static void OP_3DNowSuffix (int, int);
static void CMP_Fixup (int, int);
static void BadOp (void);
static void REP_Fixup (int, int);
+static void SEP_Fixup (int, int);
static void BND_Fixup (int, int);
static void NOTRACK_Fixup (int, int);
static void HLE_Fixup1 (int, int);
static void OP_Vex_2src_2 (int, int);
static void MOVBE_Fixup (int, int);
+static void MOVSXD_Fixup (int, int);
static void OP_Mask (int, int);
static int rex;
/* Bits of REX we've already used. */
static int rex_used;
-/* REX bits in original REX prefix ignored. */
-static int rex_ignored;
/* Mark parts used in the REX prefix. When we are testing for
empty prefix (for 8bit register REX extension), just mask it
out. Otherwise test for REX bit is excuse for existence of REX
#define Eb { OP_E, b_mode }
#define Ebnd { OP_E, bnd_mode }
#define EbS { OP_E, b_swap_mode }
+#define EbndS { OP_E, bnd_swap_mode }
#define Ev { OP_E, v_mode }
+#define Eva { OP_E, va_mode }
#define Ev_bnd { OP_E, v_bnd_mode }
#define EvS { OP_E, v_swap_mode }
#define Ed { OP_E, d_mode }
#define Mo { OP_M, o_mode }
#define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */
#define Mq { OP_M, q_mode }
+#define Mv_bnd { OP_M, v_bndmk_mode }
#define Mx { OP_M, x_mode }
#define Mxmm { OP_M, xmm_mode }
#define Gb { OP_G, b_mode }
#define Gd { OP_G, d_mode }
#define Gdq { OP_G, dq_mode }
#define Gm { OP_G, m_mode }
+#define Gva { OP_G, va_mode }
#define Gw { OP_G, w_mode }
#define Rd { OP_R, d_mode }
#define Rdq { OP_R, dq_mode }
#define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
#define Iv { OP_I, v_mode }
#define sIv { OP_sI, v_mode }
-#define Iq { OP_I, q_mode }
#define Iv64 { OP_I64, v_mode }
+#define Id { OP_I, d_mode }
#define Iw { OP_I, w_mode }
#define I1 { OP_I, const_1_mode }
#define Jb { OP_J, b_mode }
#define Jv { OP_J, v_mode }
+#define Jdqw { OP_J, dqw_mode }
#define Cm { OP_C, m_mode }
#define Dm { OP_D, m_mode }
#define Td { OP_T, d_mode }
#define EXd { OP_EX, d_mode }
#define EXdScalar { OP_EX, d_scalar_mode }
#define EXdS { OP_EX, d_swap_mode }
-#define EXdScalarS { OP_EX, d_scalar_swap_mode }
#define EXq { OP_EX, q_mode }
#define EXqScalar { OP_EX, q_scalar_mode }
#define EXqScalarS { OP_EX, q_scalar_swap_mode }
#define EXxmm_mw { OP_EX, xmm_mw_mode }
#define EXxmm_md { OP_EX, xmm_md_mode }
#define EXxmm_mq { OP_EX, xmm_mq_mode }
-#define EXxmm_mdq { OP_EX, xmm_mdq_mode }
#define EXxmmdw { OP_EX, xmmdw_mode }
#define EXxmmqd { OP_EX, xmmqd_mode }
#define EXymmq { OP_EX, ymmq_mode }
-#define EXVexWdq { OP_EX, vex_w_dq_mode }
#define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode }
#define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
#define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
#define EMCq { OP_EMC, q_mode }
#define MXC { OP_MXC, 0 }
#define OPSUF { OP_3DNowSuffix, 0 }
+#define SEP { SEP_Fixup, 0 }
#define CMP { CMP_Fixup, 0 }
#define XMM0 { XMM_Fixup, 0 }
#define FXSAVE { FXSAVE_Fixup, 0 }
#define Vex128 { OP_VEX, vex128_mode }
#define Vex256 { OP_VEX, vex256_mode }
#define VexGdq { OP_VEX, dq_mode }
-#define EXdVex { OP_EX_Vex, d_mode }
-#define EXdVexS { OP_EX_Vex, d_swap_mode }
#define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode }
-#define EXqVex { OP_EX_Vex, q_mode }
-#define EXqVexS { OP_EX_Vex, q_swap_mode }
#define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode }
#define EXVexW { OP_EX_VexW, x_mode }
#define EXdVexW { OP_EX_VexW, d_mode }
#define EXqVexW { OP_EX_VexW, q_mode }
#define EXVexImmW { OP_EX_VexImmW, x_mode }
-#define XMVex { OP_XMM_Vex, 0 }
#define XMVexScalar { OP_XMM_Vex, scalar_mode }
#define XMVexW { OP_XMM_VexW, 0 }
#define XMVexI4 { OP_REG_VexI4, x_mode }
#define PCLMUL { PCLMUL_Fixup, 0 }
-#define VZERO { VZERO_Fixup, 0 }
#define VCMP { VCMP_Fixup, 0 }
#define VPCMP { VPCMP_Fixup, 0 }
#define VPCOM { VPCOM_Fixup, 0 }
#define EXxEVexR { OP_Rounding, evex_rounding_mode }
+#define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
#define EXxEVexS { OP_Rounding, evex_sae_mode }
#define XMask { OP_Mask, mask_mode }
v_mode,
/* operand size depends on prefixes with operand swapped */
v_swap_mode,
+ /* operand size depends on address prefix */
+ va_mode,
/* word operand */
w_mode,
/* double word operand */
xmm_md_mode,
/* XMM register or quad word memory operand */
xmm_mq_mode,
- /* XMM register or double/quad word memory operand, depending on
- VEX.W. */
- xmm_mdq_mode,
/* 16-byte XMM, word, double word or quad word operand. */
xmmdw_mode,
/* 16-byte XMM, double word, quad word operand or xmm word operand. */
a_mode,
cond_jump_mode,
loop_jcxz_mode,
+ movsxd_mode,
v_bnd_mode,
+ /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */
+ v_bndmk_mode,
/* operand size depends on REX prefixes. */
dq_mode,
- /* registers like dq_mode, memory like w_mode. */
+ /* registers like dq_mode, memory like w_mode, displacements like
+ v_mode without considering Intel64 ISA. */
dqw_mode,
+ /* bounds operand */
bnd_mode,
+ /* bounds operand with operand swapped */
+ bnd_swap_mode,
/* 4- or 6-byte pointer operand */
f_mode,
const_1_mode,
vex128_mode,
/* 256bit vex mode */
vex256_mode,
- /* operand size depends on the VEX.W bit. */
- vex_w_dq_mode,
- /* Similar to vex_w_dq_mode, with VSIB dword indices. */
+ /* Operand size depends on the VEX.W bit, with VSIB dword indices. */
vex_vsib_d_w_dq_mode,
/* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */
vex_vsib_d_w_d_mode,
- /* Similar to vex_w_dq_mode, with VSIB qword indices. */
+ /* Operand size depends on the VEX.W bit, with VSIB qword indices. */
vex_vsib_q_w_dq_mode,
/* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */
vex_vsib_q_w_d_mode,
q_scalar_swap_mode,
/* like vex_mode, ignore vector length. */
vex_scalar_mode,
- /* like vex_w_dq_mode, ignore vector length. */
+ /* Operand size depends on the VEX.W bit, ignore vector length. */
vex_scalar_w_dq_mode,
/* Static rounding. */
evex_rounding_mode,
+ /* Static rounding, 64-bit mode only. */
+ evex_rounding_64_mode,
/* Supress all exceptions. */
evex_sae_mode,
USE_VEX_C5_TABLE,
USE_VEX_LEN_TABLE,
USE_VEX_W_TABLE,
- USE_EVEX_TABLE
+ USE_EVEX_TABLE,
+ USE_EVEX_LEN_TABLE
};
#define FLOAT NULL, { { NULL, FLOATCODE } }, 0
#define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I))
#define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I))
#define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I))
+#define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I))
enum
{
REG_0F01,
REG_0F0D,
REG_0F18,
- REG_0F1E_MOD_3,
+ REG_0F1C_P_0_MOD_0,
+ REG_0F1E_P_1_MOD_3,
REG_0F71,
REG_0F72,
REG_0F73,
MOD_0F01_REG_5,
MOD_0F01_REG_7,
MOD_0F12_PREFIX_0,
+ MOD_0F12_PREFIX_2,
MOD_0F13,
MOD_0F16_PREFIX_0,
+ MOD_0F16_PREFIX_2,
MOD_0F17,
MOD_0F18_REG_0,
MOD_0F18_REG_1,
MOD_0F1A_PREFIX_0,
MOD_0F1B_PREFIX_0,
MOD_0F1B_PREFIX_1,
+ MOD_0F1C_PREFIX_0,
MOD_0F1E_PREFIX_1,
MOD_0F24,
MOD_0F26,
MOD_0F2B_PREFIX_1,
MOD_0F2B_PREFIX_2,
MOD_0F2B_PREFIX_3,
- MOD_0F51,
+ MOD_0F50,
MOD_0F71_REG_2,
MOD_0F71_REG_4,
MOD_0F71_REG_6,
MOD_0F382A_PREFIX_2,
MOD_0F38F5_PREFIX_2,
MOD_0F38F6_PREFIX_0,
+ MOD_0F38F8_PREFIX_1,
+ MOD_0F38F8_PREFIX_2,
+ MOD_0F38F8_PREFIX_3,
+ MOD_0F38F9_PREFIX_0,
MOD_62_32BIT,
MOD_C4_32BIT,
MOD_C5_32BIT,
MOD_VEX_0F12_PREFIX_0,
+ MOD_VEX_0F12_PREFIX_2,
MOD_VEX_0F13,
MOD_VEX_0F16_PREFIX_0,
+ MOD_VEX_0F16_PREFIX_2,
MOD_VEX_0F17,
MOD_VEX_0F2B,
MOD_VEX_W_0_0F41_P_0_LEN_1,
MOD_VEX_W_1_0F91_P_2_LEN_0,
MOD_VEX_W_0_0F92_P_0_LEN_0,
MOD_VEX_W_0_0F92_P_2_LEN_0,
- MOD_VEX_W_0_0F92_P_3_LEN_0,
- MOD_VEX_W_1_0F92_P_3_LEN_0,
+ MOD_VEX_0F92_P_3_LEN_0,
MOD_VEX_W_0_0F93_P_0_LEN_0,
MOD_VEX_W_0_0F93_P_2_LEN_0,
- MOD_VEX_W_0_0F93_P_3_LEN_0,
- MOD_VEX_W_1_0F93_P_3_LEN_0,
+ MOD_VEX_0F93_P_3_LEN_0,
MOD_VEX_W_0_0F98_P_0_LEN_0,
MOD_VEX_W_1_0F98_P_0_LEN_0,
MOD_VEX_W_0_0F98_P_2_LEN_0,
MOD_VEX_W_0_0F3A33_P_2_LEN_0,
MOD_VEX_W_1_0F3A33_P_2_LEN_0,
- MOD_EVEX_0F10_PREFIX_1,
- MOD_EVEX_0F10_PREFIX_3,
- MOD_EVEX_0F11_PREFIX_1,
- MOD_EVEX_0F11_PREFIX_3,
MOD_EVEX_0F12_PREFIX_0,
+ MOD_EVEX_0F12_PREFIX_2,
+ MOD_EVEX_0F13,
MOD_EVEX_0F16_PREFIX_0,
+ MOD_EVEX_0F16_PREFIX_2,
+ MOD_EVEX_0F17,
+ MOD_EVEX_0F2B,
MOD_EVEX_0F38C6_REG_1,
MOD_EVEX_0F38C6_REG_2,
MOD_EVEX_0F38C6_REG_5,
RM_0F01_REG_1,
RM_0F01_REG_2,
RM_0F01_REG_3,
- RM_0F01_REG_5,
- RM_0F01_REG_7,
- RM_0F1E_MOD_3_REG_7,
- RM_0FAE_REG_6,
- RM_0FAE_REG_7
+ RM_0F01_REG_5_MOD_3,
+ RM_0F01_REG_7_MOD_3,
+ RM_0F1E_P_1_MOD_3_REG_7,
+ RM_0FAE_REG_6_MOD_3_P_0,
+ RM_0FAE_REG_7_MOD_3,
};
enum
{
PREFIX_90 = 0,
- PREFIX_MOD_0_0F01_REG_5,
- PREFIX_MOD_3_0F01_REG_5_RM_0,
- PREFIX_MOD_3_0F01_REG_5_RM_2,
+ PREFIX_0F01_REG_3_RM_1,
+ PREFIX_0F01_REG_5_MOD_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_0,
+ PREFIX_0F01_REG_5_MOD_3_RM_1,
+ PREFIX_0F01_REG_5_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_2,
+ PREFIX_0F01_REG_7_MOD_3_RM_3,
+ PREFIX_0F09,
PREFIX_0F10,
PREFIX_0F11,
PREFIX_0F12,
PREFIX_0F16,
PREFIX_0F1A,
PREFIX_0F1B,
+ PREFIX_0F1C,
PREFIX_0F1E,
PREFIX_0F2A,
PREFIX_0F2B,
PREFIX_0F7D,
PREFIX_0F7E,
PREFIX_0F7F,
- PREFIX_0FAE_REG_0,
- PREFIX_0FAE_REG_1,
- PREFIX_0FAE_REG_2,
- PREFIX_0FAE_REG_3,
- PREFIX_MOD_0_0FAE_REG_4,
- PREFIX_MOD_3_0FAE_REG_4,
- PREFIX_MOD_0_0FAE_REG_5,
- PREFIX_MOD_3_0FAE_REG_5,
- PREFIX_0FAE_REG_6,
- PREFIX_0FAE_REG_7,
+ PREFIX_0FAE_REG_0_MOD_3,
+ PREFIX_0FAE_REG_1_MOD_3,
+ PREFIX_0FAE_REG_2_MOD_3,
+ PREFIX_0FAE_REG_3_MOD_3,
+ PREFIX_0FAE_REG_4_MOD_0,
+ PREFIX_0FAE_REG_4_MOD_3,
+ PREFIX_0FAE_REG_5_MOD_0,
+ PREFIX_0FAE_REG_5_MOD_3,
+ PREFIX_0FAE_REG_6_MOD_0,
+ PREFIX_0FAE_REG_6_MOD_3,
+ PREFIX_0FAE_REG_7_MOD_0,
PREFIX_0FB8,
PREFIX_0FBC,
PREFIX_0FBD,
PREFIX_0FC2,
- PREFIX_MOD_0_0FC3,
- PREFIX_MOD_0_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_6,
- PREFIX_MOD_3_0FC7_REG_7,
+ PREFIX_0FC3_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_0,
+ PREFIX_0FC7_REG_6_MOD_3,
+ PREFIX_0FC7_REG_7_MOD_3,
PREFIX_0FD0,
PREFIX_0FD6,
PREFIX_0FE6,
PREFIX_0F38F1,
PREFIX_0F38F5,
PREFIX_0F38F6,
+ PREFIX_0F38F8,
+ PREFIX_0F38F9,
PREFIX_0F3A08,
PREFIX_0F3A09,
PREFIX_0F3A0A,
PREFIX_EVEX_0F10,
PREFIX_EVEX_0F11,
PREFIX_EVEX_0F12,
- PREFIX_EVEX_0F13,
- PREFIX_EVEX_0F14,
- PREFIX_EVEX_0F15,
PREFIX_EVEX_0F16,
- PREFIX_EVEX_0F17,
- PREFIX_EVEX_0F28,
- PREFIX_EVEX_0F29,
PREFIX_EVEX_0F2A,
- PREFIX_EVEX_0F2B,
PREFIX_EVEX_0F2C,
PREFIX_EVEX_0F2D,
PREFIX_EVEX_0F2E,
PREFIX_EVEX_0F2F,
PREFIX_EVEX_0F51,
- PREFIX_EVEX_0F54,
- PREFIX_EVEX_0F55,
- PREFIX_EVEX_0F56,
- PREFIX_EVEX_0F57,
PREFIX_EVEX_0F58,
PREFIX_EVEX_0F59,
PREFIX_EVEX_0F5A,
PREFIX_EVEX_0FC2,
PREFIX_EVEX_0FC4,
PREFIX_EVEX_0FC5,
- PREFIX_EVEX_0FC6,
PREFIX_EVEX_0FD1,
PREFIX_EVEX_0FD2,
PREFIX_EVEX_0FD3,
PREFIX_EVEX_0F3864,
PREFIX_EVEX_0F3865,
PREFIX_EVEX_0F3866,
+ PREFIX_EVEX_0F3868,
PREFIX_EVEX_0F3870,
PREFIX_EVEX_0F3871,
PREFIX_EVEX_0F3872,
{
X86_64_06 = 0,
X86_64_07,
- X86_64_0D,
+ X86_64_0E,
X86_64_16,
X86_64_17,
X86_64_1E,
X86_64_6F,
X86_64_82,
X86_64_9A,
+ X86_64_C2,
+ X86_64_C3,
X86_64_C4,
X86_64_C5,
X86_64_CE,
enum
{
- VEX_LEN_0F10_P_1 = 0,
- VEX_LEN_0F10_P_3,
- VEX_LEN_0F11_P_1,
- VEX_LEN_0F11_P_3,
- VEX_LEN_0F12_P_0_M_0,
+ VEX_LEN_0F12_P_0_M_0 = 0,
VEX_LEN_0F12_P_0_M_1,
- VEX_LEN_0F12_P_2,
+#define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0
VEX_LEN_0F13_M_0,
VEX_LEN_0F16_P_0_M_0,
VEX_LEN_0F16_P_0_M_1,
- VEX_LEN_0F16_P_2,
+#define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0
VEX_LEN_0F17_M_0,
- VEX_LEN_0F2A_P_1,
- VEX_LEN_0F2A_P_3,
- VEX_LEN_0F2C_P_1,
- VEX_LEN_0F2C_P_3,
- VEX_LEN_0F2D_P_1,
- VEX_LEN_0F2D_P_3,
- VEX_LEN_0F2E_P_0,
- VEX_LEN_0F2E_P_2,
- VEX_LEN_0F2F_P_0,
- VEX_LEN_0F2F_P_2,
VEX_LEN_0F41_P_0,
VEX_LEN_0F41_P_2,
VEX_LEN_0F42_P_0,
VEX_LEN_0F4A_P_2,
VEX_LEN_0F4B_P_0,
VEX_LEN_0F4B_P_2,
- VEX_LEN_0F51_P_1,
- VEX_LEN_0F51_P_3,
- VEX_LEN_0F52_P_1,
- VEX_LEN_0F53_P_1,
- VEX_LEN_0F58_P_1,
- VEX_LEN_0F58_P_3,
- VEX_LEN_0F59_P_1,
- VEX_LEN_0F59_P_3,
- VEX_LEN_0F5A_P_1,
- VEX_LEN_0F5A_P_3,
- VEX_LEN_0F5C_P_1,
- VEX_LEN_0F5C_P_3,
- VEX_LEN_0F5D_P_1,
- VEX_LEN_0F5D_P_3,
- VEX_LEN_0F5E_P_1,
- VEX_LEN_0F5E_P_3,
- VEX_LEN_0F5F_P_1,
- VEX_LEN_0F5F_P_3,
VEX_LEN_0F6E_P_2,
+ VEX_LEN_0F77_P_0,
VEX_LEN_0F7E_P_1,
VEX_LEN_0F7E_P_2,
VEX_LEN_0F90_P_0,
VEX_LEN_0F99_P_2,
VEX_LEN_0FAE_R_2_M_0,
VEX_LEN_0FAE_R_3_M_0,
- VEX_LEN_0FC2_P_1,
- VEX_LEN_0FC2_P_3,
VEX_LEN_0FC4_P_2,
VEX_LEN_0FC5_P_2,
VEX_LEN_0FD6_P_2,
VEX_LEN_0F3A00_P_2,
VEX_LEN_0F3A01_P_2,
VEX_LEN_0F3A06_P_2,
- VEX_LEN_0F3A0A_P_2,
- VEX_LEN_0F3A0B_P_2,
VEX_LEN_0F3A14_P_2,
VEX_LEN_0F3A15_P_2,
VEX_LEN_0F3A16_P_2,
enum
{
- VEX_W_0F10_P_0 = 0,
- VEX_W_0F10_P_1,
- VEX_W_0F10_P_2,
- VEX_W_0F10_P_3,
- VEX_W_0F11_P_0,
- VEX_W_0F11_P_1,
- VEX_W_0F11_P_2,
- VEX_W_0F11_P_3,
- VEX_W_0F12_P_0_M_0,
- VEX_W_0F12_P_0_M_1,
- VEX_W_0F12_P_1,
- VEX_W_0F12_P_2,
- VEX_W_0F12_P_3,
- VEX_W_0F13_M_0,
- VEX_W_0F14,
- VEX_W_0F15,
- VEX_W_0F16_P_0_M_0,
- VEX_W_0F16_P_0_M_1,
- VEX_W_0F16_P_1,
- VEX_W_0F16_P_2,
- VEX_W_0F17_M_0,
- VEX_W_0F28,
- VEX_W_0F29,
- VEX_W_0F2B_M_0,
- VEX_W_0F2E_P_0,
- VEX_W_0F2E_P_2,
- VEX_W_0F2F_P_0,
- VEX_W_0F2F_P_2,
- VEX_W_0F41_P_0_LEN_1,
+ EVEX_LEN_0F6E_P_2 = 0,
+ EVEX_LEN_0F7E_P_1,
+ EVEX_LEN_0F7E_P_2,
+ EVEX_LEN_0FD6_P_2,
+ EVEX_LEN_0F3819_P_2_W_0,
+ EVEX_LEN_0F3819_P_2_W_1,
+ EVEX_LEN_0F381A_P_2_W_0,
+ EVEX_LEN_0F381A_P_2_W_1,
+ EVEX_LEN_0F381B_P_2_W_0,
+ EVEX_LEN_0F381B_P_2_W_1,
+ EVEX_LEN_0F385A_P_2_W_0,
+ EVEX_LEN_0F385A_P_2_W_1,
+ EVEX_LEN_0F385B_P_2_W_0,
+ EVEX_LEN_0F385B_P_2_W_1,
+ EVEX_LEN_0F38C6_REG_1_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_2_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_5_PREFIX_2,
+ EVEX_LEN_0F38C6_REG_6_PREFIX_2,
+ EVEX_LEN_0F38C7_R_1_P_2_W_0,
+ EVEX_LEN_0F38C7_R_1_P_2_W_1,
+ EVEX_LEN_0F38C7_R_2_P_2_W_0,
+ EVEX_LEN_0F38C7_R_2_P_2_W_1,
+ EVEX_LEN_0F38C7_R_5_P_2_W_0,
+ EVEX_LEN_0F38C7_R_5_P_2_W_1,
+ EVEX_LEN_0F38C7_R_6_P_2_W_0,
+ EVEX_LEN_0F38C7_R_6_P_2_W_1,
+ EVEX_LEN_0F3A18_P_2_W_0,
+ EVEX_LEN_0F3A18_P_2_W_1,
+ EVEX_LEN_0F3A19_P_2_W_0,
+ EVEX_LEN_0F3A19_P_2_W_1,
+ EVEX_LEN_0F3A1A_P_2_W_0,
+ EVEX_LEN_0F3A1A_P_2_W_1,
+ EVEX_LEN_0F3A1B_P_2_W_0,
+ EVEX_LEN_0F3A1B_P_2_W_1,
+ EVEX_LEN_0F3A23_P_2_W_0,
+ EVEX_LEN_0F3A23_P_2_W_1,
+ EVEX_LEN_0F3A38_P_2_W_0,
+ EVEX_LEN_0F3A38_P_2_W_1,
+ EVEX_LEN_0F3A39_P_2_W_0,
+ EVEX_LEN_0F3A39_P_2_W_1,
+ EVEX_LEN_0F3A3A_P_2_W_0,
+ EVEX_LEN_0F3A3A_P_2_W_1,
+ EVEX_LEN_0F3A3B_P_2_W_0,
+ EVEX_LEN_0F3A3B_P_2_W_1,
+ EVEX_LEN_0F3A43_P_2_W_0,
+ EVEX_LEN_0F3A43_P_2_W_1
+};
+
+enum
+{
+ VEX_W_0F41_P_0_LEN_1 = 0,
VEX_W_0F41_P_2_LEN_1,
VEX_W_0F42_P_0_LEN_1,
VEX_W_0F42_P_2_LEN_1,
VEX_W_0F4A_P_2_LEN_1,
VEX_W_0F4B_P_0_LEN_1,
VEX_W_0F4B_P_2_LEN_1,
- VEX_W_0F50_M_0,
- VEX_W_0F51_P_0,
- VEX_W_0F51_P_1,
- VEX_W_0F51_P_2,
- VEX_W_0F51_P_3,
- VEX_W_0F52_P_0,
- VEX_W_0F52_P_1,
- VEX_W_0F53_P_0,
- VEX_W_0F53_P_1,
- VEX_W_0F58_P_0,
- VEX_W_0F58_P_1,
- VEX_W_0F58_P_2,
- VEX_W_0F58_P_3,
- VEX_W_0F59_P_0,
- VEX_W_0F59_P_1,
- VEX_W_0F59_P_2,
- VEX_W_0F59_P_3,
- VEX_W_0F5A_P_0,
- VEX_W_0F5A_P_1,
- VEX_W_0F5A_P_3,
- VEX_W_0F5B_P_0,
- VEX_W_0F5B_P_1,
- VEX_W_0F5B_P_2,
- VEX_W_0F5C_P_0,
- VEX_W_0F5C_P_1,
- VEX_W_0F5C_P_2,
- VEX_W_0F5C_P_3,
- VEX_W_0F5D_P_0,
- VEX_W_0F5D_P_1,
- VEX_W_0F5D_P_2,
- VEX_W_0F5D_P_3,
- VEX_W_0F5E_P_0,
- VEX_W_0F5E_P_1,
- VEX_W_0F5E_P_2,
- VEX_W_0F5E_P_3,
- VEX_W_0F5F_P_0,
- VEX_W_0F5F_P_1,
- VEX_W_0F5F_P_2,
- VEX_W_0F5F_P_3,
- VEX_W_0F60_P_2,
- VEX_W_0F61_P_2,
- VEX_W_0F62_P_2,
- VEX_W_0F63_P_2,
- VEX_W_0F64_P_2,
- VEX_W_0F65_P_2,
- VEX_W_0F66_P_2,
- VEX_W_0F67_P_2,
- VEX_W_0F68_P_2,
- VEX_W_0F69_P_2,
- VEX_W_0F6A_P_2,
- VEX_W_0F6B_P_2,
- VEX_W_0F6C_P_2,
- VEX_W_0F6D_P_2,
- VEX_W_0F6F_P_1,
- VEX_W_0F6F_P_2,
- VEX_W_0F70_P_1,
- VEX_W_0F70_P_2,
- VEX_W_0F70_P_3,
- VEX_W_0F71_R_2_P_2,
- VEX_W_0F71_R_4_P_2,
- VEX_W_0F71_R_6_P_2,
- VEX_W_0F72_R_2_P_2,
- VEX_W_0F72_R_4_P_2,
- VEX_W_0F72_R_6_P_2,
- VEX_W_0F73_R_2_P_2,
- VEX_W_0F73_R_3_P_2,
- VEX_W_0F73_R_6_P_2,
- VEX_W_0F73_R_7_P_2,
- VEX_W_0F74_P_2,
- VEX_W_0F75_P_2,
- VEX_W_0F76_P_2,
- VEX_W_0F77_P_0,
- VEX_W_0F7C_P_2,
- VEX_W_0F7C_P_3,
- VEX_W_0F7D_P_2,
- VEX_W_0F7D_P_3,
- VEX_W_0F7E_P_1,
- VEX_W_0F7F_P_1,
- VEX_W_0F7F_P_2,
VEX_W_0F90_P_0_LEN_0,
VEX_W_0F90_P_2_LEN_0,
VEX_W_0F91_P_0_LEN_0,
VEX_W_0F91_P_2_LEN_0,
VEX_W_0F92_P_0_LEN_0,
VEX_W_0F92_P_2_LEN_0,
- VEX_W_0F92_P_3_LEN_0,
VEX_W_0F93_P_0_LEN_0,
VEX_W_0F93_P_2_LEN_0,
- VEX_W_0F93_P_3_LEN_0,
VEX_W_0F98_P_0_LEN_0,
VEX_W_0F98_P_2_LEN_0,
VEX_W_0F99_P_0_LEN_0,
VEX_W_0F99_P_2_LEN_0,
- VEX_W_0FAE_R_2_M_0,
- VEX_W_0FAE_R_3_M_0,
- VEX_W_0FC2_P_0,
- VEX_W_0FC2_P_1,
- VEX_W_0FC2_P_2,
- VEX_W_0FC2_P_3,
- VEX_W_0FC4_P_2,
- VEX_W_0FC5_P_2,
- VEX_W_0FD0_P_2,
- VEX_W_0FD0_P_3,
- VEX_W_0FD1_P_2,
- VEX_W_0FD2_P_2,
- VEX_W_0FD3_P_2,
- VEX_W_0FD4_P_2,
- VEX_W_0FD5_P_2,
- VEX_W_0FD6_P_2,
- VEX_W_0FD7_P_2_M_1,
- VEX_W_0FD8_P_2,
- VEX_W_0FD9_P_2,
- VEX_W_0FDA_P_2,
- VEX_W_0FDB_P_2,
- VEX_W_0FDC_P_2,
- VEX_W_0FDD_P_2,
- VEX_W_0FDE_P_2,
- VEX_W_0FDF_P_2,
- VEX_W_0FE0_P_2,
- VEX_W_0FE1_P_2,
- VEX_W_0FE2_P_2,
- VEX_W_0FE3_P_2,
- VEX_W_0FE4_P_2,
- VEX_W_0FE5_P_2,
- VEX_W_0FE6_P_1,
- VEX_W_0FE6_P_2,
- VEX_W_0FE6_P_3,
- VEX_W_0FE7_P_2_M_0,
- VEX_W_0FE8_P_2,
- VEX_W_0FE9_P_2,
- VEX_W_0FEA_P_2,
- VEX_W_0FEB_P_2,
- VEX_W_0FEC_P_2,
- VEX_W_0FED_P_2,
- VEX_W_0FEE_P_2,
- VEX_W_0FEF_P_2,
- VEX_W_0FF0_P_3_M_0,
- VEX_W_0FF1_P_2,
- VEX_W_0FF2_P_2,
- VEX_W_0FF3_P_2,
- VEX_W_0FF4_P_2,
- VEX_W_0FF5_P_2,
- VEX_W_0FF6_P_2,
- VEX_W_0FF7_P_2,
- VEX_W_0FF8_P_2,
- VEX_W_0FF9_P_2,
- VEX_W_0FFA_P_2,
- VEX_W_0FFB_P_2,
- VEX_W_0FFC_P_2,
- VEX_W_0FFD_P_2,
- VEX_W_0FFE_P_2,
- VEX_W_0F3800_P_2,
- VEX_W_0F3801_P_2,
- VEX_W_0F3802_P_2,
- VEX_W_0F3803_P_2,
- VEX_W_0F3804_P_2,
- VEX_W_0F3805_P_2,
- VEX_W_0F3806_P_2,
- VEX_W_0F3807_P_2,
- VEX_W_0F3808_P_2,
- VEX_W_0F3809_P_2,
- VEX_W_0F380A_P_2,
- VEX_W_0F380B_P_2,
VEX_W_0F380C_P_2,
VEX_W_0F380D_P_2,
VEX_W_0F380E_P_2,
VEX_W_0F380F_P_2,
VEX_W_0F3816_P_2,
- VEX_W_0F3817_P_2,
VEX_W_0F3818_P_2,
VEX_W_0F3819_P_2,
VEX_W_0F381A_P_2_M_0,
- VEX_W_0F381C_P_2,
- VEX_W_0F381D_P_2,
- VEX_W_0F381E_P_2,
- VEX_W_0F3820_P_2,
- VEX_W_0F3821_P_2,
- VEX_W_0F3822_P_2,
- VEX_W_0F3823_P_2,
- VEX_W_0F3824_P_2,
- VEX_W_0F3825_P_2,
- VEX_W_0F3828_P_2,
- VEX_W_0F3829_P_2,
- VEX_W_0F382A_P_2_M_0,
- VEX_W_0F382B_P_2,
VEX_W_0F382C_P_2_M_0,
VEX_W_0F382D_P_2_M_0,
VEX_W_0F382E_P_2_M_0,
VEX_W_0F382F_P_2_M_0,
- VEX_W_0F3830_P_2,
- VEX_W_0F3831_P_2,
- VEX_W_0F3832_P_2,
- VEX_W_0F3833_P_2,
- VEX_W_0F3834_P_2,
- VEX_W_0F3835_P_2,
VEX_W_0F3836_P_2,
- VEX_W_0F3837_P_2,
- VEX_W_0F3838_P_2,
- VEX_W_0F3839_P_2,
- VEX_W_0F383A_P_2,
- VEX_W_0F383B_P_2,
- VEX_W_0F383C_P_2,
- VEX_W_0F383D_P_2,
- VEX_W_0F383E_P_2,
- VEX_W_0F383F_P_2,
- VEX_W_0F3840_P_2,
- VEX_W_0F3841_P_2,
VEX_W_0F3846_P_2,
VEX_W_0F3858_P_2,
VEX_W_0F3859_P_2,
VEX_W_0F3878_P_2,
VEX_W_0F3879_P_2,
VEX_W_0F38CF_P_2,
- VEX_W_0F38DB_P_2,
VEX_W_0F3A00_P_2,
VEX_W_0F3A01_P_2,
VEX_W_0F3A02_P_2,
VEX_W_0F3A04_P_2,
VEX_W_0F3A05_P_2,
VEX_W_0F3A06_P_2,
- VEX_W_0F3A08_P_2,
- VEX_W_0F3A09_P_2,
- VEX_W_0F3A0A_P_2,
- VEX_W_0F3A0B_P_2,
- VEX_W_0F3A0C_P_2,
- VEX_W_0F3A0D_P_2,
- VEX_W_0F3A0E_P_2,
- VEX_W_0F3A0F_P_2,
- VEX_W_0F3A14_P_2,
- VEX_W_0F3A15_P_2,
VEX_W_0F3A18_P_2,
VEX_W_0F3A19_P_2,
- VEX_W_0F3A20_P_2,
- VEX_W_0F3A21_P_2,
VEX_W_0F3A30_P_2_LEN_0,
VEX_W_0F3A31_P_2_LEN_0,
VEX_W_0F3A32_P_2_LEN_0,
VEX_W_0F3A33_P_2_LEN_0,
VEX_W_0F3A38_P_2,
VEX_W_0F3A39_P_2,
- VEX_W_0F3A40_P_2,
- VEX_W_0F3A41_P_2,
- VEX_W_0F3A42_P_2,
VEX_W_0F3A46_P_2,
VEX_W_0F3A48_P_2,
VEX_W_0F3A49_P_2,
VEX_W_0F3A4A_P_2,
VEX_W_0F3A4B_P_2,
VEX_W_0F3A4C_P_2,
- VEX_W_0F3A62_P_2,
- VEX_W_0F3A63_P_2,
VEX_W_0F3ACE_P_2,
VEX_W_0F3ACF_P_2,
- VEX_W_0F3ADF_P_2,
-
- EVEX_W_0F10_P_0,
- EVEX_W_0F10_P_1_M_0,
- EVEX_W_0F10_P_1_M_1,
- EVEX_W_0F10_P_2,
- EVEX_W_0F10_P_3_M_0,
- EVEX_W_0F10_P_3_M_1,
- EVEX_W_0F11_P_0,
- EVEX_W_0F11_P_1_M_0,
- EVEX_W_0F11_P_1_M_1,
- EVEX_W_0F11_P_2,
- EVEX_W_0F11_P_3_M_0,
- EVEX_W_0F11_P_3_M_1,
- EVEX_W_0F12_P_0_M_0,
+
+ EVEX_W_0F10_P_1,
+ EVEX_W_0F10_P_3,
+ EVEX_W_0F11_P_1,
+ EVEX_W_0F11_P_3,
EVEX_W_0F12_P_0_M_1,
EVEX_W_0F12_P_1,
- EVEX_W_0F12_P_2,
EVEX_W_0F12_P_3,
- EVEX_W_0F13_P_0,
- EVEX_W_0F13_P_2,
- EVEX_W_0F14_P_0,
- EVEX_W_0F14_P_2,
- EVEX_W_0F15_P_0,
- EVEX_W_0F15_P_2,
- EVEX_W_0F16_P_0_M_0,
EVEX_W_0F16_P_0_M_1,
EVEX_W_0F16_P_1,
- EVEX_W_0F16_P_2,
- EVEX_W_0F17_P_0,
- EVEX_W_0F17_P_2,
- EVEX_W_0F28_P_0,
- EVEX_W_0F28_P_2,
- EVEX_W_0F29_P_0,
- EVEX_W_0F29_P_2,
- EVEX_W_0F2A_P_1,
EVEX_W_0F2A_P_3,
- EVEX_W_0F2B_P_0,
- EVEX_W_0F2B_P_2,
- EVEX_W_0F2E_P_0,
- EVEX_W_0F2E_P_2,
- EVEX_W_0F2F_P_0,
- EVEX_W_0F2F_P_2,
- EVEX_W_0F51_P_0,
EVEX_W_0F51_P_1,
- EVEX_W_0F51_P_2,
EVEX_W_0F51_P_3,
- EVEX_W_0F54_P_0,
- EVEX_W_0F54_P_2,
- EVEX_W_0F55_P_0,
- EVEX_W_0F55_P_2,
- EVEX_W_0F56_P_0,
- EVEX_W_0F56_P_2,
- EVEX_W_0F57_P_0,
- EVEX_W_0F57_P_2,
- EVEX_W_0F58_P_0,
EVEX_W_0F58_P_1,
- EVEX_W_0F58_P_2,
EVEX_W_0F58_P_3,
- EVEX_W_0F59_P_0,
EVEX_W_0F59_P_1,
- EVEX_W_0F59_P_2,
EVEX_W_0F59_P_3,
EVEX_W_0F5A_P_0,
EVEX_W_0F5A_P_1,
EVEX_W_0F5B_P_0,
EVEX_W_0F5B_P_1,
EVEX_W_0F5B_P_2,
- EVEX_W_0F5C_P_0,
EVEX_W_0F5C_P_1,
- EVEX_W_0F5C_P_2,
EVEX_W_0F5C_P_3,
- EVEX_W_0F5D_P_0,
EVEX_W_0F5D_P_1,
- EVEX_W_0F5D_P_2,
EVEX_W_0F5D_P_3,
- EVEX_W_0F5E_P_0,
EVEX_W_0F5E_P_1,
- EVEX_W_0F5E_P_2,
EVEX_W_0F5E_P_3,
- EVEX_W_0F5F_P_0,
EVEX_W_0F5F_P_1,
- EVEX_W_0F5F_P_2,
EVEX_W_0F5F_P_3,
EVEX_W_0F62_P_2,
EVEX_W_0F66_P_2,
EVEX_W_0F6B_P_2,
EVEX_W_0F6C_P_2,
EVEX_W_0F6D_P_2,
- EVEX_W_0F6E_P_2,
EVEX_W_0F6F_P_1,
EVEX_W_0F6F_P_2,
EVEX_W_0F6F_P_3,
EVEX_W_0F7A_P_1,
EVEX_W_0F7A_P_2,
EVEX_W_0F7A_P_3,
- EVEX_W_0F7B_P_1,
EVEX_W_0F7B_P_2,
EVEX_W_0F7B_P_3,
EVEX_W_0F7E_P_1,
- EVEX_W_0F7E_P_2,
EVEX_W_0F7F_P_1,
EVEX_W_0F7F_P_2,
EVEX_W_0F7F_P_3,
- EVEX_W_0FC2_P_0,
EVEX_W_0FC2_P_1,
- EVEX_W_0FC2_P_2,
EVEX_W_0FC2_P_3,
- EVEX_W_0FC6_P_0,
- EVEX_W_0FC6_P_2,
EVEX_W_0FD2_P_2,
EVEX_W_0FD3_P_2,
EVEX_W_0FD4_P_2,
EVEX_W_0F3839_P_1,
EVEX_W_0F383A_P_1,
EVEX_W_0F3840_P_2,
+ EVEX_W_0F3852_P_1,
EVEX_W_0F3854_P_2,
EVEX_W_0F3855_P_2,
EVEX_W_0F3858_P_2,
EVEX_W_0F3862_P_2,
EVEX_W_0F3863_P_2,
EVEX_W_0F3866_P_2,
+ EVEX_W_0F3868_P_3,
EVEX_W_0F3870_P_2,
EVEX_W_0F3871_P_2,
+ EVEX_W_0F3872_P_1,
EVEX_W_0F3872_P_2,
+ EVEX_W_0F3872_P_3,
EVEX_W_0F3873_P_2,
EVEX_W_0F3875_P_2,
EVEX_W_0F3878_P_2,
EVEX_W_0F3A09_P_2,
EVEX_W_0F3A0A_P_2,
EVEX_W_0F3A0B_P_2,
- EVEX_W_0F3A16_P_2,
EVEX_W_0F3A18_P_2,
EVEX_W_0F3A19_P_2,
EVEX_W_0F3A1A_P_2,
EVEX_W_0F3A1B_P_2,
EVEX_W_0F3A1D_P_2,
EVEX_W_0F3A21_P_2,
- EVEX_W_0F3A22_P_2,
EVEX_W_0F3A23_P_2,
EVEX_W_0F3A38_P_2,
EVEX_W_0F3A39_P_2,
'H' => print ",pt" or ",pn" branch hint
'I' => honor following macro letter even in Intel mode (implemented only
for some of the macro letters)
- 'J' => print 'l'
+ 'J' unused.
'K' => print 'd' or 'q' if rex prefix is present.
'L' => print 'l' if suffix_always is true
'M' => print 'r' if intel_mnemonic is false.
prefix and behave as 'S' otherwise
'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
'X' => print 's', 'd' depending on data16 prefix (for XMM)
- 'Y' => 'q' if instruction has an REX 64bit overwrite prefix and
- suffix_always is true.
+ 'Y' unused.
'Z' => print 'q' in 64bit mode and behave as 'L' otherwise
'!' => change condition from true to false or from false to true.
'%' => add 1 upper case letter to the macro.
- '^' => print 'w' or 'l' depending on operand size prefix or
- suffix_always is true (lcall/ljmp).
+ '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
+ prefix or suffix_always is true (lcall/ljmp).
'@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending
on operand size prefix.
'&' => print 'q' in 64bit mode for Intel64 ISA or if instruction
"XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
register operands and no broadcast.
"XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
- "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand
- or suffix_always is true
+ "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory
+ operand or no operand at all in 64bit mode, or if suffix_always
+ is true.
"LB" => print "abs" in 64bit mode and behave as 'B' otherwise
"LS" => print "abs" in 64bit mode and behave as 'S' otherwise
"LV" => print "abs" for 64bit operand and behave as 'S' otherwise
{ "orS", { Gv, EvS }, 0 },
{ "orB", { AL, Ib }, 0 },
{ "orS", { eAX, Iv }, 0 },
- { X86_64_TABLE (X86_64_0D) },
+ { X86_64_TABLE (X86_64_0E) },
{ Bad_Opcode }, /* 0x0f extended opcode escape */
/* 10 */
{ "adcB", { Ebh1, Gb }, 0 },
/* c0 */
{ REG_TABLE (REG_C0) },
{ REG_TABLE (REG_C1) },
- { "retT", { Iw, BND }, 0 },
- { "retT", { BND }, 0 },
+ { X86_64_TABLE (X86_64_C2) },
+ { X86_64_TABLE (X86_64_C3) },
{ X86_64_TABLE (X86_64_C4) },
{ X86_64_TABLE (X86_64_C5) },
{ REG_TABLE (REG_C6) },
/* c8 */
{ "enterT", { Iw, Ib }, 0 },
{ "leaveT", { XX }, 0 },
- { "Jret{|f}P", { Iw }, 0 },
- { "Jret{|f}P", { XX }, 0 },
+ { "{l|}ret{|f}P", { Iw }, 0 },
+ { "{l|}ret{|f}P", { XX }, 0 },
{ "int3", { XX }, 0 },
{ "int", { Ib }, 0 },
{ X86_64_TABLE (X86_64_CE) },
{ Bad_Opcode },
{ "syscall", { XX }, 0 },
{ "clts", { XX }, 0 },
- { "sysret%LP", { XX }, 0 },
+ { "sysret%LQ", { XX }, 0 },
/* 08 */
{ "invd", { XX }, 0 },
- { "wbinvd", { XX }, 0 },
+ { PREFIX_TABLE (PREFIX_0F09) },
{ Bad_Opcode },
{ "ud2", { XX }, 0 },
{ Bad_Opcode },
{ "nopQ", { Ev }, 0 },
{ PREFIX_TABLE (PREFIX_0F1A) },
{ PREFIX_TABLE (PREFIX_0F1B) },
- { "nopQ", { Ev }, 0 },
+ { PREFIX_TABLE (PREFIX_0F1C) },
{ "nopQ", { Ev }, 0 },
{ PREFIX_TABLE (PREFIX_0F1E) },
{ "nopQ", { Ev }, 0 },
{ "rdtsc", { XX }, 0 },
{ "rdmsr", { XX }, 0 },
{ "rdpmc", { XX }, 0 },
- { "sysenter", { XX }, 0 },
- { "sysexit", { XX }, 0 },
+ { "sysenter", { SEP }, 0 },
+ { "sysexit", { SEP }, 0 },
{ Bad_Opcode },
{ "getsec", { XX }, 0 },
/* 38 */
{ "cmovleS", { Gv, Ev }, 0 },
{ "cmovgS", { Gv, Ev }, 0 },
/* 50 */
- { MOD_TABLE (MOD_0F51) },
+ { MOD_TABLE (MOD_0F50) },
{ PREFIX_TABLE (PREFIX_0F51) },
{ PREFIX_TABLE (PREFIX_0F52) },
{ PREFIX_TABLE (PREFIX_0F53) },
{ "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
/* b8 */
{ PREFIX_TABLE (PREFIX_0FB8) },
- { "ud1", { XX }, 0 },
+ { "ud1S", { Gv, Ev }, 0 },
{ REG_TABLE (REG_0FBA) },
{ "btcS", { Evh1, Gv }, 0 },
{ PREFIX_TABLE (PREFIX_0FBC) },
{ "paddb", { MX, EM }, PREFIX_OPCODE },
{ "paddw", { MX, EM }, PREFIX_OPCODE },
{ "paddd", { MX, EM }, PREFIX_OPCODE },
- { Bad_Opcode },
+ { "ud0S", { Gv, Ev }, 0 },
};
static const unsigned char onebyte_has_modrm[256] = {
/* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
/* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
/* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
- /* b0 */ 1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1, /* bf */
+ /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
/* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
/* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
/* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
- /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0 /* ff */
+ /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */
/* ------------------------------- */
/* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
};
{ MOD_TABLE (MOD_0F18_REG_6) },
{ MOD_TABLE (MOD_0F18_REG_7) },
},
- /* REG_0F1E_MOD_3 */
+ /* REG_0F1C_P_0_MOD_0 */
+ {
+ { "cldemote", { Mb }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ /* REG_0F1E_P_1_MOD_3 */
{
{ "nopQ", { Ev }, 0 },
{ "rdsspK", { Rdq }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
- { RM_TABLE (RM_0F1E_MOD_3_REG_7) },
+ { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
},
/* REG_0F71 */
{
},
/* REG_XOP_LWP */
{
- { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
- { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 },
+ { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
+ { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 },
},
/* REG_XOP_TBM_01 */
{
{ Bad_Opcode },
- { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 },
- { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 },
+ { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 },
},
/* REG_XOP_TBM_02 */
{
{ Bad_Opcode },
- { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
- { "blci", { { OP_LWP_E, 0 }, Ev }, 0 },
+ { "blci", { { OP_LWP_E, 0 }, Edq }, 0 },
},
-#define NEED_REG_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_REG_TABLE
+
+#include "i386-dis-evex-reg.h"
};
static const struct dis386 prefix_table[][4] = {
{ NULL, { { NULL, 0 } }, PREFIX_IGNORED }
},
- /* PREFIX_MOD_0_0F01_REG_5 */
+ /* PREFIX_0F01_REG_3_RM_1 */
{
+ { "vmmcall", { Skip_MODRM }, 0 },
+ { "vmgexit", { Skip_MODRM }, 0 },
{ Bad_Opcode },
- { "rstorssp", { Mq }, PREFIX_OPCODE },
+ { "vmgexit", { Skip_MODRM }, 0 },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_0 */
+ /* PREFIX_0F01_REG_5_MOD_0 */
{
{ Bad_Opcode },
+ { "rstorssp", { Mq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
+ {
+ { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
+ { Bad_Opcode },
+ { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
+ {
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { Bad_Opcode },
+ { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0F01_REG_5_RM_2 */
+ /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
{
{ Bad_Opcode },
{ "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE },
},
+ /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
+ {
+ { "monitorx", { { OP_Monitor, 0 } }, 0 },
+ { "mcommit", { Skip_MODRM }, 0 },
+ },
+
+ /* PREFIX_0F01_REG_7_MOD_3_RM_3 */
+ {
+ { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 },
+ },
+
+ /* PREFIX_0F09 */
+ {
+ { "wbinvd", { XX }, 0 },
+ { "wbnoinvd", { XX }, 0 },
+ },
+
/* PREFIX_0F10 */
{
{ "movups", { XM, EXx }, PREFIX_OPCODE },
{
{ MOD_TABLE (MOD_0F12_PREFIX_0) },
{ "movsldup", { XM, EXx }, PREFIX_OPCODE },
- { "movlpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F12_PREFIX_2) },
{ "movddup", { XM, EXq }, PREFIX_OPCODE },
},
{
{ MOD_TABLE (MOD_0F16_PREFIX_0) },
{ "movshdup", { XM, EXx }, PREFIX_OPCODE },
- { "movhpd", { XM, EXq }, PREFIX_OPCODE },
+ { MOD_TABLE (MOD_0F16_PREFIX_2) },
},
/* PREFIX_0F1A */
{
{ MOD_TABLE (MOD_0F1B_PREFIX_0) },
{ MOD_TABLE (MOD_0F1B_PREFIX_1) },
- { "bndmov", { Ebnd, Gbnd }, 0 },
+ { "bndmov", { EbndS, Gbnd }, 0 },
{ "bndcn", { Gbnd, Ev_bnd }, 0 },
},
+ /* PREFIX_0F1C */
+ {
+ { MOD_TABLE (MOD_0F1C_PREFIX_0) },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ { "nopQ", { Ev }, PREFIX_OPCODE },
+ },
+
/* PREFIX_0F1E */
{
{ "nopQ", { Ev }, PREFIX_OPCODE },
/* PREFIX_0F2A */
{
{ "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE },
+ { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE },
{ "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
- { "cvtsi2sd%LQ", { XM, Ev }, 0 },
+ { "cvtsi2sd%LQ", { XM, Edq }, 0 },
},
/* PREFIX_0F2B */
/* PREFIX_0F2C */
{
{ "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvttss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
{ "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvttsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2D */
{
{ "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
- { "cvtss2siY", { Gv, EXd }, PREFIX_OPCODE },
+ { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
{ "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
- { "cvtsd2siY", { Gv, EXq }, PREFIX_OPCODE },
+ { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
},
/* PREFIX_0F2E */
{ "movdqa", { EXxS, XM }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_0 */
+ /* PREFIX_0FAE_REG_0_MOD_3 */
{
{ Bad_Opcode },
{ "rdfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_1 */
+ /* PREFIX_0FAE_REG_1_MOD_3 */
{
{ Bad_Opcode },
{ "rdgsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_2 */
+ /* PREFIX_0FAE_REG_2_MOD_3 */
{
{ Bad_Opcode },
{ "wrfsbase", { Ev }, 0 },
},
- /* PREFIX_0FAE_REG_3 */
+ /* PREFIX_0FAE_REG_3_MOD_3 */
{
{ Bad_Opcode },
{ "wrgsbase", { Ev }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_0 */
{
{ "xsave", { FXSAVE }, 0 },
{ "ptwrite%LQ", { Edq }, 0 },
},
- /* PREFIX_MOD_3_0FAE_REG_4 */
+ /* PREFIX_0FAE_REG_4_MOD_3 */
{
{ Bad_Opcode },
{ "ptwrite%LQ", { Edq }, 0 },
},
- /* PREFIX_MOD_0_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_0 */
{
{ "xrstor", { FXSAVE }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_3_0FAE_REG_5 */
+ /* PREFIX_0FAE_REG_5_MOD_3 */
{
{ "lfence", { Skip_MODRM }, 0 },
{ "incsspK", { Rdq }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_6 */
+ /* PREFIX_0FAE_REG_6_MOD_0 */
{
{ "xsaveopt", { FXSAVE }, PREFIX_OPCODE },
{ "clrssbsy", { Mq }, PREFIX_OPCODE },
{ "clwb", { Mb }, PREFIX_OPCODE },
},
- /* PREFIX_0FAE_REG_7 */
+ /* PREFIX_0FAE_REG_6_MOD_3 */
+ {
+ { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
+ { "umonitor", { Eva }, PREFIX_OPCODE },
+ { "tpause", { Edq }, PREFIX_OPCODE },
+ { "umwait", { Edq }, PREFIX_OPCODE },
+ },
+
+ /* PREFIX_0FAE_REG_7_MOD_0 */
{
{ "clflush", { Mb }, 0 },
{ Bad_Opcode },
{ "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC3 */
+ /* PREFIX_0FC3_MOD_0 */
{
- { "movntiS", { Ev, Gv }, PREFIX_OPCODE },
+ { "movntiS", { Edq, Gdq }, PREFIX_OPCODE },
},
- /* PREFIX_MOD_0_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_0 */
{
{ "vmptrld",{ Mq }, 0 },
{ "vmxon", { Mq }, 0 },
{ "vmclear",{ Mq }, 0 },
},
- /* PREFIX_MOD_3_0FC7_REG_6 */
+ /* PREFIX_0FC7_REG_6_MOD_3 */
{
{ "rdrand", { Ev }, 0 },
{ Bad_Opcode },
{ "rdrand", { Ev }, 0 }
},
- /* PREFIX_MOD_3_0FC7_REG_7 */
+ /* PREFIX_0FC7_REG_7_MOD_3 */
{
{ "rdseed", { Ev }, 0 },
{ "rdpid", { Em }, 0 },
{ Bad_Opcode },
},
+ /* PREFIX_0F38F8 */
+ {
+ { Bad_Opcode },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_1) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_2) },
+ { MOD_TABLE (MOD_0F38F8_PREFIX_3) },
+ },
+
+ /* PREFIX_0F38F9 */
+ {
+ { MOD_TABLE (MOD_0F38F9_PREFIX_0) },
+ },
+
/* PREFIX_0F3A08 */
{
{ Bad_Opcode },
/* PREFIX_VEX_0F10 */
{
- { VEX_W_TABLE (VEX_W_0F10_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F10_P_1) },
- { VEX_W_TABLE (VEX_W_0F10_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F10_P_3) },
+ { "vmovups", { XM, EXx }, 0 },
+ { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
+ { "vmovupd", { XM, EXx }, 0 },
+ { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F11 */
{
- { VEX_W_TABLE (VEX_W_0F11_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F11_P_1) },
- { VEX_W_TABLE (VEX_W_0F11_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F11_P_3) },
+ { "vmovups", { EXxS, XM }, 0 },
+ { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
+ { "vmovupd", { EXxS, XM }, 0 },
+ { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
},
/* PREFIX_VEX_0F12 */
{
{ MOD_TABLE (MOD_VEX_0F12_PREFIX_0) },
- { VEX_W_TABLE (VEX_W_0F12_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
- { VEX_W_TABLE (VEX_W_0F12_P_3) },
+ { "vmovsldup", { XM, EXx }, 0 },
+ { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) },
+ { "vmovddup", { XM, EXymmq }, 0 },
},
/* PREFIX_VEX_0F16 */
{
{ MOD_TABLE (MOD_VEX_0F16_PREFIX_0) },
- { VEX_W_TABLE (VEX_W_0F16_P_1) },
- { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
+ { "vmovshdup", { XM, EXx }, 0 },
+ { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) },
},
/* PREFIX_VEX_0F2A */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) },
+ { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) },
+ { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 },
},
/* PREFIX_VEX_0F2C */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) },
+ { "vcvttss2si", { Gdq, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) },
+ { "vcvttsd2si", { Gdq, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F2D */
{
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) },
+ { "vcvtss2si", { Gdq, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) },
+ { "vcvtsd2si", { Gdq, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F2E */
{
- { VEX_LEN_TABLE (VEX_LEN_0F2E_P_0) },
+ { "vucomiss", { XMScalar, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2E_P_2) },
+ { "vucomisd", { XMScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F2F */
{
- { VEX_LEN_TABLE (VEX_LEN_0F2F_P_0) },
+ { "vcomiss", { XMScalar, EXdScalar }, 0 },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F2F_P_2) },
+ { "vcomisd", { XMScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F41 */
/* PREFIX_VEX_0F51 */
{
- { VEX_W_TABLE (VEX_W_0F51_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F51_P_1) },
- { VEX_W_TABLE (VEX_W_0F51_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F51_P_3) },
+ { "vsqrtps", { XM, EXx }, 0 },
+ { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vsqrtpd", { XM, EXx }, 0 },
+ { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F52 */
{
- { VEX_W_TABLE (VEX_W_0F52_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F52_P_1) },
+ { "vrsqrtps", { XM, EXx }, 0 },
+ { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
/* PREFIX_VEX_0F53 */
{
- { VEX_W_TABLE (VEX_W_0F53_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F53_P_1) },
+ { "vrcpps", { XM, EXx }, 0 },
+ { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
},
/* PREFIX_VEX_0F58 */
{
- { VEX_W_TABLE (VEX_W_0F58_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F58_P_1) },
- { VEX_W_TABLE (VEX_W_0F58_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F58_P_3) },
+ { "vaddps", { XM, Vex, EXx }, 0 },
+ { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vaddpd", { XM, Vex, EXx }, 0 },
+ { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F59 */
{
- { VEX_W_TABLE (VEX_W_0F59_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F59_P_1) },
- { VEX_W_TABLE (VEX_W_0F59_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F59_P_3) },
+ { "vmulps", { XM, Vex, EXx }, 0 },
+ { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vmulpd", { XM, Vex, EXx }, 0 },
+ { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F5A */
{
- { VEX_W_TABLE (VEX_W_0F5A_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5A_P_1) },
- { "vcvtpd2ps%XY", { XMM, EXx }, 0 },
- { VEX_LEN_TABLE (VEX_LEN_0F5A_P_3) },
+ { "vcvtps2pd", { XM, EXxmmq }, 0 },
+ { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vcvtpd2ps%XY",{ XMM, EXx }, 0 },
+ { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F5B */
{
- { VEX_W_TABLE (VEX_W_0F5B_P_0) },
- { VEX_W_TABLE (VEX_W_0F5B_P_1) },
- { VEX_W_TABLE (VEX_W_0F5B_P_2) },
+ { "vcvtdq2ps", { XM, EXx }, 0 },
+ { "vcvttps2dq", { XM, EXx }, 0 },
+ { "vcvtps2dq", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F5C */
{
- { VEX_W_TABLE (VEX_W_0F5C_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5C_P_1) },
- { VEX_W_TABLE (VEX_W_0F5C_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5C_P_3) },
+ { "vsubps", { XM, Vex, EXx }, 0 },
+ { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vsubpd", { XM, Vex, EXx }, 0 },
+ { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F5D */
{
- { VEX_W_TABLE (VEX_W_0F5D_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5D_P_1) },
- { VEX_W_TABLE (VEX_W_0F5D_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5D_P_3) },
+ { "vminps", { XM, Vex, EXx }, 0 },
+ { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vminpd", { XM, Vex, EXx }, 0 },
+ { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F5E */
{
- { VEX_W_TABLE (VEX_W_0F5E_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5E_P_1) },
- { VEX_W_TABLE (VEX_W_0F5E_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5E_P_3) },
+ { "vdivps", { XM, Vex, EXx }, 0 },
+ { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vdivpd", { XM, Vex, EXx }, 0 },
+ { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F5F */
{
- { VEX_W_TABLE (VEX_W_0F5F_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0F5F_P_1) },
- { VEX_W_TABLE (VEX_W_0F5F_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0F5F_P_3) },
+ { "vmaxps", { XM, Vex, EXx }, 0 },
+ { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ { "vmaxpd", { XM, Vex, EXx }, 0 },
+ { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
},
/* PREFIX_VEX_0F60 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F60_P_2) },
+ { "vpunpcklbw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F61 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F61_P_2) },
+ { "vpunpcklwd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F62 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F62_P_2) },
+ { "vpunpckldq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F63 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F63_P_2) },
+ { "vpacksswb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F64 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F64_P_2) },
+ { "vpcmpgtb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F65 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F65_P_2) },
+ { "vpcmpgtw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F66 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F66_P_2) },
+ { "vpcmpgtd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F67 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F67_P_2) },
+ { "vpackuswb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F68 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F68_P_2) },
+ { "vpunpckhbw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F69 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F69_P_2) },
+ { "vpunpckhwd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6A_P_2) },
+ { "vpunpckhdq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6B_P_2) },
+ { "vpackssdw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6C_P_2) },
+ { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6D_P_2) },
+ { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F6E */
/* PREFIX_VEX_0F6F */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F6F_P_1) },
- { VEX_W_TABLE (VEX_W_0F6F_P_2) },
+ { "vmovdqu", { XM, EXx }, 0 },
+ { "vmovdqa", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F70 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F70_P_1) },
- { VEX_W_TABLE (VEX_W_0F70_P_2) },
- { VEX_W_TABLE (VEX_W_0F70_P_3) },
+ { "vpshufhw", { XM, EXx, Ib }, 0 },
+ { "vpshufd", { XM, EXx, Ib }, 0 },
+ { "vpshuflw", { XM, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F71_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_2_P_2) },
+ { "vpsrlw", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F71_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_4_P_2) },
+ { "vpsraw", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F71_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F71_R_6_P_2) },
+ { "vpsllw", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F72_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_2_P_2) },
+ { "vpsrld", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F72_REG_4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_4_P_2) },
+ { "vpsrad", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F72_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F72_R_6_P_2) },
+ { "vpslld", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_2_P_2) },
+ { "vpsrlq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_3_P_2) },
+ { "vpsrldq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_6_P_2) },
+ { "vpsllq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F73_REG_7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F73_R_7_P_2) },
+ { "vpslldq", { Vex, XS, Ib }, 0 },
},
/* PREFIX_VEX_0F74 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F74_P_2) },
+ { "vpcmpeqb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F75 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F75_P_2) },
+ { "vpcmpeqw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F76 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F76_P_2) },
+ { "vpcmpeqd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F77 */
{
- { VEX_W_TABLE (VEX_W_0F77_P_0) },
+ { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) },
},
/* PREFIX_VEX_0F7C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7C_P_2) },
- { VEX_W_TABLE (VEX_W_0F7C_P_3) },
+ { "vhaddpd", { XM, Vex, EXx }, 0 },
+ { "vhaddps", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F7D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7D_P_2) },
- { VEX_W_TABLE (VEX_W_0F7D_P_3) },
+ { "vhsubpd", { XM, Vex, EXx }, 0 },
+ { "vhsubps", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F7E */
/* PREFIX_VEX_0F7F */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F7F_P_1) },
- { VEX_W_TABLE (VEX_W_0F7F_P_2) },
+ { "vmovdqu", { EXxS, XM }, 0 },
+ { "vmovdqa", { EXxS, XM }, 0 },
},
/* PREFIX_VEX_0F90 */
/* PREFIX_VEX_0FC2 */
{
- { VEX_W_TABLE (VEX_W_0FC2_P_0) },
- { VEX_LEN_TABLE (VEX_LEN_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_2) },
- { VEX_LEN_TABLE (VEX_LEN_0FC2_P_3) },
+ { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
+ { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
+ { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
+ { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
},
/* PREFIX_VEX_0FC4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD0_P_2) },
- { VEX_W_TABLE (VEX_W_0FD0_P_3) },
+ { "vaddsubpd", { XM, Vex, EXx }, 0 },
+ { "vaddsubps", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD1_P_2) },
+ { "vpsrlw", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FD2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD2_P_2) },
+ { "vpsrld", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FD3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD3_P_2) },
+ { "vpsrlq", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FD4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD4_P_2) },
+ { "vpaddq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD5_P_2) },
+ { "vpmullw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD8_P_2) },
+ { "vpsubusb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FD9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD9_P_2) },
+ { "vpsubusw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDA_P_2) },
+ { "vpminub", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDB_P_2) },
+ { "vpand", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDC_P_2) },
+ { "vpaddusb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDD_P_2) },
+ { "vpaddusw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDE_P_2) },
+ { "vpmaxub", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FDF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FDF_P_2) },
+ { "vpandn", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE0_P_2) },
+ { "vpavgb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE1 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE1_P_2) },
+ { "vpsraw", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FE2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE2_P_2) },
+ { "vpsrad", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FE3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE3_P_2) },
+ { "vpavgw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE4_P_2) },
+ { "vpmulhuw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE5_P_2) },
+ { "vpmulhw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE6 */
{
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE6_P_1) },
- { VEX_W_TABLE (VEX_W_0FE6_P_2) },
- { VEX_W_TABLE (VEX_W_0FE6_P_3) },
+ { "vcvtdq2pd", { XM, EXxmmq }, 0 },
+ { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
+ { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
},
/* PREFIX_VEX_0FE7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE8_P_2) },
+ { "vpsubsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FE9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FE9_P_2) },
+ { "vpsubsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEA_P_2) },
+ { "vpminsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEB_P_2) },
+ { "vpor", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEC_P_2) },
+ { "vpaddsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FED */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FED_P_2) },
+ { "vpaddsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEE_P_2) },
+ { "vpmaxsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FEF */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FEF_P_2) },
+ { "vpxor", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF0 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF1_P_2) },
+ { "vpsllw", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FF2 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF2_P_2) },
+ { "vpslld", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FF3 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF3_P_2) },
+ { "vpsllq", { XM, Vex, EXxmm }, 0 },
},
/* PREFIX_VEX_0FF4 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF4_P_2) },
+ { "vpmuludq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF5 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF5_P_2) },
+ { "vpmaddwd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF6 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF6_P_2) },
+ { "vpsadbw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF7 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF8_P_2) },
+ { "vpsubb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FF9 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FF9_P_2) },
+ { "vpsubw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFA */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFA_P_2) },
+ { "vpsubd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFB */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFB_P_2) },
+ { "vpsubq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFC */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFC_P_2) },
+ { "vpaddb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFD */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFD_P_2) },
+ { "vpaddw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0FFE */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FFE_P_2) },
+ { "vpaddd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3800 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3800_P_2) },
+ { "vpshufb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3801 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3801_P_2) },
+ { "vphaddw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3802 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3802_P_2) },
+ { "vphaddd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3803 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3803_P_2) },
+ { "vphaddsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3804 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3804_P_2) },
+ { "vpmaddubsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3805 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3805_P_2) },
+ { "vphsubw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3806 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3806_P_2) },
+ { "vphsubd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3807 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3807_P_2) },
+ { "vphsubsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3808 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3808_P_2) },
+ { "vpsignb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3809 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3809_P_2) },
+ { "vpsignw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F380A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380A_P_2) },
+ { "vpsignd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F380B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F380B_P_2) },
+ { "vpmulhrsw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F380C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3817_P_2) },
+ { "vptest", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F3818 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381C_P_2) },
+ { "vpabsb", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F381D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381D_P_2) },
+ { "vpabsw", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F381E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F381E_P_2) },
+ { "vpabsd", { XM, EXx }, 0 },
},
/* PREFIX_VEX_0F3820 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3820_P_2) },
+ { "vpmovsxbw", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3821 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3821_P_2) },
+ { "vpmovsxbd", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3822 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3822_P_2) },
+ { "vpmovsxbq", { XM, EXxmmdw }, 0 },
},
/* PREFIX_VEX_0F3823 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3823_P_2) },
+ { "vpmovsxwd", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3824 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3824_P_2) },
+ { "vpmovsxwq", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3825 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3825_P_2) },
+ { "vpmovsxdq", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3828 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3828_P_2) },
+ { "vpmuldq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3829 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3829_P_2) },
+ { "vpcmpeqq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F382A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F382B_P_2) },
+ { "vpackusdw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F382C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3830_P_2) },
+ { "vpmovzxbw", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3831 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3831_P_2) },
+ { "vpmovzxbd", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3832 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3832_P_2) },
+ { "vpmovzxbq", { XM, EXxmmdw }, 0 },
},
/* PREFIX_VEX_0F3833 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3833_P_2) },
+ { "vpmovzxwd", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3834 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3834_P_2) },
+ { "vpmovzxwq", { XM, EXxmmqd }, 0 },
},
/* PREFIX_VEX_0F3835 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3835_P_2) },
+ { "vpmovzxdq", { XM, EXxmmq }, 0 },
},
/* PREFIX_VEX_0F3836 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3837_P_2) },
+ { "vpcmpgtq", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3838 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3838_P_2) },
+ { "vpminsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3839 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3839_P_2) },
+ { "vpminsd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383A_P_2) },
+ { "vpminuw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383B_P_2) },
+ { "vpminud", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383C_P_2) },
+ { "vpmaxsb", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383D_P_2) },
+ { "vpmaxsd", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383E_P_2) },
+ { "vpmaxuw", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F383F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F383F_P_2) },
+ { "vpmaxud", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3840 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3840_P_2) },
+ { "vpmulld", { XM, Vex, EXx }, 0 },
},
/* PREFIX_VEX_0F3841 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A08_P_2) },
+ { "vroundps", { XM, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A09 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A09_P_2) },
+ { "vroundpd", { XM, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0A */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0A_P_2) },
+ { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0B */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_LEN_TABLE (VEX_LEN_0F3A0B_P_2) },
+ { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0C */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0C_P_2) },
+ { "vblendps", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0D */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0D_P_2) },
+ { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0E */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0E_P_2) },
+ { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A0F */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A0F_P_2) },
+ { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A14 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A40_P_2) },
+ { "vdpps", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A41 */
{
{ Bad_Opcode },
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F3A42_P_2) },
+ { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
},
/* PREFIX_VEX_0F3A44 */
{ VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) },
},
-#define NEED_PREFIX_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_PREFIX_TABLE
+#include "i386-dis-evex-prefix.h"
};
static const struct dis386 x86_64_table[][2] = {
{ "popP", { es }, 0 },
},
- /* X86_64_0D */
+ /* X86_64_0E */
{
{ "pushP", { cs }, 0 },
},
/* X86_64_63 */
{
{ "arpl", { Ew, Gw }, 0 },
- { "movs{lq|xd}", { Gv, Ed }, 0 },
+ { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 },
},
/* X86_64_6D */
/* X86_64_9A */
{
- { "Jcall{T|}", { Ap }, 0 },
+ { "{l|}call{T|}", { Ap }, 0 },
+ },
+
+ /* X86_64_C2 */
+ {
+ { "retP", { Iw, BND }, 0 },
+ { "ret@", { Iw, BND }, 0 },
+ },
+
+ /* X86_64_C3 */
+ {
+ { "retP", { BND }, 0 },
+ { "ret@", { BND }, 0 },
},
/* X86_64_C4 */
/* X86_64_EA */
{
- { "Jjmp{T|}", { Ap }, 0 },
+ { "{l|}jmp{T|}", { Ap }, 0 },
},
/* X86_64_0F01_REG_0 */
{ PREFIX_TABLE (PREFIX_0F38F6) },
{ Bad_Opcode },
/* f8 */
- { Bad_Opcode },
- { Bad_Opcode },
+ { PREFIX_TABLE (PREFIX_0F38F8) },
+ { PREFIX_TABLE (PREFIX_0F38F9) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
/* 10 */
- { "bextr", { Gv, Ev, Iq }, 0 },
+ { "bextrS", { Gdq, Edq, Id }, 0 },
{ Bad_Opcode },
{ REG_TABLE (REG_XOP_LWP) },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0F11) },
{ PREFIX_TABLE (PREFIX_VEX_0F12) },
{ MOD_TABLE (MOD_VEX_0F13) },
- { VEX_W_TABLE (VEX_W_0F14) },
- { VEX_W_TABLE (VEX_W_0F15) },
+ { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F16) },
{ MOD_TABLE (MOD_VEX_0F17) },
/* 18 */
{ Bad_Opcode },
{ Bad_Opcode },
/* 28 */
- { VEX_W_TABLE (VEX_W_0F28) },
- { VEX_W_TABLE (VEX_W_0F29) },
+ { "vmovapX", { XM, EXx }, PREFIX_OPCODE },
+ { "vmovapX", { EXxS, XM }, PREFIX_OPCODE },
{ PREFIX_TABLE (PREFIX_VEX_0F2A) },
{ MOD_TABLE (MOD_VEX_0F2B) },
{ PREFIX_TABLE (PREFIX_VEX_0F2C) },
{ PREFIX_TABLE (PREFIX_VEX_0F51) },
{ PREFIX_TABLE (PREFIX_VEX_0F52) },
{ PREFIX_TABLE (PREFIX_VEX_0F53) },
- { "vandpX", { XM, Vex, EXx }, 0 },
- { "vandnpX", { XM, Vex, EXx }, 0 },
- { "vorpX", { XM, Vex, EXx }, 0 },
- { "vxorpX", { XM, Vex, EXx }, 0 },
+ { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
+ { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE },
/* 58 */
{ PREFIX_TABLE (PREFIX_VEX_0F58) },
{ PREFIX_TABLE (PREFIX_VEX_0F59) },
{ Bad_Opcode },
{ PREFIX_TABLE (PREFIX_VEX_0FC4) },
{ PREFIX_TABLE (PREFIX_VEX_0FC5) },
- { "vshufpX", { XM, Vex, EXx, Ib }, 0 },
+ { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
{ Bad_Opcode },
/* c8 */
{ Bad_Opcode },
},
};
-#define NEED_OPCODE_TABLE
#include "i386-dis-evex.h"
-#undef NEED_OPCODE_TABLE
-static const struct dis386 vex_len_table[][2] = {
- /* VEX_LEN_0F10_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F10_P_1) },
- { VEX_W_TABLE (VEX_W_0F10_P_1) },
- },
-
- /* VEX_LEN_0F10_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F10_P_3) },
- { VEX_W_TABLE (VEX_W_0F10_P_3) },
- },
-
- /* VEX_LEN_0F11_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F11_P_1) },
- { VEX_W_TABLE (VEX_W_0F11_P_1) },
- },
-
- /* VEX_LEN_0F11_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F11_P_3) },
- { VEX_W_TABLE (VEX_W_0F11_P_3) },
- },
- /* VEX_LEN_0F12_P_0_M_0 */
+static const struct dis386 vex_len_table[][2] = {
+ /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_0_M_0) },
+ { "vmovlpX", { XM, Vex128, EXq }, 0 },
},
/* VEX_LEN_0F12_P_0_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F12_P_0_M_1) },
- },
-
- /* VEX_LEN_0F12_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F12_P_2) },
+ { "vmovhlps", { XM, Vex128, EXq }, 0 },
},
/* VEX_LEN_0F13_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F13_M_0) },
+ { "vmovlpX", { EXq, XM }, PREFIX_OPCODE },
},
- /* VEX_LEN_0F16_P_0_M_0 */
+ /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_0_M_0) },
+ { "vmovhpX", { XM, Vex128, EXq }, 0 },
},
/* VEX_LEN_0F16_P_0_M_1 */
{
- { VEX_W_TABLE (VEX_W_0F16_P_0_M_1) },
- },
-
- /* VEX_LEN_0F16_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F16_P_2) },
+ { "vmovlhps", { XM, Vex128, EXq }, 0 },
},
/* VEX_LEN_0F17_M_0 */
{
- { VEX_W_TABLE (VEX_W_0F17_M_0) },
- },
-
- /* VEX_LEN_0F2A_P_1 */
- {
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
- { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 },
- },
-
- /* VEX_LEN_0F2A_P_3 */
- {
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
- { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 },
- },
-
- /* VEX_LEN_0F2C_P_1 */
- {
- { "vcvttss2siY", { Gv, EXdScalar }, 0 },
- { "vcvttss2siY", { Gv, EXdScalar }, 0 },
- },
-
- /* VEX_LEN_0F2C_P_3 */
- {
- { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
- { "vcvttsd2siY", { Gv, EXqScalar }, 0 },
- },
-
- /* VEX_LEN_0F2D_P_1 */
- {
- { "vcvtss2siY", { Gv, EXdScalar }, 0 },
- { "vcvtss2siY", { Gv, EXdScalar }, 0 },
- },
-
- /* VEX_LEN_0F2D_P_3 */
- {
- { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
- { "vcvtsd2siY", { Gv, EXqScalar }, 0 },
- },
-
- /* VEX_LEN_0F2E_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F2E_P_0) },
- { VEX_W_TABLE (VEX_W_0F2E_P_0) },
- },
-
- /* VEX_LEN_0F2E_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F2E_P_2) },
- { VEX_W_TABLE (VEX_W_0F2E_P_2) },
- },
-
- /* VEX_LEN_0F2F_P_0 */
- {
- { VEX_W_TABLE (VEX_W_0F2F_P_0) },
- { VEX_W_TABLE (VEX_W_0F2F_P_0) },
- },
-
- /* VEX_LEN_0F2F_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F2F_P_2) },
- { VEX_W_TABLE (VEX_W_0F2F_P_2) },
+ { "vmovhpX", { EXq, XM }, PREFIX_OPCODE },
},
/* VEX_LEN_0F41_P_0 */
{ VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) },
},
- /* VEX_LEN_0F51_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F51_P_1) },
- { VEX_W_TABLE (VEX_W_0F51_P_1) },
- },
-
- /* VEX_LEN_0F51_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F51_P_3) },
- { VEX_W_TABLE (VEX_W_0F51_P_3) },
- },
-
- /* VEX_LEN_0F52_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F52_P_1) },
- { VEX_W_TABLE (VEX_W_0F52_P_1) },
- },
-
- /* VEX_LEN_0F53_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F53_P_1) },
- { VEX_W_TABLE (VEX_W_0F53_P_1) },
- },
-
- /* VEX_LEN_0F58_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F58_P_1) },
- { VEX_W_TABLE (VEX_W_0F58_P_1) },
- },
-
- /* VEX_LEN_0F58_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F58_P_3) },
- { VEX_W_TABLE (VEX_W_0F58_P_3) },
- },
-
- /* VEX_LEN_0F59_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F59_P_1) },
- { VEX_W_TABLE (VEX_W_0F59_P_1) },
- },
-
- /* VEX_LEN_0F59_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F59_P_3) },
- { VEX_W_TABLE (VEX_W_0F59_P_3) },
- },
-
- /* VEX_LEN_0F5A_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5A_P_1) },
- { VEX_W_TABLE (VEX_W_0F5A_P_1) },
- },
-
- /* VEX_LEN_0F5A_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5A_P_3) },
- { VEX_W_TABLE (VEX_W_0F5A_P_3) },
- },
-
- /* VEX_LEN_0F5C_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5C_P_1) },
- { VEX_W_TABLE (VEX_W_0F5C_P_1) },
- },
-
- /* VEX_LEN_0F5C_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5C_P_3) },
- { VEX_W_TABLE (VEX_W_0F5C_P_3) },
- },
-
- /* VEX_LEN_0F5D_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5D_P_1) },
- { VEX_W_TABLE (VEX_W_0F5D_P_1) },
- },
-
- /* VEX_LEN_0F5D_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5D_P_3) },
- { VEX_W_TABLE (VEX_W_0F5D_P_3) },
- },
-
- /* VEX_LEN_0F5E_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5E_P_1) },
- { VEX_W_TABLE (VEX_W_0F5E_P_1) },
- },
-
- /* VEX_LEN_0F5E_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0F5E_P_3) },
- { VEX_W_TABLE (VEX_W_0F5E_P_3) },
- },
-
- /* VEX_LEN_0F5F_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0F5F_P_1) },
- { VEX_W_TABLE (VEX_W_0F5F_P_1) },
- },
-
- /* VEX_LEN_0F5F_P_3 */
+ /* VEX_LEN_0F6E_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F5F_P_3) },
- { VEX_W_TABLE (VEX_W_0F5F_P_3) },
+ { "vmovK", { XMScalar, Edq }, 0 },
},
- /* VEX_LEN_0F6E_P_2 */
+ /* VEX_LEN_0F77_P_1 */
{
- { "vmovK", { XMScalar, Edq }, 0 },
- { "vmovK", { XMScalar, Edq }, 0 },
+ { "vzeroupper", { XX }, 0 },
+ { "vzeroall", { XX }, 0 },
},
/* VEX_LEN_0F7E_P_1 */
{
- { VEX_W_TABLE (VEX_W_0F7E_P_1) },
- { VEX_W_TABLE (VEX_W_0F7E_P_1) },
+ { "vmovq", { XMScalar, EXqScalar }, 0 },
},
/* VEX_LEN_0F7E_P_2 */
{
{ "vmovK", { Edq, XMScalar }, 0 },
- { "vmovK", { Edq, XMScalar }, 0 },
},
/* VEX_LEN_0F90_P_0 */
/* VEX_LEN_0F92_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F92_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) },
},
/* VEX_LEN_0F93_P_0 */
/* VEX_LEN_0F93_P_3 */
{
- { VEX_W_TABLE (VEX_W_0F93_P_3_LEN_0) },
+ { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) },
},
/* VEX_LEN_0F98_P_0 */
/* VEX_LEN_0FAE_R_2_M_0 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_2_M_0) },
+ { "vldmxcsr", { Md }, 0 },
},
/* VEX_LEN_0FAE_R_3_M_0 */
{
- { VEX_W_TABLE (VEX_W_0FAE_R_3_M_0) },
- },
-
- /* VEX_LEN_0FC2_P_1 */
- {
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- { VEX_W_TABLE (VEX_W_0FC2_P_1) },
- },
-
- /* VEX_LEN_0FC2_P_3 */
- {
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
- { VEX_W_TABLE (VEX_W_0FC2_P_3) },
+ { "vstmxcsr", { Md }, 0 },
},
/* VEX_LEN_0FC4_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FC4_P_2) },
+ { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
},
/* VEX_LEN_0FC5_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FC5_P_2) },
+ { "vpextrw", { Gdq, XS, Ib }, 0 },
},
/* VEX_LEN_0FD6_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FD6_P_2) },
- { VEX_W_TABLE (VEX_W_0FD6_P_2) },
+ { "vmovq", { EXqScalarS, XMScalar }, 0 },
},
/* VEX_LEN_0FF7_P_2 */
{
- { VEX_W_TABLE (VEX_W_0FF7_P_2) },
+ { "vmaskmovdqu", { XM, XS }, 0 },
},
/* VEX_LEN_0F3816_P_2 */
/* VEX_LEN_0F3841_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3841_P_2) },
+ { "vphminposuw", { XM, EXx }, 0 },
},
/* VEX_LEN_0F385A_P_2_M_0 */
/* VEX_LEN_0F38DB_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F38DB_P_2) },
+ { "vaesimc", { XM, EXx }, 0 },
},
/* VEX_LEN_0F38F2_P_0 */
{ VEX_W_TABLE (VEX_W_0F3A06_P_2) },
},
- /* VEX_LEN_0F3A0A_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0A_P_2) },
- },
-
- /* VEX_LEN_0F3A0B_P_2 */
- {
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- { VEX_W_TABLE (VEX_W_0F3A0B_P_2) },
- },
-
/* VEX_LEN_0F3A14_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A14_P_2) },
+ { "vpextrb", { Edqb, XM, Ib }, 0 },
},
/* VEX_LEN_0F3A15_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A15_P_2) },
+ { "vpextrw", { Edqw, XM, Ib }, 0 },
},
/* VEX_LEN_0F3A16_P_2 */
/* VEX_LEN_0F3A20_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A20_P_2) },
+ { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
},
/* VEX_LEN_0F3A21_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A21_P_2) },
+ { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
},
/* VEX_LEN_0F3A22_P_2 */
/* VEX_LEN_0F3A41_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A41_P_2) },
+ { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A46_P_2 */
/* VEX_LEN_0F3A62_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A62_P_2) },
+ { "vpcmpistrm", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A63_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3A63_P_2) },
+ { "vpcmpistri", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3A6A_P_2 */
/* VEX_LEN_0F3ADF_P_2 */
{
- { VEX_W_TABLE (VEX_W_0F3ADF_P_2) },
+ { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
},
/* VEX_LEN_0F3AF0_P_3 */
},
};
+#include "i386-dis-evex-len.h"
+
static const struct dis386 vex_w_table[][2] = {
- {
- /* VEX_W_0F10_P_0 */
- { "vmovups", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F10_P_1 */
- { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F10_P_2 */
- { "vmovupd", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F10_P_3 */
- { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F11_P_0 */
- { "vmovups", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F11_P_1 */
- { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 },
- },
- {
- /* VEX_W_0F11_P_2 */
- { "vmovupd", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F11_P_3 */
- { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 },
- },
- {
- /* VEX_W_0F12_P_0_M_0 */
- { "vmovlps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F12_P_0_M_1 */
- { "vmovhlps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F12_P_1 */
- { "vmovsldup", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F12_P_2 */
- { "vmovlpd", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F12_P_3 */
- { "vmovddup", { XM, EXymmq }, 0 },
- },
- {
- /* VEX_W_0F13_M_0 */
- { "vmovlpX", { EXq, XM }, 0 },
- },
- {
- /* VEX_W_0F14 */
- { "vunpcklpX", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F15 */
- { "vunpckhpX", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F16_P_0_M_0 */
- { "vmovhps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F16_P_0_M_1 */
- { "vmovlhps", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F16_P_1 */
- { "vmovshdup", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F16_P_2 */
- { "vmovhpd", { XM, Vex128, EXq }, 0 },
- },
- {
- /* VEX_W_0F17_M_0 */
- { "vmovhpX", { EXq, XM }, 0 },
- },
- {
- /* VEX_W_0F28 */
- { "vmovapX", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F29 */
- { "vmovapX", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F2B_M_0 */
- { "vmovntpX", { Mx, XM }, 0 },
- },
- {
- /* VEX_W_0F2E_P_0 */
- { "vucomiss", { XMScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F2E_P_2 */
- { "vucomisd", { XMScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F2F_P_0 */
- { "vcomiss", { XMScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F2F_P_2 */
- { "vcomisd", { XMScalar, EXqScalar }, 0 },
- },
{
/* VEX_W_0F41_P_0_LEN_1 */
{ MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) },
{ MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) },
},
{
- /* VEX_W_0F50_M_0 */
- { "vmovmskpX", { Gdq, XS }, 0 },
+ /* VEX_W_0F90_P_0_LEN_0 */
+ { "kmovw", { MaskG, MaskE }, 0 },
+ { "kmovq", { MaskG, MaskE }, 0 },
},
{
- /* VEX_W_0F51_P_0 */
- { "vsqrtps", { XM, EXx }, 0 },
+ /* VEX_W_0F90_P_2_LEN_0 */
+ { "kmovb", { MaskG, MaskBDE }, 0 },
+ { "kmovd", { MaskG, MaskBDE }, 0 },
},
{
- /* VEX_W_0F51_P_1 */
- { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F91_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
},
{
- /* VEX_W_0F51_P_2 */
- { "vsqrtpd", { XM, EXx }, 0 },
+ /* VEX_W_0F91_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
},
{
- /* VEX_W_0F51_P_3 */
- { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 },
+ /* VEX_W_0F92_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
},
{
- /* VEX_W_0F52_P_0 */
- { "vrsqrtps", { XM, EXx }, 0 },
+ /* VEX_W_0F92_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
},
{
- /* VEX_W_0F52_P_1 */
- { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F93_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
},
{
- /* VEX_W_0F53_P_0 */
- { "vrcpps", { XM, EXx }, 0 },
+ /* VEX_W_0F93_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
},
{
- /* VEX_W_0F53_P_1 */
- { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F98_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
},
{
- /* VEX_W_0F58_P_0 */
- { "vaddps", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F98_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
},
{
- /* VEX_W_0F58_P_1 */
- { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 },
+ /* VEX_W_0F99_P_0_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
},
{
- /* VEX_W_0F58_P_2 */
- { "vaddpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F58_P_3 */
- { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F59_P_0 */
- { "vmulps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F59_P_1 */
- { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F59_P_2 */
- { "vmulpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F59_P_3 */
- { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5A_P_0 */
- { "vcvtps2pd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F5A_P_1 */
- { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5A_P_3 */
- { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5B_P_0 */
- { "vcvtdq2ps", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F5B_P_1 */
- { "vcvttps2dq", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F5B_P_2 */
- { "vcvtps2dq", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F5C_P_0 */
- { "vsubps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5C_P_1 */
- { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5C_P_2 */
- { "vsubpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5C_P_3 */
- { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5D_P_0 */
- { "vminps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5D_P_1 */
- { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5D_P_2 */
- { "vminpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5D_P_3 */
- { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5E_P_0 */
- { "vdivps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5E_P_1 */
- { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5E_P_2 */
- { "vdivpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5E_P_3 */
- { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F5F_P_0 */
- { "vmaxps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5F_P_1 */
- { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 },
- },
- {
- /* VEX_W_0F5F_P_2 */
- { "vmaxpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F5F_P_3 */
- { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F60_P_2 */
- { "vpunpcklbw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F61_P_2 */
- { "vpunpcklwd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F62_P_2 */
- { "vpunpckldq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F63_P_2 */
- { "vpacksswb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F64_P_2 */
- { "vpcmpgtb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F65_P_2 */
- { "vpcmpgtw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F66_P_2 */
- { "vpcmpgtd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F67_P_2 */
- { "vpackuswb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F68_P_2 */
- { "vpunpckhbw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F69_P_2 */
- { "vpunpckhwd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6A_P_2 */
- { "vpunpckhdq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6B_P_2 */
- { "vpackssdw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6C_P_2 */
- { "vpunpcklqdq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6D_P_2 */
- { "vpunpckhqdq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F6F_P_1 */
- { "vmovdqu", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F6F_P_2 */
- { "vmovdqa", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F70_P_1 */
- { "vpshufhw", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F70_P_2 */
- { "vpshufd", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F70_P_3 */
- { "vpshuflw", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F71_R_2_P_2 */
- { "vpsrlw", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F71_R_4_P_2 */
- { "vpsraw", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F71_R_6_P_2 */
- { "vpsllw", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F72_R_2_P_2 */
- { "vpsrld", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F72_R_4_P_2 */
- { "vpsrad", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F72_R_6_P_2 */
- { "vpslld", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_2_P_2 */
- { "vpsrlq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_3_P_2 */
- { "vpsrldq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_6_P_2 */
- { "vpsllq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F73_R_7_P_2 */
- { "vpslldq", { Vex, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0F74_P_2 */
- { "vpcmpeqb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F75_P_2 */
- { "vpcmpeqw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F76_P_2 */
- { "vpcmpeqd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F77_P_0 */
- { "", { VZERO }, 0 },
- },
- {
- /* VEX_W_0F7C_P_2 */
- { "vhaddpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7C_P_3 */
- { "vhaddps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7D_P_2 */
- { "vhsubpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7D_P_3 */
- { "vhsubps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F7E_P_1 */
- { "vmovq", { XMScalar, EXqScalar }, 0 },
- },
- {
- /* VEX_W_0F7F_P_1 */
- { "vmovdqu", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F7F_P_2 */
- { "vmovdqa", { EXxS, XM }, 0 },
- },
- {
- /* VEX_W_0F90_P_0_LEN_0 */
- { "kmovw", { MaskG, MaskE }, 0 },
- { "kmovq", { MaskG, MaskE }, 0 },
- },
- {
- /* VEX_W_0F90_P_2_LEN_0 */
- { "kmovb", { MaskG, MaskBDE }, 0 },
- { "kmovd", { MaskG, MaskBDE }, 0 },
- },
- {
- /* VEX_W_0F91_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F91_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F92_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F92_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F92_P_3_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F92_P_3_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F92_P_3_LEN_0) },
- },
- {
- /* VEX_W_0F93_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F93_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F93_P_3_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F93_P_3_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F93_P_3_LEN_0) },
- },
- {
- /* VEX_W_0F98_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F98_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) },
- },
- {
- /* VEX_W_0F99_P_0_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) },
- },
- {
- /* VEX_W_0F99_P_2_LEN_0 */
- { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
- { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
- },
- {
- /* VEX_W_0FAE_R_2_M_0 */
- { "vldmxcsr", { Md }, 0 },
- },
- {
- /* VEX_W_0FAE_R_3_M_0 */
- { "vstmxcsr", { Md }, 0 },
- },
- {
- /* VEX_W_0FC2_P_0 */
- { "vcmpps", { XM, Vex, EXx, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC2_P_1 */
- { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC2_P_2 */
- { "vcmppd", { XM, Vex, EXx, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC2_P_3 */
- { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 },
- },
- {
- /* VEX_W_0FC4_P_2 */
- { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 },
- },
- {
- /* VEX_W_0FC5_P_2 */
- { "vpextrw", { Gdq, XS, Ib }, 0 },
- },
- {
- /* VEX_W_0FD0_P_2 */
- { "vaddsubpd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD0_P_3 */
- { "vaddsubps", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD1_P_2 */
- { "vpsrlw", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FD2_P_2 */
- { "vpsrld", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FD3_P_2 */
- { "vpsrlq", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FD4_P_2 */
- { "vpaddq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD5_P_2 */
- { "vpmullw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD6_P_2 */
- { "vmovq", { EXqScalarS, XMScalar }, 0 },
- },
- {
- /* VEX_W_0FD7_P_2_M_1 */
- { "vpmovmskb", { Gdq, XS }, 0 },
- },
- {
- /* VEX_W_0FD8_P_2 */
- { "vpsubusb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FD9_P_2 */
- { "vpsubusw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDA_P_2 */
- { "vpminub", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDB_P_2 */
- { "vpand", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDC_P_2 */
- { "vpaddusb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDD_P_2 */
- { "vpaddusw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDE_P_2 */
- { "vpmaxub", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FDF_P_2 */
- { "vpandn", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE0_P_2 */
- { "vpavgb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE1_P_2 */
- { "vpsraw", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FE2_P_2 */
- { "vpsrad", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FE3_P_2 */
- { "vpavgw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE4_P_2 */
- { "vpmulhuw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE5_P_2 */
- { "vpmulhw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE6_P_1 */
- { "vcvtdq2pd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0FE6_P_2 */
- { "vcvttpd2dq%XY", { XMM, EXx }, 0 },
- },
- {
- /* VEX_W_0FE6_P_3 */
- { "vcvtpd2dq%XY", { XMM, EXx }, 0 },
- },
- {
- /* VEX_W_0FE7_P_2_M_0 */
- { "vmovntdq", { Mx, XM }, 0 },
- },
- {
- /* VEX_W_0FE8_P_2 */
- { "vpsubsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FE9_P_2 */
- { "vpsubsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEA_P_2 */
- { "vpminsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEB_P_2 */
- { "vpor", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEC_P_2 */
- { "vpaddsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FED_P_2 */
- { "vpaddsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEE_P_2 */
- { "vpmaxsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FEF_P_2 */
- { "vpxor", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FF0_P_3_M_0 */
- { "vlddqu", { XM, M }, 0 },
- },
- {
- /* VEX_W_0FF1_P_2 */
- { "vpsllw", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FF2_P_2 */
- { "vpslld", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FF3_P_2 */
- { "vpsllq", { XM, Vex, EXxmm }, 0 },
- },
- {
- /* VEX_W_0FF4_P_2 */
- { "vpmuludq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FF5_P_2 */
- { "vpmaddwd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FF6_P_2 */
- { "vpsadbw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FF7_P_2 */
- { "vmaskmovdqu", { XM, XS }, 0 },
- },
- {
- /* VEX_W_0FF8_P_2 */
- { "vpsubb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FF9_P_2 */
- { "vpsubw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FFA_P_2 */
- { "vpsubd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FFB_P_2 */
- { "vpsubq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FFC_P_2 */
- { "vpaddb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FFD_P_2 */
- { "vpaddw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0FFE_P_2 */
- { "vpaddd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3800_P_2 */
- { "vpshufb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3801_P_2 */
- { "vphaddw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3802_P_2 */
- { "vphaddd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3803_P_2 */
- { "vphaddsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3804_P_2 */
- { "vpmaddubsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3805_P_2 */
- { "vphsubw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3806_P_2 */
- { "vphsubd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3807_P_2 */
- { "vphsubsw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3808_P_2 */
- { "vpsignb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3809_P_2 */
- { "vpsignw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F380A_P_2 */
- { "vpsignd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F380B_P_2 */
- { "vpmulhrsw", { XM, Vex, EXx }, 0 },
+ /* VEX_W_0F99_P_2_LEN_0 */
+ { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) },
+ { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) },
},
{
/* VEX_W_0F380C_P_2 */
/* VEX_W_0F3816_P_2 */
{ "vpermps", { XM, Vex, EXx }, 0 },
},
- {
- /* VEX_W_0F3817_P_2 */
- { "vptest", { XM, EXx }, 0 },
- },
{
/* VEX_W_0F3818_P_2 */
{ "vbroadcastss", { XM, EXxmm_md }, 0 },
/* VEX_W_0F381A_P_2_M_0 */
{ "vbroadcastf128", { XM, Mxmm }, 0 },
},
- {
- /* VEX_W_0F381C_P_2 */
- { "vpabsb", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F381D_P_2 */
- { "vpabsw", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F381E_P_2 */
- { "vpabsd", { XM, EXx }, 0 },
- },
- {
- /* VEX_W_0F3820_P_2 */
- { "vpmovsxbw", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3821_P_2 */
- { "vpmovsxbd", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3822_P_2 */
- { "vpmovsxbq", { XM, EXxmmdw }, 0 },
- },
- {
- /* VEX_W_0F3823_P_2 */
- { "vpmovsxwd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3824_P_2 */
- { "vpmovsxwq", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3825_P_2 */
- { "vpmovsxdq", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3828_P_2 */
- { "vpmuldq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3829_P_2 */
- { "vpcmpeqq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F382A_P_2_M_0 */
- { "vmovntdqa", { XM, Mx }, 0 },
- },
- {
- /* VEX_W_0F382B_P_2 */
- { "vpackusdw", { XM, Vex, EXx }, 0 },
- },
{
/* VEX_W_0F382C_P_2_M_0 */
{ "vmaskmovps", { XM, Vex, Mx }, 0 },
/* VEX_W_0F382F_P_2_M_0 */
{ "vmaskmovpd", { Mx, Vex, XM }, 0 },
},
- {
- /* VEX_W_0F3830_P_2 */
- { "vpmovzxbw", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3831_P_2 */
- { "vpmovzxbd", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3832_P_2 */
- { "vpmovzxbq", { XM, EXxmmdw }, 0 },
- },
- {
- /* VEX_W_0F3833_P_2 */
- { "vpmovzxwd", { XM, EXxmmq }, 0 },
- },
- {
- /* VEX_W_0F3834_P_2 */
- { "vpmovzxwq", { XM, EXxmmqd }, 0 },
- },
- {
- /* VEX_W_0F3835_P_2 */
- { "vpmovzxdq", { XM, EXxmmq }, 0 },
- },
{
/* VEX_W_0F3836_P_2 */
{ "vpermd", { XM, Vex, EXx }, 0 },
},
- {
- /* VEX_W_0F3837_P_2 */
- { "vpcmpgtq", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3838_P_2 */
- { "vpminsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3839_P_2 */
- { "vpminsd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383A_P_2 */
- { "vpminuw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383B_P_2 */
- { "vpminud", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383C_P_2 */
- { "vpmaxsb", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383D_P_2 */
- { "vpmaxsd", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383E_P_2 */
- { "vpmaxuw", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F383F_P_2 */
- { "vpmaxud", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3840_P_2 */
- { "vpmulld", { XM, Vex, EXx }, 0 },
- },
- {
- /* VEX_W_0F3841_P_2 */
- { "vphminposuw", { XM, EXx }, 0 },
- },
{
/* VEX_W_0F3846_P_2 */
{ "vpsravd", { XM, Vex, EXx }, 0 },
/* VEX_W_0F38CF_P_2 */
{ "vgf2p8mulb", { XM, Vex, EXx }, 0 },
},
- {
- /* VEX_W_0F38DB_P_2 */
- { "vaesimc", { XM, EXx }, 0 },
- },
{
/* VEX_W_0F3A00_P_2 */
{ Bad_Opcode },
/* VEX_W_0F3A06_P_2 */
{ "vperm2f128", { XM, Vex256, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3A08_P_2 */
- { "vroundps", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A09_P_2 */
- { "vroundpd", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0A_P_2 */
- { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0B_P_2 */
- { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0C_P_2 */
- { "vblendps", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0D_P_2 */
- { "vblendpd", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0E_P_2 */
- { "vpblendw", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A0F_P_2 */
- { "vpalignr", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A14_P_2 */
- { "vpextrb", { Edqb, XM, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A15_P_2 */
- { "vpextrw", { Edqw, XM, Ib }, 0 },
- },
{
/* VEX_W_0F3A18_P_2 */
{ "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 },
/* VEX_W_0F3A19_P_2 */
{ "vextractf128", { EXxmm, XM, Ib }, 0 },
},
- {
- /* VEX_W_0F3A20_P_2 */
- { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A21_P_2 */
- { "vinsertps", { XM, Vex128, EXd, Ib }, 0 },
- },
{
/* VEX_W_0F3A30_P_2_LEN_0 */
{ MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) },
/* VEX_W_0F3A39_P_2 */
{ "vextracti128", { EXxmm, XM, Ib }, 0 },
},
- {
- /* VEX_W_0F3A40_P_2 */
- { "vdpps", { XM, Vex, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A41_P_2 */
- { "vdppd", { XM, Vex128, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A42_P_2 */
- { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 },
- },
{
/* VEX_W_0F3A46_P_2 */
{ "vperm2i128", { XM, Vex256, EXx, Ib }, 0 },
/* VEX_W_0F3A4C_P_2 */
{ "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 },
},
- {
- /* VEX_W_0F3A62_P_2 */
- { "vpcmpistrm", { XM, EXx, Ib }, 0 },
- },
- {
- /* VEX_W_0F3A63_P_2 */
- { "vpcmpistri", { XM, EXx, Ib }, 0 },
- },
{
/* VEX_W_0F3ACE_P_2 */
{ Bad_Opcode },
{ Bad_Opcode },
{ "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 },
},
- {
- /* VEX_W_0F3ADF_P_2 */
- { "vaeskeygenassist", { XM, EXx, Ib }, 0 },
- },
-#define NEED_VEX_W_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_VEX_W_TABLE
+
+#include "i386-dis-evex-w.h"
};
static const struct dis386 mod_table[][2] = {
},
{
/* MOD_FF_REG_3 */
- { "Jcall^", { indirEp }, 0 },
+ { "{l|}call^", { indirEp }, 0 },
},
{
/* MOD_FF_REG_5 */
- { "Jjmp^", { indirEp }, 0 },
+ { "{l|}jmp^", { indirEp }, 0 },
},
{
/* MOD_0F01_REG_0 */
},
{
/* MOD_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) },
- { RM_TABLE (RM_0F01_REG_5) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
+ { RM_TABLE (RM_0F01_REG_5_MOD_3) },
},
{
/* MOD_0F01_REG_7 */
{ "invlpg", { Mb }, 0 },
- { RM_TABLE (RM_0F01_REG_7) },
+ { RM_TABLE (RM_0F01_REG_7_MOD_3) },
},
{
/* MOD_0F12_PREFIX_0 */
- { "movlps", { XM, EXq }, PREFIX_OPCODE },
- { "movhlps", { XM, EXq }, PREFIX_OPCODE },
+ { "movlpX", { XM, EXq }, 0 },
+ { "movhlps", { XM, EXq }, 0 },
+ },
+ {
+ /* MOD_0F12_PREFIX_2 */
+ { "movlpX", { XM, EXq }, 0 },
},
{
/* MOD_0F13 */
},
{
/* MOD_0F16_PREFIX_0 */
- { "movhps", { XM, EXq }, 0 },
+ { "movhpX", { XM, EXq }, 0 },
{ "movlhps", { XM, EXq }, 0 },
},
+ {
+ /* MOD_0F16_PREFIX_2 */
+ { "movhpX", { XM, EXq }, 0 },
+ },
{
/* MOD_0F17 */
{ "movhpX", { EXq, XM }, PREFIX_OPCODE },
},
{
/* MOD_0F1A_PREFIX_0 */
- { "bndldx", { Gbnd, Ev_bnd }, 0 },
+ { "bndldx", { Gbnd, Mv_bnd }, 0 },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1B_PREFIX_0 */
- { "bndstx", { Ev_bnd, Gbnd }, 0 },
+ { "bndstx", { Mv_bnd, Gbnd }, 0 },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1B_PREFIX_1 */
- { "bndmk", { Gbnd, Ev_bnd }, 0 },
+ { "bndmk", { Gbnd, Mv_bnd }, 0 },
+ { "nopQ", { Ev }, 0 },
+ },
+ {
+ /* MOD_0F1C_PREFIX_0 */
+ { REG_TABLE (REG_0F1C_P_0_MOD_0) },
{ "nopQ", { Ev }, 0 },
},
{
/* MOD_0F1E_PREFIX_1 */
{ "nopQ", { Ev }, 0 },
- { REG_TABLE (REG_0F1E_MOD_3) },
+ { REG_TABLE (REG_0F1E_P_1_MOD_3) },
},
{
/* MOD_0F24 */
{"movntsd", { Mq, XM }, PREFIX_OPCODE },
},
{
- /* MOD_0F51 */
+ /* MOD_0F50 */
{ Bad_Opcode },
{ "movmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
/* MOD_0FAE_REG_0 */
{ "fxsave", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
},
{
/* MOD_0FAE_REG_1 */
{ "fxrstor", { FXSAVE }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_1) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
},
{
/* MOD_0FAE_REG_2 */
{ "ldmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_2) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
},
{
/* MOD_0FAE_REG_3 */
{ "stmxcsr", { Md }, 0 },
- { PREFIX_TABLE (PREFIX_0FAE_REG_3) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
},
{
/* MOD_0FAE_REG_4 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
},
{
/* MOD_0FAE_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
},
{
/* MOD_0FAE_REG_6 */
- { PREFIX_TABLE (PREFIX_0FAE_REG_6) },
- { RM_TABLE (RM_0FAE_REG_6) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
},
{
/* MOD_0FAE_REG_7 */
- { PREFIX_TABLE (PREFIX_0FAE_REG_7) },
- { RM_TABLE (RM_0FAE_REG_7) },
+ { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
+ { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
},
{
/* MOD_0FB2 */
},
{
/* MOD_0FC3 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC3) },
+ { PREFIX_TABLE (PREFIX_0FC3_MOD_0) },
},
{
/* MOD_0FC7_REG_3 */
},
{
/* MOD_0FC7_REG_6 */
- { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) }
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
+ { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
},
{
/* MOD_0FC7_REG_7 */
{ "vmptrst", { Mq }, 0 },
- { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) }
+ { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
},
{
/* MOD_0FD7 */
/* MOD_0F38F6_PREFIX_0 */
{ "wrssK", { M, Gdq }, PREFIX_OPCODE },
},
+ {
+ /* MOD_0F38F8_PREFIX_1 */
+ { "enqcmds", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F8_PREFIX_2 */
+ { "movdir64b", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F8_PREFIX_3 */
+ { "enqcmd", { Gva, M }, PREFIX_OPCODE },
+ },
+ {
+ /* MOD_0F38F9_PREFIX_0 */
+ { "movdiri", { Ev, Gv }, PREFIX_OPCODE },
+ },
{
/* MOD_62_32BIT */
{ "bound{S|}", { Gv, Ma }, 0 },
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) },
},
+ {
+ /* MOD_VEX_0F12_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) },
+ },
{
/* MOD_VEX_0F13 */
{ VEX_LEN_TABLE (VEX_LEN_0F13_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) },
{ VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) },
},
+ {
+ /* MOD_VEX_0F16_PREFIX_2 */
+ { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) },
+ },
{
/* MOD_VEX_0F17 */
{ VEX_LEN_TABLE (VEX_LEN_0F17_M_0) },
},
{
/* MOD_VEX_0F2B */
- { VEX_W_TABLE (VEX_W_0F2B_M_0) },
+ { "vmovntpX", { Mx, XM }, PREFIX_OPCODE },
},
{
/* MOD_VEX_W_0_0F41_P_0_LEN_1 */
{
/* MOD_VEX_0F50 */
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0F50_M_0) },
+ { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE },
},
{
/* MOD_VEX_0F71_REG_2 */
{ "kmovb", { MaskG, Rdq }, 0 },
},
{
- /* MOD_VEX_W_0_0F92_P_3_LEN_0 */
+ /* MOD_VEX_0F92_P_3_LEN_0 */
{ Bad_Opcode },
- { "kmovd", { MaskG, Rdq }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F92_P_3_LEN_0 */
- { Bad_Opcode },
- { "kmovq", { MaskG, Rdq }, 0 },
+ { "kmovK", { MaskG, Rdq }, 0 },
},
{
/* MOD_VEX_W_0_0F93_P_0_LEN_0 */
{ "kmovb", { Gdq, MaskR }, 0 },
},
{
- /* MOD_VEX_W_0_0F93_P_3_LEN_0 */
- { Bad_Opcode },
- { "kmovd", { Gdq, MaskR }, 0 },
- },
- {
- /* MOD_VEX_W_1_0F93_P_3_LEN_0 */
+ /* MOD_VEX_0F93_P_3_LEN_0 */
{ Bad_Opcode },
- { "kmovq", { Gdq, MaskR }, 0 },
+ { "kmovK", { Gdq, MaskR }, 0 },
},
{
/* MOD_VEX_W_0_0F98_P_0_LEN_0 */
{
/* MOD_VEX_0FD7_PREFIX_2 */
{ Bad_Opcode },
- { VEX_W_TABLE (VEX_W_0FD7_P_2_M_1) },
+ { "vpmovmskb", { Gdq, XS }, 0 },
},
{
/* MOD_VEX_0FE7_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0FE7_P_2_M_0) },
+ { "vmovntdq", { Mx, XM }, 0 },
},
{
/* MOD_VEX_0FF0_PREFIX_3 */
- { VEX_W_TABLE (VEX_W_0FF0_P_3_M_0) },
+ { "vlddqu", { XM, M }, 0 },
},
{
/* MOD_VEX_0F381A_PREFIX_2 */
},
{
/* MOD_VEX_0F382A_PREFIX_2 */
- { VEX_W_TABLE (VEX_W_0F382A_P_2_M_0) },
+ { "vmovntdqa", { XM, Mx }, 0 },
},
{
/* MOD_VEX_0F382C_PREFIX_2 */
{ Bad_Opcode },
{ "kshiftlq", { MaskG, MaskR, Ib }, 0 },
},
-#define NEED_MOD_TABLE
-#include "i386-dis-evex.h"
-#undef NEED_MOD_TABLE
+
+#include "i386-dis-evex-mod.h"
};
static const struct dis386 rm_table[][8] = {
},
{
/* RM_C7_REG_7 */
- { "xbeginT", { Skip_MODRM, Jv }, 0 },
+ { "xbeginT", { Skip_MODRM, Jdqw }, 0 },
},
{
/* RM_0F01_REG_0 */
- { Bad_Opcode },
+ { "enclv", { Skip_MODRM }, 0 },
{ "vmcall", { Skip_MODRM }, 0 },
{ "vmlaunch", { Skip_MODRM }, 0 },
{ "vmresume", { Skip_MODRM }, 0 },
{ "vmxoff", { Skip_MODRM }, 0 },
+ { "pconfig", { Skip_MODRM }, 0 },
},
{
/* RM_0F01_REG_1 */
{
/* RM_0F01_REG_3 */
{ "vmrun", { Skip_MODRM }, 0 },
- { "vmmcall", { Skip_MODRM }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
{ "vmload", { Skip_MODRM }, 0 },
{ "vmsave", { Skip_MODRM }, 0 },
{ "stgi", { Skip_MODRM }, 0 },
{ "invlpga", { Skip_MODRM }, 0 },
},
{
- /* RM_0F01_REG_5 */
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) },
- { Bad_Opcode },
- { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) },
+ /* RM_0F01_REG_5_MOD_3 */
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
{ Bad_Opcode },
{ Bad_Opcode },
{ Bad_Opcode },
{ "wrpkru", { Skip_MODRM }, 0 },
},
{
- /* RM_0F01_REG_7 */
+ /* RM_0F01_REG_7_MOD_3 */
{ "swapgs", { Skip_MODRM }, 0 },
{ "rdtscp", { Skip_MODRM }, 0 },
- { "monitorx", { { OP_Monitor, 0 } }, 0 },
- { "mwaitx", { { OP_Mwaitx, 0 } }, 0 },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
+ { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) },
{ "clzero", { Skip_MODRM }, 0 },
+ { "rdpru", { Skip_MODRM }, 0 },
},
{
- /* RM_0F1E_MOD_3_REG_7 */
+ /* RM_0F1E_P_1_MOD_3_REG_7 */
{ "nopQ", { Ev }, 0 },
{ "nopQ", { Ev }, 0 },
{ "endbr64", { Skip_MODRM }, PREFIX_OPCODE },
{ "nopQ", { Ev }, 0 },
},
{
- /* RM_0FAE_REG_6 */
+ /* RM_0FAE_REG_6_MOD_3 */
{ "mfence", { Skip_MODRM }, 0 },
},
{
- /* RM_0FAE_REG_7 */
+ /* RM_0FAE_REG_7_MOD_3 */
{ "sfence", { Skip_MODRM }, 0 },
},
#define BND_PREFIX (0xf2 | 0x400)
#define NOTRACK_PREFIX (0x3e | 0x100)
+/* Remember if the current op is a jump instruction. */
+static bfd_boolean op_is_jump = FALSE;
+
static int
ckprefix (void)
{
int newrex, i, length;
rex = 0;
- rex_ignored = 0;
prefixes = 0;
used_prefixes = 0;
rex_used = 0;
enum x86_64_isa
{
- amd64 = 0,
+ amd64 = 1,
intel64
};
dp = &vex_len_table[dp->op[1].bytemode][vindex];
break;
+ case USE_EVEX_LEN_TABLE:
+ if (!vex.evex)
+ abort ();
+
+ switch (vex.length)
+ {
+ case 128:
+ vindex = 0;
+ break;
+ case 256:
+ vindex = 1;
+ break;
+ case 512:
+ vindex = 2;
+ break;
+ default:
+ abort ();
+ break;
+ }
+
+ dp = &evex_len_table[dp->op[1].bytemode][vindex];
+ break;
+
case USE_XOP_8F_TABLE:
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
/* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */
{
/* In 16/32-bit mode REX_B is silently ignored. */
rex &= ~REX_B;
- if (vex.register_specifier > 0x7)
- {
- dp = &bad_opcode;
- return dp;
- }
}
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
case USE_VEX_C4_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 3);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = ~(*codep >> 5) & 0x7;
switch ((*codep & 0x1f))
{
{
if (vex.w)
rex |= REX_W;
- vex.register_specifier = (~(*codep >> 3)) & 0xf;
}
else
{
/* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
is ignored, other REX bits are 0 and the highest bit in
- VEX.vvvv is also ignored. */
+ VEX.vvvv is also ignored (but we mustn't clear it here). */
rex = 0;
- vex.register_specifier = (~(*codep >> 3)) & 0x7;
}
+ vex.register_specifier = (~(*codep >> 3)) & 0xf;
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
case USE_VEX_C5_TABLE:
/* VEX prefix. */
FETCH_DATA (info, codep + 2);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
rex = (*codep & 0x80) ? 0 : REX_R;
/* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
VEX.vvvv is 1. */
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- vex.w = 0;
vex.length = (*codep & 0x4) ? 256 : 128;
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
/* EVEX prefix. */
vex.evex = 1;
FETCH_DATA (info, codep + 4);
- /* All bits in the REX prefix are ignored. */
- rex_ignored = rex;
/* The first byte after 0x62. */
rex = ~(*codep >> 5) & 0x7;
vex.r = *codep & 0x10;
rex |= REX_W;
vex.register_specifier = (~(*codep >> 3)) & 0xf;
- if (address_mode != mode_64bit)
- {
- /* In 16/32-bit mode silently ignore following bits. */
- rex &= ~REX_B;
- vex.r = 1;
- vex.v = 1;
- vex.register_specifier &= 0x7;
- }
/* The U bit. */
if (!(*codep & 0x4))
switch ((*codep & 0x3))
{
case 0:
- vex.prefix = 0;
break;
case 1:
vex.prefix = DATA_PREFIX_OPCODE;
vex.mask_register_specifier = *codep & 0x7;
vex.zeroing = *codep & 0x80;
+ if (address_mode != mode_64bit)
+ {
+ /* In 16/32-bit mode silently ignore following bits. */
+ rex &= ~REX_B;
+ vex.r = 1;
+ vex.v = 1;
+ }
+
need_vex = 1;
need_vex_reg = 1;
codep++;
else if (CONST_STRNEQ (p, "x86-64"))
{
address_mode = mode_64bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
else if (CONST_STRNEQ (p, "i386"))
{
address_mode = mode_32bit;
- priv.orig_sizeflag = AFLAG | DFLAG;
+ priv.orig_sizeflag |= AFLAG | DFLAG;
}
else if (CONST_STRNEQ (p, "i8086"))
{
address_mode = mode_16bit;
- priv.orig_sizeflag = 0;
+ priv.orig_sizeflag &= ~(AFLAG | DFLAG);
}
else if (CONST_STRNEQ (p, "intel"))
{
need_vex = 0;
need_vex_reg = 0;
vex_w_done = 0;
- vex.evex = 0;
+ memset (&vex, 0, sizeof (vex));
if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
{
}
}
+ /* Clear instruction information. */
+ if (the_info)
+ {
+ the_info->insn_info_valid = 0;
+ the_info->branch_delay_insns = 0;
+ the_info->data_size = 0;
+ the_info->insn_type = dis_noninsn;
+ the_info->target = 0;
+ the_info->target2 = 0;
+ }
+
+ /* Reset jump operation indicator. */
+ op_is_jump = FALSE;
+
+ {
+ int jump_detection = 0;
+
+ /* Extract flags. */
+ for (i = 0; i < MAX_OPERANDS; ++i)
+ {
+ if ((dp->op[i].rtn == OP_J)
+ || (dp->op[i].rtn == OP_indirE))
+ jump_detection |= 1;
+ else if ((dp->op[i].rtn == BND_Fixup)
+ || (!dp->op[i].rtn && !dp->op[i].bytemode))
+ jump_detection |= 2;
+ else if ((dp->op[i].bytemode == cond_jump_mode)
+ || (dp->op[i].bytemode == loop_jcxz_mode))
+ jump_detection |= 4;
+ }
+
+ /* Determine if this is a jump or branch. */
+ if ((jump_detection & 0x3) == 0x3)
+ {
+ op_is_jump = TRUE;
+ if (jump_detection & 0x4)
+ the_info->insn_type = dis_condbranch;
+ else
+ the_info->insn_type =
+ (dp->name && !strncmp(dp->name, "call", 4))
+ ? dis_jsr : dis_branch;
+ }
+ }
+
+ /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
+ are all 0s in inverted form. */
+ if (need_vex && vex.register_specifier != 0)
+ {
+ (*info->fprintf_func) (info->stream, "(bad)");
+ return end_codep - priv.the_buffer;
+ }
+
/* Check if the REX prefix is used. */
- if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0)
+ if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0)
all_prefixes[last_rex_prefix] = 0;
/* Check if the SEG prefix is used. */
/* Check if the DATA prefix is used. */
if ((prefixes & PREFIX_DATA) != 0
- && (used_prefixes & PREFIX_DATA) != 0)
+ && (used_prefixes & PREFIX_DATA) != 0
+ && !need_vex)
all_prefixes[last_data_prefix] = 0;
/* Print the extra prefixes. */
PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
separately. */
if (dp->prefix_requirement == PREFIX_OPCODE
- && dp != &bad_opcode
- && (((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ)) != 0
+ && (((need_vex
+ ? vex.prefix == REPE_PREFIX_OPCODE
+ || vex.prefix == REPNE_PREFIX_OPCODE
+ : (prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
&& (used_prefixes
& (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
- || ((((prefixes
- & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
- == PREFIX_DATA)
- && (used_prefixes & PREFIX_DATA) == 0))))
+ || (((need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : ((prefixes
+ & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
+ == PREFIX_DATA))
+ && (used_prefixes & PREFIX_DATA) == 0))
+ || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA))))
{
(*info->fprintf_func) (info->stream, "(bad)");
return end_codep - priv.the_buffer;
if (needcomma)
(*info->fprintf_func) (info->stream, ",");
if (op_index[i] != -1 && !op_riprel[i])
- (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info);
+ {
+ bfd_vma target = (bfd_vma) op_address[op_index[i]];
+
+ if (the_info && op_is_jump)
+ {
+ the_info->insn_info_valid = 1;
+ the_info->branch_delay_insns = 0;
+ the_info->data_size = 0;
+ the_info->target = target;
+ the_info->target2 = 0;
+ }
+ (*info->print_address_func) (target, info);
+ }
else
(*info->fprintf_func) (info->stream, "%s", op_txt[i]);
needcomma = 1;
"fist{l|}",
"fistp{l|}",
"(bad)",
- "fld{t||t|}",
+ "fld{t|}",
"(bad)",
- "fstp{t||t|}",
+ "fstp{t|}",
/* dc */
"fadd{l|}",
"fmul{l|}",
"fNsaveIC",
"fNstsw",
/* de */
- "fiadd",
- "fimul",
- "ficom",
- "ficomp",
- "fisub",
- "fisubr",
- "fidiv",
- "fidivr",
+ "fiadd{s|}",
+ "fimul{s|}",
+ "ficom{s|}",
+ "ficomp{s|}",
+ "fisub{s|}",
+ "fisubr{s|}",
+ "fidiv{s|}",
+ "fidivr{s|}",
/* df */
- "fild",
- "fisttp",
- "fist",
- "fistp",
+ "fild{s|}",
+ "fisttp{s|}",
+ "fist{s|}",
+ "fistp{s|}",
"fbld",
"fild{ll|}",
"fbstp",
{ "fmul", { STi, ST }, 0 },
{ Bad_Opcode },
{ Bad_Opcode },
- { "fsub!M", { STi, ST }, 0 },
- { "fsubM", { STi, ST }, 0 },
- { "fdiv!M", { STi, ST }, 0 },
- { "fdivM", { STi, ST }, 0 },
+ { "fsub{!M|r}", { STi, ST }, 0 },
+ { "fsub{M|}", { STi, ST }, 0 },
+ { "fdiv{!M|r}", { STi, ST }, 0 },
+ { "fdiv{M|}", { STi, ST }, 0 },
},
/* dd */
{
{ "fmulp", { STi, ST }, 0 },
{ Bad_Opcode },
{ FGRPde_3 },
- { "fsub!Mp", { STi, ST }, 0 },
- { "fsubMp", { STi, ST }, 0 },
- { "fdiv!Mp", { STi, ST }, 0 },
- { "fdivMp", { STi, ST }, 0 },
+ { "fsub{!M|r}p", { STi, ST }, 0 },
+ { "fsub{M|}p", { STi, ST }, 0 },
+ { "fdiv{!M|r}p", { STi, ST }, 0 },
+ { "fdiv{M|}p", { STi, ST }, 0 },
},
/* df */
{
case 'B':
if (l == 0 && len == 1)
{
-case_B:
+ case_B:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
*obufp++ = 'n';
}
break;
- case 'J':
- if (intel_syntax)
- break;
- *obufp++ = 'l';
- break;
case 'K':
USED_REX (REX_W);
if (rex & REX_W)
SAVE_LAST (*p);
break;
}
-case_L:
+ case_L:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
case 'P':
if (l == 0 && len == 1)
{
-case_P:
+ case_P:
if (intel_syntax)
{
if ((rex & REX_W) == 0
case 'Q':
if (l == 0 && len == 1)
{
-case_Q:
+ case_Q:
if (intel_syntax && !alt)
break;
USED_REX (REX_W);
SAVE_LAST (*p);
break;
}
- if (intel_syntax
+ if ((intel_syntax && need_modrm)
|| (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)))
break;
if ((rex & REX_W))
USED_REX (REX_W);
*obufp++ = 'q';
}
- else
- *obufp++ = 'l';
+ else if((address_mode == mode_64bit && need_modrm)
+ || (sizeflag & SUFFIX_ALWAYS))
+ *obufp++ = intel_syntax? 'd' : 'l';
}
break;
case 'R':
case 'S':
if (l == 0 && len == 1)
{
-case_S:
+ case_S:
if (intel_syntax)
break;
if (sizeflag & SUFFIX_ALWAYS)
SAVE_LAST (*p);
break;
}
- if (need_vex && vex.prefix)
+ if (need_vex
+ ? vex.prefix == DATA_PREFIX_OPCODE
+ : prefixes & PREFIX_DATA)
{
- if (vex.prefix == DATA_PREFIX_OPCODE)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
+ *obufp++ = 'd';
+ used_prefixes |= PREFIX_DATA;
}
else
- {
- if (prefixes & PREFIX_DATA)
- *obufp++ = 'd';
- else
- *obufp++ = 's';
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
+ *obufp++ = 's';
break;
case 'Y':
if (l == 0 && len == 1)
- {
- if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
- break;
- if (rex & REX_W)
- {
- USED_REX (REX_W);
- *obufp++ = 'q';
- }
- break;
- }
+ abort ();
else
{
if (l != 1 || len != 2 || last[0] != 'X')
case '^':
if (intel_syntax)
break;
+ if (isa64 == intel64 && (rex & REX_W))
+ {
+ USED_REX (REX_W);
+ *obufp++ = 'q';
+ break;
+ }
if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
{
if (sizeflag & DFLAG)
oappend ("DWORD PTR ");
used_prefixes |= (prefixes & PREFIX_DATA);
break;
+ case movsxd_mode:
+ if (!(sizeflag & DFLAG) && isa64 == intel64)
+ oappend ("WORD PTR ");
+ else
+ oappend ("DWORD PTR ");
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
case d_mode:
case d_scalar_mode:
case d_scalar_swap_mode:
case o_mode:
oappend ("OWORD PTR ");
break;
- case xmm_mdq_mode:
- case vex_w_dq_mode:
case vex_scalar_w_dq_mode:
if (!need_vex)
abort ();
oappend ("WORD PTR ");
break;
case v_bnd_mode:
+ case v_bndmk_mode:
default:
break;
}
if ((sizeflag & SUFFIX_ALWAYS)
&& (bytemode == b_swap_mode
+ || bytemode == bnd_swap_mode
|| bytemode == v_swap_mode))
swap_operand ();
names = address_mode == mode_64bit ? names64 : names32;
break;
case bnd_mode:
+ case bnd_swap_mode:
if (reg > 0x3)
{
oappend ("(bad)");
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case movsxd_mode:
+ if (!(sizeflag & DFLAG) && isa64 == intel64)
+ names = names16;
+ else
+ names = names32;
+ used_prefixes |= (prefixes & PREFIX_DATA);
+ break;
+ case va_mode:
+ names = (address_mode == mode_64bit
+ ? names64 : names32);
+ if (!(prefixes & PREFIX_ADDR))
+ names = (address_mode == mode_16bit
+ ? names16 : names);
+ else
+ {
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
+ }
+ break;
case mask_bd_mode:
case mask_mode:
if (reg > 0x7)
case db_mode:
shift = 0;
break;
+ case dq_mode:
+ if (address_mode != mode_64bit)
+ {
+ shift = 2;
+ break;
+ }
+ /* fall through */
+ case vex_scalar_w_dq_mode:
case vex_vsib_d_w_dq_mode:
case vex_vsib_d_w_d_mode:
case vex_vsib_q_w_dq_mode:
case vex_vsib_q_w_d_mode:
case evex_x_gscat_mode:
- case xmm_mdq_mode:
shift = vex.w ? 3 : 2;
break;
case x_mode:
case d_scalar_swap_mode:
shift = 2;
break;
- case w_scalar_mode:
+ case w_scalar_mode:
case xmm_mw_mode:
shift = 1;
break;
- case b_scalar_mode:
+ case b_scalar_mode:
case xmm_mb_mode:
shift = 0;
break;
int havebase;
int haveindex;
int needindex;
+ int needaddr32;
int base, rbase;
int vindex = 0;
int scale = 0;
int addr32flag = !((sizeflag & AFLAG)
|| bytemode == v_bnd_mode
- || bytemode == bnd_mode);
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode);
const char **indexes64 = names64;
const char **indexes32 = names32;
if (address_mode == mode_64bit && !havesib)
riprel = 1;
disp = get32s ();
+ if (riprel && bytemode == v_bndmk_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
}
break;
case 1:
break;
}
- /* In 32bit mode, we need index register to tell [offset] from
- [eiz*1 + offset]. */
- needindex = (havesib
- && !havebase
- && !haveindex
- && address_mode == mode_32bit);
+ needindex = 0;
+ needaddr32 = 0;
+ if (havesib
+ && !havebase
+ && !haveindex
+ && address_mode != mode_16bit)
+ {
+ if (address_mode == mode_64bit)
+ {
+ /* Display eiz instead of addr32. */
+ needindex = addr32flag;
+ needaddr32 = 1;
+ }
+ else
+ {
+ /* In 32-bit mode, we need index register to tell [offset]
+ from [eiz*1 + offset]. */
+ needindex = 1;
+ }
+ }
+
havedisp = (havebase
|| needindex
|| (havesib && (haveindex || scale != 0)));
}
}
- if ((havebase || haveindex || riprel)
- && (bytemode != v_bnd_mode)
- && (bytemode != bnd_mode))
+ if ((havebase || haveindex || needindex || needaddr32 || riprel)
+ && (address_mode != mode_64bit
+ || ((bytemode != v_bnd_mode)
+ && (bytemode != v_bndmk_mode)
+ && (bytemode != bnd_mode)
+ && (bytemode != bnd_swap_mode))))
used_prefixes |= PREFIX_ADDR;
if (havedisp || (intel_syntax && riprel))
}
}
}
+ else if (bytemode == v_bnd_mode
+ || bytemode == v_bndmk_mode
+ || bytemode == bnd_mode
+ || bytemode == bnd_swap_mode)
+ {
+ oappend ("(bad)");
+ return;
+ }
else
{
/* 16 bit address mode */
disp = *codep++;
if ((disp & 0x80) != 0)
disp -= 0x100;
+ if (vex.evex && shift > 0)
+ disp <<= shift;
break;
case 2:
disp = get16 ();
OP_G (int bytemode, int sizeflag)
{
int add = 0;
+ const char **names;
USED_REX (REX_R);
if (rex & REX_R)
add += 8;
case dqb_mode:
case dqd_mode:
case dqw_mode:
+ case movsxd_mode:
USED_REX (REX_W);
if (rex & REX_W)
oappend (names64[modrm.reg + add]);
else
{
- if ((sizeflag & DFLAG) || bytemode != v_mode)
+ if ((sizeflag & DFLAG)
+ || (bytemode != v_mode && bytemode != movsxd_mode))
oappend (names32[modrm.reg + add]);
else
oappend (names16[modrm.reg + add]);
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case va_mode:
+ names = (address_mode == mode_64bit
+ ? names64 : names32);
+ if (!(prefixes & PREFIX_ADDR))
+ {
+ if (address_mode == mode_16bit)
+ names = names16;
+ }
+ else
+ {
+ /* Remove "addr16/addr32". */
+ all_prefixes[last_addr_prefix] = 0;
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
+ used_prefixes |= PREFIX_ADDR;
+ }
+ oappend (names[modrm.reg + add]);
+ break;
case m_mode:
if (address_mode == mode_64bit)
oappend (names64[modrm.reg + add]);
op = *codep++;
mask = 0xff;
break;
- case q_mode:
- if (address_mode == mode_64bit)
- {
- op = get32s ();
- break;
- }
- /* Fall through. */
case v_mode:
USED_REX (REX_W);
if (rex & REX_W)
used_prefixes |= (prefixes & PREFIX_DATA);
}
break;
+ case d_mode:
+ mask = 0xffffffff;
+ op = get32 ();
+ break;
case w_mode:
mask = 0xfffff;
op = get16 ();
static void
OP_I64 (int bytemode, int sizeflag)
{
- bfd_signed_vma op;
- bfd_signed_vma mask = -1;
-
- if (address_mode != mode_64bit)
+ if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W))
{
OP_I (bytemode, sizeflag);
return;
}
- switch (bytemode)
- {
- case b_mode:
- FETCH_DATA (the_info, codep + 1);
- op = *codep++;
- mask = 0xff;
- break;
- case v_mode:
- USED_REX (REX_W);
- if (rex & REX_W)
- op = get64 ();
- else
- {
- if (sizeflag & DFLAG)
- {
- op = get32 ();
- mask = 0xffffffff;
- }
- else
- {
- op = get16 ();
- mask = 0xfffff;
- }
- used_prefixes |= (prefixes & PREFIX_DATA);
- }
- break;
- case w_mode:
- mask = 0xfffff;
- op = get16 ();
- break;
- default:
- oappend (INTERNAL_DISASSEMBLER_ERROR);
- return;
- }
+ USED_REX (REX_W);
- op &= mask;
scratchbuf[0] = '$';
- print_operand_value (scratchbuf + 1, 1, op);
+ print_operand_value (scratchbuf + 1, 1, get64 ());
oappend_maybe_intel (scratchbuf);
scratchbuf[0] = '\0';
}
disp -= 0x100;
break;
case v_mode:
- if (isa64 == amd64)
+ if (isa64 != intel64)
+ case dqw_mode:
USED_REX (REX_W);
if ((sizeflag & DFLAG)
|| (address_mode == mode_64bit
- && (isa64 != amd64 || (rex & REX_W))))
+ && ((isa64 == intel64 && bytemode != dqw_mode)
+ || (rex & REX_W))))
disp = get32s ();
else
{
& ~((bfd_vma) 0xffff));
}
if (address_mode != mode_64bit
- || (isa64 == amd64 && !(rex & REX_W)))
+ || (isa64 != intel64 && !(rex & REX_W)))
used_prefixes |= (prefixes & PREFIX_DATA);
break;
default:
&& bytemode != xmm_mw_mode
&& bytemode != xmm_md_mode
&& bytemode != xmm_mq_mode
- && bytemode != xmm_mdq_mode
&& bytemode != xmmq_mode
&& bytemode != evex_half_bcst_xmmq_mode
&& bytemode != ymm_mode
}
static void
-OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
-{
- /* mwaitx %eax,%ecx,%ebx */
- if (!intel_syntax)
- {
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[3]);
- two_source_ops = 1;
- }
- /* Skip mod/rm byte. */
- MODRM_CHECK;
- codep++;
-}
-
-static void
-OP_Mwait (int bytemode ATTRIBUTE_UNUSED,
- int sizeflag ATTRIBUTE_UNUSED)
+OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED)
{
- /* mwait %eax,%ecx */
+ /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */
if (!intel_syntax)
{
- const char **names = (address_mode == mode_64bit
- ? names64 : names32);
- strcpy (op_out[0], names[0]);
- strcpy (op_out[1], names[1]);
+ strcpy (op_out[0], names32[0]);
+ strcpy (op_out[1], names32[1]);
+ if (bytemode == eBX_reg)
+ strcpy (op_out[2], names32[3]);
two_source_ops = 1;
}
/* Skip mod/rm byte. */
OP_Monitor (int bytemode ATTRIBUTE_UNUSED,
int sizeflag ATTRIBUTE_UNUSED)
{
- /* monitor %eax,%ecx,%edx" */
+ /* monitor %{e,r,}ax,%ecx,%edx" */
if (!intel_syntax)
{
- const char **op1_names;
const char **names = (address_mode == mode_64bit
? names64 : names32);
- if (!(prefixes & PREFIX_ADDR))
- op1_names = (address_mode == mode_16bit
- ? names16 : names);
- else
+ if (prefixes & PREFIX_ADDR)
{
/* Remove "addr16/addr32". */
all_prefixes[last_addr_prefix] = 0;
- op1_names = (address_mode != mode_32bit
- ? names32 : names16);
+ names = (address_mode != mode_32bit
+ ? names32 : names16);
used_prefixes |= PREFIX_ADDR;
}
- strcpy (op_out[0], op1_names[0]);
- strcpy (op_out[1], names[1]);
- strcpy (op_out[2], names[2]);
+ else if (address_mode == mode_16bit)
+ names = names16;
+ strcpy (op_out[0], names[0]);
+ strcpy (op_out[1], names32[1]);
+ strcpy (op_out[2], names32[2]);
two_source_ops = 1;
}
/* Skip mod/rm byte. */
}
}
+static void
+SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
+{
+ if ( isa64 != amd64 )
+ return;
+
+ obufp = obuf;
+ BadOp ();
+ mnemonicendp = obufp;
+ ++codep;
+}
+
/* For BND-prefixed instructions 0xF2 prefix should be displayed as
"bnd". */
mnemonicendp = p;
*p = '\0';
-skip:
+ skip:
if (modrm.mod == 3)
{
int add;
return;
reg = vex.register_specifier;
- if (vex.evex)
- {
- if (!vex.v)
- reg += 16;
- }
+ vex.register_specifier = 0;
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ else if (vex.evex && !vex.v)
+ reg += 16;
if (bytemode == vex_scalar_mode)
{
names = names_xmm;
break;
case dq_mode:
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
if (rex & REX_B)
reg += 8;
}
- else if (reg > 7 && address_mode != mode_64bit)
- BadOp ();
+ if (address_mode != mode_64bit)
+ reg &= 7;
}
switch (vex.length)
}
if (vex.w)
- oappend (names_xmm[vex.register_specifier]);
+ {
+ unsigned int reg = vex.register_specifier;
+ vex.register_specifier = 0;
+
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ oappend (names_xmm[reg]);
+ }
else
OP_Vex_2src (bytemode, sizeflag);
}
if (vex.w)
OP_Vex_2src (bytemode, sizeflag);
else
- oappend (names_xmm[vex.register_specifier]);
+ {
+ unsigned int reg = vex.register_specifier;
+ vex.register_specifier = 0;
+
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ oappend (names_xmm[reg]);
+ }
}
static void
abort ();
reg >>= 4;
- if (reg > 7 && address_mode != mode_64bit)
- BadOp ();
+ if (address_mode != mode_64bit)
+ reg &= 7;
switch (vex.length)
{
OP_EX_Vex (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
- {
- if (vex.register_specifier != 0)
- BadOp ();
- need_vex_reg = 0;
- }
+ need_vex_reg = 0;
OP_EX (bytemode, sizeflag);
}
OP_XMM_Vex (int bytemode, int sizeflag)
{
if (modrm.mod != 3)
- {
- if (vex.register_specifier != 0)
- BadOp ();
- need_vex_reg = 0;
- }
+ need_vex_reg = 0;
OP_XMM (bytemode, sizeflag);
}
-static void
-VZERO_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
-{
- switch (vex.length)
- {
- case 128:
- mnemonicendp = stpcpy (obuf, "vzeroupper");
- break;
- case 256:
- mnemonicendp = stpcpy (obuf, "vzeroall");
- break;
- default:
- abort ();
- }
-}
-
static struct op vex_cmp_op[] =
{
{ STRING_COMMA_LEN ("eq") },
mnemonicendp = p;
*p = '\0';
-skip:
+ skip:
OP_M (bytemode, sizeflag);
}
+static void
+MOVSXD_Fixup (int bytemode, int sizeflag)
+{
+ /* Add proper suffix to "movsxd". */
+ char *p = mnemonicendp;
+
+ switch (bytemode)
+ {
+ case movsxd_mode:
+ if (intel_syntax)
+ {
+ *p++ = 'x';
+ *p++ = 'd';
+ goto skip;
+ }
+
+ USED_REX (REX_W);
+ if (rex & REX_W)
+ {
+ *p++ = 'l';
+ *p++ = 'q';
+ }
+ else
+ {
+ *p++ = 'x';
+ *p++ = 'd';
+ }
+ break;
+ default:
+ oappend (INTERNAL_DISASSEMBLER_ERROR);
+ break;
+ }
+
+ skip:
+ mnemonicendp = p;
+ *p = '\0';
+ OP_E (bytemode, sizeflag);
+}
+
static void
OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
MODRM_CHECK;
codep++;
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED)
{
const char **names;
+ unsigned int reg = vex.register_specifier;
+ vex.register_specifier = 0;
- if (vex.w)
+ if (rex & REX_W)
names = names64;
else
names = names32;
- oappend (names[vex.register_specifier]);
+ if (address_mode != mode_64bit)
+ reg &= 7;
+ oappend (names[reg]);
}
static void
{
if (!vex.evex
|| (bytemode != evex_rounding_mode
+ && bytemode != evex_rounding_64_mode
&& bytemode != evex_sae_mode))
abort ();
if (modrm.mod == 3 && vex.b)
switch (bytemode)
{
+ case evex_rounding_64_mode:
+ if (address_mode != mode_64bit)
+ {
+ oappend ("(bad)");
+ break;
+ }
+ /* Fall through. */
case evex_rounding_mode:
oappend (names_rounding[vex.ll]);
break;
projects / thirdparty / binutils-gdb.git / blobdiff