Add AMD znver3 processor support

[thirdparty/binutils-gdb.git] / opcodes / i386-opc.tbl

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 56c2838991fb1453032f1917317474c43abbd448..ede9e98bd69c5df2305a99a1b5982677ad53c4c6 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -3960,6 +3960,19 @@ vpclmulhqhqdq, 3, 0x6644, 0x11, 1, CpuVPCLMULQDQ|CpuAVX512F, Modrm|OpcodePrefix=
 
 // AVX512 + VPCLMULQDQ instructions end
 
+// INVLPGB instructions
+
+invlpgb, 0, 0xf01fe, None, 3, CpuINVLPGB, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+invlpgb, 2, 0xf01fe, None, 3, CpuINVLPGB, AddrPrefixOpReg, { Acc|Word|Dword|Qword, RegD|Dword }
+
+// INVLPGB instructions end
+
+// TLBSYNC instructions
+
+tlbsync, 0, 0xf01ff, None, 3, CpuTLBSYNC, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+// TLBSYNC instructions end
+
 // CLZERO instructions
 
 clzero, 0, 0xf01fc, None, 3, CpuCLZERO, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
@@ -4092,6 +4105,19 @@ mcommit, 0, 0x0f01fa, None, 3, CpuMCOMMIT, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|N
 
 // MCOMMIT instruction end
 
+// SNP instructions
+
+psmash, 0, 0xf01ff, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+psmash, 1, 0xf01ff, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
+pvalidate, 0, 0xf01ff, None, 3, CpuSNP, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+pvalidate, 1, 0xf01ff, None, 3, CpuSNP, AddrPrefixOpReg|Prefix_0XF2, { Acc|Word|Dword|Qword }
+rmpupdate, 0, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+rmpupdate, 1, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF2, { Acc|Dword|Qword }
+rmpadjust, 0, 0xf01fe, None, 3, CpuSNP|Cpu64, Prefix_0XF3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+rmpadjust, 1, 0xf01fe, None, 3, CpuSNP|Cpu64, AddrPrefixOpReg|Prefix_0XF3, { Acc|Dword|Qword }
+
+// SNP instructions end
+
 // RDPRU instruction
 
 rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }