// i386 register table.
-// Copyright (C) 2007-2019 Free Software Foundation, Inc.
+// Copyright (C) 2007-2021 Free Software Foundation, Inc.
//
// This file is part of the GNU opcodes library.
//
// 02110-1301, USA.
// Make %st first as we test for it.
-st, Class=Reg|Acc|Tbyte, 0, 0, 11, 33
+st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
// 8 bit regs
-al, Class=Reg|Acc|Byte, 0, 0, Dw2Inval, Dw2Inval
-cl, Class=Reg|Byte|ShiftCount, 0, 1, Dw2Inval, Dw2Inval
+al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
+cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
// 16 bit regs
-ax, Class=Reg|Acc|Word, 0, 0, Dw2Inval, Dw2Inval
+ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
-dx, Class=Reg|Word|InOutPortReg, 0, 2, Dw2Inval, Dw2Inval
+dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
// 32 bit regs
-eax, Class=Reg|Acc|Dword|BaseIndex, 0, 0, 0, Dw2Inval
-ecx, Class=Reg|Dword|BaseIndex, 0, 1, 1, Dw2Inval
-edx, Class=Reg|Dword|BaseIndex, 0, 2, 2, Dw2Inval
-ebx, Class=Reg|Dword|BaseIndex, 0, 3, 3, Dw2Inval
+eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
+ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
+edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
+ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
-rax, Class=Reg|Acc|Qword|BaseIndex, 0, 0, Dw2Inval, 0
-rcx, Class=Reg|Qword|BaseIndex, 0, 1, Dw2Inval, 2
-rdx, Class=Reg|Qword|BaseIndex, 0, 2, Dw2Inval, 1
-rbx, Class=Reg|Qword|BaseIndex, 0, 3, Dw2Inval, 3
+rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
+rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
+rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
+rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
// Vector mask registers.
-k0, RegMask, 0, 0, 93, 118
-k1, RegMask, 0, 1, 94, 119
-k2, RegMask, 0, 2, 95, 120
-k3, RegMask, 0, 3, 96, 121
-k4, RegMask, 0, 4, 97, 122
-k5, RegMask, 0, 5, 98, 123
-k6, RegMask, 0, 6, 99, 124
-k7, RegMask, 0, 7, 100, 125
+k0, Class=RegMask, 0, 0, 93, 118
+k1, Class=RegMask, 0, 1, 94, 119
+k2, Class=RegMask, 0, 2, 95, 120
+k3, Class=RegMask, 0, 3, 96, 121
+k4, Class=RegMask, 0, 4, 97, 122
+k5, Class=RegMask, 0, 5, 98, 123
+k6, Class=RegMask, 0, 6, 99, 124
+k7, Class=RegMask, 0, 7, 100, 125
// Segment registers.
-es, SReg, 0, 0, 40, 50
-cs, SReg, 0, 1, 41, 51
-ss, SReg, 0, 2, 42, 52
-ds, SReg, 0, 3, 43, 53
-fs, SReg, 0, 4, 44, 54
-gs, SReg, 0, 5, 45, 55
-flat, SReg, 0, RegFlat, Dw2Inval, Dw2Inval
+es, Class=SReg, 0, 0, 40, 50
+cs, Class=SReg, 0, 1, 41, 51
+ss, Class=SReg, 0, 2, 42, 52
+ds, Class=SReg, 0, 3, 43, 53
+fs, Class=SReg, 0, 4, 44, 54
+gs, Class=SReg, 0, 5, 45, 55
+flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
// Control registers.
-cr0, Control, 0, 0, Dw2Inval, Dw2Inval
-cr1, Control, 0, 1, Dw2Inval, Dw2Inval
-cr2, Control, 0, 2, Dw2Inval, Dw2Inval
-cr3, Control, 0, 3, Dw2Inval, Dw2Inval
-cr4, Control, 0, 4, Dw2Inval, Dw2Inval
-cr5, Control, 0, 5, Dw2Inval, Dw2Inval
-cr6, Control, 0, 6, Dw2Inval, Dw2Inval
-cr7, Control, 0, 7, Dw2Inval, Dw2Inval
-cr8, Control, RegRex, 0, Dw2Inval, Dw2Inval
-cr9, Control, RegRex, 1, Dw2Inval, Dw2Inval
-cr10, Control, RegRex, 2, Dw2Inval, Dw2Inval
-cr11, Control, RegRex, 3, Dw2Inval, Dw2Inval
-cr12, Control, RegRex, 4, Dw2Inval, Dw2Inval
-cr13, Control, RegRex, 5, Dw2Inval, Dw2Inval
-cr14, Control, RegRex, 6, Dw2Inval, Dw2Inval
-cr15, Control, RegRex, 7, Dw2Inval, Dw2Inval
+cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
+cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
+cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
+cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
+cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
+cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
+cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
+cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
+cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
+cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
+cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
+cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
+cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
+cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
+cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
+cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
// Debug registers.
-db0, Debug, 0, 0, Dw2Inval, Dw2Inval
-db1, Debug, 0, 1, Dw2Inval, Dw2Inval
-db2, Debug, 0, 2, Dw2Inval, Dw2Inval
-db3, Debug, 0, 3, Dw2Inval, Dw2Inval
-db4, Debug, 0, 4, Dw2Inval, Dw2Inval
-db5, Debug, 0, 5, Dw2Inval, Dw2Inval
-db6, Debug, 0, 6, Dw2Inval, Dw2Inval
-db7, Debug, 0, 7, Dw2Inval, Dw2Inval
-db8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
-db9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
-db10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
-db11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
-db12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
-db13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
-db14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
-db15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
-dr0, Debug, 0, 0, Dw2Inval, Dw2Inval
-dr1, Debug, 0, 1, Dw2Inval, Dw2Inval
-dr2, Debug, 0, 2, Dw2Inval, Dw2Inval
-dr3, Debug, 0, 3, Dw2Inval, Dw2Inval
-dr4, Debug, 0, 4, Dw2Inval, Dw2Inval
-dr5, Debug, 0, 5, Dw2Inval, Dw2Inval
-dr6, Debug, 0, 6, Dw2Inval, Dw2Inval
-dr7, Debug, 0, 7, Dw2Inval, Dw2Inval
-dr8, Debug, RegRex, 0, Dw2Inval, Dw2Inval
-dr9, Debug, RegRex, 1, Dw2Inval, Dw2Inval
-dr10, Debug, RegRex, 2, Dw2Inval, Dw2Inval
-dr11, Debug, RegRex, 3, Dw2Inval, Dw2Inval
-dr12, Debug, RegRex, 4, Dw2Inval, Dw2Inval
-dr13, Debug, RegRex, 5, Dw2Inval, Dw2Inval
-dr14, Debug, RegRex, 6, Dw2Inval, Dw2Inval
-dr15, Debug, RegRex, 7, Dw2Inval, Dw2Inval
+db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
+db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
+db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
+db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
+db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
+db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
+db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
+db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
+db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
+db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
+db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
+db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
+db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
+db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
+db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
+db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
+dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
+dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
+dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
+dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
+dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
+dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
+dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
+dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
+dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
+dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
+dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
+dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
+dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
+dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
+dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
+dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
// Test registers.
-tr0, Test, 0, 0, Dw2Inval, Dw2Inval
-tr1, Test, 0, 1, Dw2Inval, Dw2Inval
-tr2, Test, 0, 2, Dw2Inval, Dw2Inval
-tr3, Test, 0, 3, Dw2Inval, Dw2Inval
-tr4, Test, 0, 4, Dw2Inval, Dw2Inval
-tr5, Test, 0, 5, Dw2Inval, Dw2Inval
-tr6, Test, 0, 6, Dw2Inval, Dw2Inval
-tr7, Test, 0, 7, Dw2Inval, Dw2Inval
+tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
+tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
+tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
+tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
+tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
+tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
+tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
+tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
// MMX and simd registers.
-mm0, RegMMX, 0, 0, 29, 41
-mm1, RegMMX, 0, 1, 30, 42
-mm2, RegMMX, 0, 2, 31, 43
-mm3, RegMMX, 0, 3, 32, 44
-mm4, RegMMX, 0, 4, 33, 45
-mm5, RegMMX, 0, 5, 34, 46
-mm6, RegMMX, 0, 6, 35, 47
-mm7, RegMMX, 0, 7, 36, 48
-xmm0, RegSIMD|Acc|Xmmword, 0, 0, 21, 17
-xmm1, RegSIMD|Xmmword, 0, 1, 22, 18
-xmm2, RegSIMD|Xmmword, 0, 2, 23, 19
-xmm3, RegSIMD|Xmmword, 0, 3, 24, 20
-xmm4, RegSIMD|Xmmword, 0, 4, 25, 21
-xmm5, RegSIMD|Xmmword, 0, 5, 26, 22
-xmm6, RegSIMD|Xmmword, 0, 6, 27, 23
-xmm7, RegSIMD|Xmmword, 0, 7, 28, 24
-xmm8, RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
-xmm9, RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
-xmm10, RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
-xmm11, RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
-xmm12, RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
-xmm13, RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
-xmm14, RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
-xmm15, RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
-xmm16, RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
-xmm17, RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
-xmm18, RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
-xmm19, RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
-xmm20, RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
-xmm21, RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
-xmm22, RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
-xmm23, RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
-xmm24, RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
-xmm25, RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
-xmm26, RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
-xmm27, RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
-xmm28, RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
-xmm29, RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
-xmm30, RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
-xmm31, RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
+mm0, Class=RegMMX, 0, 0, 29, 41
+mm1, Class=RegMMX, 0, 1, 30, 42
+mm2, Class=RegMMX, 0, 2, 31, 43
+mm3, Class=RegMMX, 0, 3, 32, 44
+mm4, Class=RegMMX, 0, 4, 33, 45
+mm5, Class=RegMMX, 0, 5, 34, 46
+mm6, Class=RegMMX, 0, 6, 35, 47
+mm7, Class=RegMMX, 0, 7, 36, 48
+xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
+xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
+xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
+xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
+xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
+xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
+xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
+xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
+xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
+xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
+xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
+xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
+xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
+xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
+xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
+xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
+xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
+xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
+xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
+xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
+xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
+xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
+xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
+xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
+xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
+xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
+xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
+xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
+xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
+xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
+xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
+xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
// AVX registers.
-ymm0, RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
-ymm1, RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
-ymm2, RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
-ymm3, RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
-ymm4, RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
-ymm5, RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
-ymm6, RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
-ymm7, RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
-ymm8, RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
-ymm9, RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
-ymm10, RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
-ymm11, RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
-ymm12, RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
-ymm13, RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
-ymm14, RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
-ymm15, RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
-ymm16, RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
-ymm17, RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
-ymm18, RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
-ymm19, RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
-ymm20, RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
-ymm21, RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
-ymm22, RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
-ymm23, RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
-ymm24, RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
-ymm25, RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
-ymm26, RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
-ymm27, RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
-ymm28, RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
-ymm29, RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
-ymm30, RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
-ymm31, RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+ymm0, Class=RegSIMD|Ymmword, 0, 0, Dw2Inval, Dw2Inval
+ymm1, Class=RegSIMD|Ymmword, 0, 1, Dw2Inval, Dw2Inval
+ymm2, Class=RegSIMD|Ymmword, 0, 2, Dw2Inval, Dw2Inval
+ymm3, Class=RegSIMD|Ymmword, 0, 3, Dw2Inval, Dw2Inval
+ymm4, Class=RegSIMD|Ymmword, 0, 4, Dw2Inval, Dw2Inval
+ymm5, Class=RegSIMD|Ymmword, 0, 5, Dw2Inval, Dw2Inval
+ymm6, Class=RegSIMD|Ymmword, 0, 6, Dw2Inval, Dw2Inval
+ymm7, Class=RegSIMD|Ymmword, 0, 7, Dw2Inval, Dw2Inval
+ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, Dw2Inval
+ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, Dw2Inval
+ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, Dw2Inval
+ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, Dw2Inval
+ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, Dw2Inval
+ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, Dw2Inval
+ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, Dw2Inval
+ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, Dw2Inval
+ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, Dw2Inval
+ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, Dw2Inval
+ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, Dw2Inval
+ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, Dw2Inval
+ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, Dw2Inval
+ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, Dw2Inval
+ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, Dw2Inval
+ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, Dw2Inval
+ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
// AVX512 registers.
-zmm0, RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
-zmm1, RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
-zmm2, RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
-zmm3, RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
-zmm4, RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
-zmm5, RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
-zmm6, RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
-zmm7, RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
-zmm8, RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
-zmm9, RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
-zmm10, RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
-zmm11, RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
-zmm12, RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
-zmm13, RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
-zmm14, RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
-zmm15, RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
-zmm16, RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
-zmm17, RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
-zmm18, RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
-zmm19, RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
-zmm20, RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
-zmm21, RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
-zmm22, RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
-zmm23, RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
-zmm24, RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
-zmm25, RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
-zmm26, RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
-zmm27, RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
-zmm28, RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
-zmm29, RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
-zmm30, RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
-zmm31, RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+zmm0, Class=RegSIMD|Zmmword, 0, 0, Dw2Inval, Dw2Inval
+zmm1, Class=RegSIMD|Zmmword, 0, 1, Dw2Inval, Dw2Inval
+zmm2, Class=RegSIMD|Zmmword, 0, 2, Dw2Inval, Dw2Inval
+zmm3, Class=RegSIMD|Zmmword, 0, 3, Dw2Inval, Dw2Inval
+zmm4, Class=RegSIMD|Zmmword, 0, 4, Dw2Inval, Dw2Inval
+zmm5, Class=RegSIMD|Zmmword, 0, 5, Dw2Inval, Dw2Inval
+zmm6, Class=RegSIMD|Zmmword, 0, 6, Dw2Inval, Dw2Inval
+zmm7, Class=RegSIMD|Zmmword, 0, 7, Dw2Inval, Dw2Inval
+zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, Dw2Inval
+zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, Dw2Inval
+zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, Dw2Inval
+zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, Dw2Inval
+zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, Dw2Inval
+zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, Dw2Inval
+zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, Dw2Inval
+zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, Dw2Inval
+zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, Dw2Inval
+zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, Dw2Inval
+zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, Dw2Inval
+zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, Dw2Inval
+zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, Dw2Inval
+zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, Dw2Inval
+zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, Dw2Inval
+zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, Dw2Inval
+zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, Dw2Inval
+zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, Dw2Inval
+zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, Dw2Inval
+zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, Dw2Inval
+zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, Dw2Inval
+zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, Dw2Inval
+zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, Dw2Inval
+zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, Dw2Inval
+// TMM registers for AMX
+tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
+tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
+tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
+tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
+tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
+tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
+tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
+tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
// Bound registers for MPX
-bnd0, RegBND, 0, 0, Dw2Inval, Dw2Inval
-bnd1, RegBND, 0, 1, Dw2Inval, Dw2Inval
-bnd2, RegBND, 0, 2, Dw2Inval, Dw2Inval
-bnd3, RegBND, 0, 3, Dw2Inval, Dw2Inval
+bnd0, Class=RegBND, 0, 0, Dw2Inval, Dw2Inval
+bnd1, Class=RegBND, 0, 1, Dw2Inval, Dw2Inval
+bnd2, Class=RegBND, 0, 2, Dw2Inval, Dw2Inval
+bnd3, Class=RegBND, 0, 3, Dw2Inval, Dw2Inval
// No Class=Reg will make these registers rejected for all purposes except
// for addressing. This saves creating one extra type for RIP/EIP.
rip, Qword, RegRex64, RegIP, Dw2Inval, 16
riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
// fp regs.
-st(0), Class=Reg|Acc|Tbyte, 0, 0, 11, 33
+st(0), Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
st(1), Class=Reg|Tbyte, 0, 1, 12, 34
st(2), Class=Reg|Tbyte, 0, 2, 13, 35
st(3), Class=Reg|Tbyte, 0, 3, 14, 36
projects / thirdparty / binutils-gdb.git / blobdiff