]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blobdiff - opcodes/mips-opc.c
MIPS/GAS: Split Loongson MMI Instructions from loongson2f/3a
[thirdparty/binutils-gdb.git] / opcodes / mips-opc.c
index 3dcec768481c1c36a2a1f9421217f94a59bbc7dc..31532f88a8dd7f3229a2af97facc363cb09ca4e4 100644 (file)
@@ -1,5 +1,5 @@
 /* mips-opc.c -- MIPS opcode list.
-   Copyright (C) 1993-2016 Free Software Foundation, Inc.
+   Copyright (C) 1993-2018 Free Software Foundation, Inc.
    Contributed by Ralph Campbell and OSF
    Commented and modified by Ian Lance Taylor, Cygnus Support
    Extended for MIPS32 support by Anders Norlander, and by SiByte, Inc.
@@ -46,6 +46,7 @@ decode_mips_operand (const char *p)
        case 'a': INT_ADJ (19, 0, 262143, 2, FALSE);
        case 'b': INT_ADJ (18, 0, 131071, 3, FALSE);
        case 'd': SPECIAL (0, 0, REPEAT_DEST_REG);
+       case 'm': SPECIAL (20, 6, SAVE_RESTORE_LIST);
        case 's': SPECIAL (5, 21, NON_ZERO_REG);
        case 't': SPECIAL (5, 16, NON_ZERO_REG);
        case 'u': PREV_CHECK (5, 16, TRUE, FALSE, FALSE, FALSE);
@@ -138,6 +139,7 @@ decode_mips_operand (const char *p)
        case '\'': BRANCH (26, 0, 2);
        case '"': BRANCH (21, 0, 2);
        case ';': SPECIAL (10, 16, SAME_RS_RT);
+       case '\\': BIT (2, 8, 0);               /* (0 .. 3) */
        }
       break;
 
@@ -232,6 +234,7 @@ decode_mips_operand (const char *p)
 #define RD_2   INSN_READ_2
 #define RD_3   INSN_READ_3
 #define RD_4   INSN_READ_4
+#define RD_31  INSN2_READ_GPR_31
 #define MOD_1  (WR_1|RD_1)
 #define MOD_2  (WR_2|RD_2)
 
@@ -261,6 +264,10 @@ decode_mips_operand (const char *p)
 #define RD_HILO RD_HI|RD_LO
 #define MOD_HILO WR_HILO|RD_HILO
 
+#define RD_SP  INSN2_READ_SP
+#define WR_SP  INSN2_WRITE_SP
+#define MOD_SP (RD_SP|WR_SP)
+
 #define IS_M    INSN_MULT
 
 #define WR_MACC INSN2_WRITE_MDMX_ACC
@@ -321,6 +328,7 @@ decode_mips_operand (const char *p)
 #define IOCT2  (INSN_OCTEON2 | INSN_OCTEON3)
 #define IOCT3  INSN_OCTEON3
 #define XLR     INSN_XLR
+#define IAMR2  INSN_INTERAPTIV_MR2
 #define IVIRT  ASE_VIRT
 #define IVIRT64        ASE_VIRT64
 
@@ -395,6 +403,17 @@ decode_mips_operand (const char *p)
 
 /* eXtended Physical Address (XPA) support.  */
 #define XPA     ASE_XPA
+#define XPAVZ  ASE_XPA_VIRT
+
+/* Cyclic redundancy check instruction (CRC) support.  */
+#define CRC    ASE_CRC
+#define CRC64  ASE_CRC64
+
+/* Global INValidate (GINV) support.  */
+#define GINV   ASE_GINV
+
+/* Loongson MultiMedia extensions Instructions (MMI) support.  */
+#define LMMI   ASE_LOONGSON_MMI
 
 /* The order of overloaded instructions matters.  Label arguments and
    register arguments look the same. Instructions that can have either
@@ -636,7 +655,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"add",                        "d,v,t",        0x00000020, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"add",                        "t,r,I",        0,    (int) M_ADD_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"add",                        "D,S,T",        0x45c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"add",                        "D,S,T",        0x4b40000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"add.s",              "D,V,T",        0x46000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"add.d",              "D,V,T",        0x46200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"add.ob",             "X,Y,Q",        0x7800000b, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -657,7 +676,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"addu",               "d,v,t",        0x00000021, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"addu",               "t,r,I",        0,    (int) M_ADDU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"addu",               "D,S,T",        0x45800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"addu",               "D,S,T",        0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"addu",               "D,S,T",        0x4b00000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"alni.ob",            "X,Y,Z,O",      0x78000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"alni.ob",            "D,S,T,%",      0x48000018, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"alni.qh",            "X,Y,Z,O",      0x7800001a, 0xff00003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -667,7 +686,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"and",                        "d,v,t",        0x00000024, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"and",                        "t,r,I",        0,    (int) M_AND_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"and",                        "D,S,T",        0x47c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"and",                        "D,S,T",        0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"and",                        "D,S,T",        0x4bc00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"and.ob",             "X,Y,Q",        0x7800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"and.ob",             "D,S,Q",        0x4800000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"and.qh",             "X,Y,Q",        0x7820000c, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -985,7 +1004,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dadd",               "d,v,t",        0x0000002c, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dadd",               "t,r,I",        0,    (int) M_DADD_I,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"dadd",               "D,S,T",        0x45e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dadd",               "D,S,T",        0x4b60000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"daddi",              "t,r,j",        0x60000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      I69 },
 {"daddiu",             "t,r,j",        0x64000000, 0xfc000000, WR_1|RD_2,              0,              I3,             0,      0 },
 {"daddu",              "d,v,t",        0x0000002d, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
@@ -1125,25 +1144,25 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dsll",               "d,w,>",        0x0000003c, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsll32 */
 {"dsll",               "d,w,<",        0x00000038, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsll",               "D,S,T",        0x45a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsll",               "D,S,T",        0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsll",               "D,S,T",        0x4b20000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsrav",              "d,t,s",        0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsra32",             "d,w,<",        0x0000003f, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsra",               "d,w,s",        0x00000017, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 }, /* dsrav */
 {"dsra",               "d,w,>",        0x0000003f, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsra32 */
 {"dsra",               "d,w,<",        0x0000003b, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsra",               "D,S,T",        0x45e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsra",               "D,S,T",        0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsra",               "D,S,T",        0x4b60000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsrlv",              "d,t,s",        0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsrl32",             "d,w,<",        0x0000003e, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsrl",               "d,w,s",        0x00000016, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 }, /* dsrlv */
 {"dsrl",               "d,w,>",        0x0000003e, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 }, /* dsrl32 */
 {"dsrl",               "d,w,<",        0x0000003a, 0xffe0003f, WR_1|RD_2,              0,              I3,             0,      0 },
 {"dsrl",               "D,S,T",        0x45a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsrl",               "D,S,T",        0x4b20000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsub",               "d,v,t",        0x0000002e, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsub",               "d,v,I",        0,    (int) M_DSUB_I,   INSN_MACRO,             0,              I3,             0,      I69 },
 {"dsub",               "D,S,T",        0x45e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"dsub",               "D,S,T",        0x4b60000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"dsubu",              "d,v,t",        0x0000002f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I3,             0,      0 },
 {"dsubu",              "d,v,I",        0,    (int) M_DSUBU_I,  INSN_MACRO,             0,              I3,             0,      0 },
 {"dvpe",               "",             0x41600001, 0xffffffff, TRAP,                   0,              0,              MT32,   0 },
@@ -1383,10 +1402,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mfc0",               "t,G,H",        0x40000000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I32,            0,      0 },
 {"mfgc0",              "t,G",          0x40600000, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
 {"mfgc0",              "t,G,H",        0x40600000, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              IVIRT,  0 },
-{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              I33,            XPA,    0 },
-{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LC,          0,              I33,            XPA,    0 },
-{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LC,          0,              I33,            IVIRT|XPA,      0 },
-{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LC,          0,              I33,            IVIRT|XPA,      0 },
+{"mfhc0",              "t,G",          0x40400000, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              XPA,    0 },
+{"mfhc0",              "t,G,H",        0x40400000, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              XPA,    0 },
+{"mfhgc0",             "t,G",          0x40600400, 0xffe007ff, WR_1|RD_C0|LC,          0,              0,              XPAVZ,  0 },
+{"mfhgc0",             "t,G,H",        0x40600400, 0xffe007f8, WR_1|RD_C0|LC,          0,              0,              XPAVZ,  0 },
 {"mfc1",               "t,S",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
 {"mfc1",               "t,G",          0x44000000, 0xffe007ff, WR_1|RD_2|LC|FP_S,      0,              I1,             0,      0 },
 {"mfhc1",              "t,S",          0x44600000, 0xffe007ff, WR_1|RD_2|LC|FP_D,      0,              I33,            0,      0 },
@@ -1481,10 +1500,10 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"mtc0",               "t,G,H",        0x40800000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I32,            0,      0 },
 {"mtgc0",              "t,G",          0x40600200, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              IVIRT,  0 },
 {"mtgc0",              "t,G,H",        0x40600200, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,   0,               0,              IVIRT,  0 },
-{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
-{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            XPA,    0 },
-{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
-{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              I33,            IVIRT|XPA,      0 },
+{"mthc0",              "t,G",          0x40c00000, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPA,    0 },
+{"mthc0",              "t,G,H",        0x40c00000, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPA,    0 },
+{"mthgc0",             "t,G",          0x40600600, 0xffe007ff, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPAVZ,  0 },
+{"mthgc0",             "t,G,H",        0x40600600, 0xffe007f8, RD_1|WR_C0|WR_CC|CM,    0,              0,              XPAVZ,  0 },
 {"mtc1",               "t,S",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
 {"mtc1",               "t,G",          0x44800000, 0xffe007ff, RD_1|WR_2|CM|FP_S,      0,              I1,             0,      0 },
 {"mthc1",              "t,S",          0x44e00000, 0xffe007ff, RD_1|WR_2|CM|FP_D,      0,              I33,            0,      0 },
@@ -1612,7 +1631,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"nor",                        "d,v,t",        0x00000027, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"nor",                        "t,r,I",        0,    (int) M_NOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"nor",                        "D,S,T",        0x47a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"nor",                        "D,S,T",        0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"nor",                        "D,S,T",        0x4ba00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"nor.ob",             "X,Y,Q",        0x7800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"nor.ob",             "D,S,Q",        0x4800000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"nor.qh",             "X,Y,Q",        0x7820000f, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1620,7 +1639,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"or",                 "d,v,t",        0x00000025, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"or",                 "t,r,I",        0,    (int) M_OR_I,     INSN_MACRO,             0,              I1,             0,      0 },
 {"or",                 "D,S,T",        0x45a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"or",                 "D,S,T",        0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"or",                 "D,S,T",        0x4b20000c, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"or.ob",              "X,Y,Q",        0x7800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"or.ob",              "D,S,Q",        0x4800000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"or.qh",              "X,Y,Q",        0x7820000e, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1833,7 +1852,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"seq",                        "d,v,t",        0,    (int) M_SEQ,      INSN_MACRO,             0,              I1,             0,      0 },
 {"seq",                        "d,v,I",        0,    (int) M_SEQ_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"seq",                        "S,T",          0x46a00032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"seq",                        "S,T",          0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"seq",                        "S,T",          0x4ba0000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"seqi",               "t,r,+Q",       0x7000002e, 0xfc00003f, WR_1|RD_2,              0,              IOCT,           0,      0 },
 {"sge",                        "d,v,t",        0,    (int) M_SGE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sge",                        "d,v,I",        0,    (int) M_SGE_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1859,33 +1878,33 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"shfl.repa.qh",       "X,Y,Z",        0x7b20001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.repb.qh",       "X,Y,Z",        0x7ba0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"shfl.upsl.ob",       "X,Y,Z",        0x78c0001f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
-{"sigrie",             "u",            0x41700000, 0xffff0000, TRAP,                   0,              I37,            0,      0 },
+{"sigrie",             "u",            0x04170000, 0xffff0000, TRAP,                   0,              I37,            0,      0 },
 {"sle",                        "d,v,t",        0,    (int) M_SLE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "d,v,I",        0,    (int) M_SLE_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"sle",                        "S,T",          0x46a0003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sle",                        "S,T",          0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sle",                        "S,T",          0x4ba0000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sleu",               "d,v,t",        0,    (int) M_SLEU,     INSN_MACRO,             0,              I1,             0,      0 },
 {"sleu",               "d,v,I",        0,    (int) M_SLEU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"sleu",               "S,T",          0x4680003e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sleu",               "S,T",          0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sleu",               "S,T",          0x4b80000e, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sllv",               "d,t,s",        0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sll",                        "d,w,s",        0x00000004, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* sllv */
 {"sll",                        "d,w,<",        0x00000000, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sll",                        "D,S,T",        0x45800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"sll",                        "D,S,T",        0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"sll",                        "D,S,T",        0x4b00000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sll.ob",             "X,Y,Q",        0x78000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"sll.ob",             "D,S,Q",        0x48000010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"sll.qh",             "X,Y,Q",        0x78200010, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"slt",                        "d,v,t",        0x0000002a, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"slt",                        "d,v,I",        0,    (int) M_SLT_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"slt",                        "S,T",          0x46a0003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"slt",                        "S,T",          0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"slt",                        "S,T",          0x4ba0000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"slti",               "t,r,j",        0x28000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sltiu",              "t,r,j",        0x2c000000, 0xfc000000, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sltu",               "d,v,t",        0x0000002b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sltu",               "d,v,I",        0,    (int) M_SLTU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"sltu",               "S,T",          0x4680003c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sltu",               "S,T",          0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sltu",               "S,T",          0x4b80000d, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 {"sne",                        "d,v,t",        0x7000002b, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IOCT,           0,      0 },
 {"sne",                        "d,v,t",        0,    (int) M_SNE,      INSN_MACRO,             0,              I1,             0,      0 },
 {"sne",                        "d,v,I",        0,    (int) M_SNE_I,    INSN_MACRO,             0,              I1,             0,      0 },
@@ -1901,13 +1920,13 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sra",                        "d,w,s",        0x00000007, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* srav */
 {"sra",                        "d,w,<",        0x00000003, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"sra",                        "D,S,T",        0x45c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"sra",                        "D,S,T",        0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"sra",                        "D,S,T",        0x4b40000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sra.qh",             "X,Y,Q",        0x78200013, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
 {"srlv",               "d,t,s",        0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"srl",                        "d,w,s",        0x00000006, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 }, /* srlv */
 {"srl",                        "d,w,<",        0x00000002, 0xffe0003f, WR_1|RD_2,              0,              I1,             0,      0 },
 {"srl",                        "D,S,T",        0x45800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"srl",                        "D,S,T",        0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"srl",                        "D,S,T",        0x4b00000f, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"srl.ob",             "X,Y,Q",        0x78000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"srl.ob",             "D,S,Q",        0x48000012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"srl.qh",             "X,Y,Q",        0x78200012, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -1916,7 +1935,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"sub",                        "d,v,t",        0x00000022, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"sub",                        "d,v,I",        0,    (int) M_SUB_I,    INSN_MACRO,             0,              I1,             0,      I37 },
 {"sub",                        "D,S,T",        0x45c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"sub",                        "D,S,T",        0x4b40000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"sub.d",              "D,V,T",        0x46200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              I1,             0,      SF },
 {"sub.s",              "D,V,T",        0x46000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              I1,             0,      0 },
 {"sub.ob",             "X,Y,Q",        0x7800000a, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
@@ -1932,7 +1951,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"subu",               "d,v,t",        0x00000023, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"subu",               "d,v,I",        0,    (int) M_SUBU_I,   INSN_MACRO,             0,              I1,             0,      0 },
 {"subu",               "D,S,T",        0x45800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2E,           0,      0 },
-{"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              IL2F|IL3A,      0,      0 },
+{"subu",               "D,S,T",        0x4b00000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_S,    0,              0,              LMMI,   0 },
 {"suspend",            "",             0x42000022, 0xffffffff, 0,                      0,              V1,             0,      0 },
 {"suxc1",              "S,t(b)",       0x4c00000d, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_D, 0,              I5_33|N55,      0,      I37},
 {"sw",                 "t,o(b)",       0xac000000, 0xfc000000, RD_1|RD_3|SM,           0,              I1,             0,      0 },
@@ -1962,15 +1981,15 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"invalidate",         "t,o(b)",       0xb8000000, 0xfc000000, RD_1|RD_3,              0,              I2,             0,      I37 }, /* same */
 {"invalidate",         "t,A(b)",       0,    (int) M_SWR_AB,   INSN_MACRO,             0,              I2,             0,      I37 }, /* as swr */
 {"swxc1",              "S,t(b)",       0x4c000008, 0xfc0007ff, RD_1|RD_2|RD_3|SM|FP_S, 0,              I4_33,          0,      I37 },
-{"synciobdma",         "",             0x0000008f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
-{"syncs",              "",             0x0000018f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
-{"syncw",              "",             0x0000010f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
-{"syncws",             "",             0x0000014f, 0xffffffff, NODS,                   0,              IOCT,           0,      0 },
-{"sync_acquire",       "",             0x0000044f, 0xffffffff, NODS,                   0,              I33,            0,      0 },
-{"sync_mb",            "",             0x0000040f, 0xffffffff, NODS,                   0,              I33,            0,      0 },
-{"sync_release",       "",             0x0000048f, 0xffffffff, NODS,                   0,              I33,            0,      0 },
-{"sync_rmb",           "",             0x000004cf, 0xffffffff, NODS,                   0,              I33,            0,      0 },
-{"sync_wmb",           "",             0x0000010f, 0xffffffff, NODS,                   0,              I33,            0,      0 },
+{"synciobdma",         "",             0x0000008f, 0xffffffff, NODS,                   INSN2_ALIAS,    IOCT,           0,      0 },
+{"syncs",              "",             0x0000018f, 0xffffffff, NODS,                   INSN2_ALIAS,    IOCT,           0,      0 },
+{"syncw",              "",             0x0000010f, 0xffffffff, NODS,                   INSN2_ALIAS,    IOCT,           0,      0 },
+{"syncws",             "",             0x0000014f, 0xffffffff, NODS,                   INSN2_ALIAS,    IOCT,           0,      0 },
+{"sync_acquire",       "",             0x0000044f, 0xffffffff, NODS,                   INSN2_ALIAS,    I33,            0,      0 },
+{"sync_mb",            "",             0x0000040f, 0xffffffff, NODS,                   INSN2_ALIAS,    I33,            0,      0 },
+{"sync_release",       "",             0x0000048f, 0xffffffff, NODS,                   INSN2_ALIAS,    I33,            0,      0 },
+{"sync_rmb",           "",             0x000004cf, 0xffffffff, NODS,                   INSN2_ALIAS,    I33,            0,      0 },
+{"sync_wmb",           "",             0x0000010f, 0xffffffff, NODS,                   INSN2_ALIAS,    I33,            0,      0 },
 {"sync",               "",             0x0000000f, 0xffffffff, NODS,                   0,              I2|G1,          0,      0 },
 {"sync",               "1",            0x0000000f, 0xfffff83f, NODS,                   0,              I32,            0,      0 },
 {"sync.p",             "",             0x0000040f, 0xffffffff, NODS,                   0,              I2,             0,      0 },
@@ -2053,7 +2072,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"xor",                        "d,v,t",        0x00000026, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              I1,             0,      0 },
 {"xor",                        "t,r,I",        0,    (int) M_XOR_I,    INSN_MACRO,             0,              I1,             0,      0 },
 {"xor",                        "D,S,T",        0x47800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"xor",                        "D,S,T",        0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"xor",                        "D,S,T",        0x4b800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"xor.ob",             "X,Y,Q",        0x7800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              SB1,            MX,     0 },
 {"xor.ob",             "D,S,Q",        0x4800000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              N54,            0,      0 },
 {"xor.qh",             "X,Y,Q",        0x7820000d, 0xfc20003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              MX,     0 },
@@ -2454,139 +2473,139 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"dmodu.g",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL2F,           0,      0 },
 {"gsdmodu",            "d,s,t",        0x7000001f, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              IL3A,           0,      0 },
 {"packsshb",           "D,S,T",        0x47400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packsshb",           "D,S,T",        0x4b400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packsswh",           "D,S,T",        0x47200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packsswh",           "D,S,T",        0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packsswh",           "D,S,T",        0x4b200002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"packushb",           "D,S,T",        0x47600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"packushb",           "D,S,T",        0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"packushb",           "D,S,T",        0x4b600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddb",              "D,S,T",        0x47c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddb",              "D,S,T",        0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddb",              "D,S,T",        0x4bc00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddb",              "d,s,t",        0x70000208, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddh",              "D,S,T",        0x47400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
 {"paddh",              "d,s,t",        0x70000108, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
-{"paddh",              "D,S,T",        0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddh",              "D,S,T",        0x4b400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddw",              "D,S,T",        0x47600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddw",              "D,S,T",        0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddw",              "D,S,T",        0x4b600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddw",              "d,s,t",        0x70000008, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddd",              "D,S,T",        0x47e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddd",              "D,S,T",        0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddd",              "D,S,T",        0x4be00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsb",             "D,S,T",        0x47800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddsb",             "D,S,T",        0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddsb",             "D,S,T",        0x4b800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsb",             "d,s,t",        0x70000608, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddsh",             "D,S,T",        0x47000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddsh",             "D,S,T",        0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddsh",             "D,S,T",        0x4b000000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddsh",             "d,s,t",        0x70000508, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"paddusb",            "D,S,T",        0x47a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddusb",            "D,S,T",        0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddusb",            "D,S,T",        0x4ba00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"paddush",            "D,S,T",        0x47200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"paddush",            "D,S,T",        0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"paddush",            "D,S,T",        0x4b200000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pandn",              "D,S,T",        0x47e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pandn",              "D,S,T",        0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pandn",              "D,S,T",        0x4be00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pavgb",              "D,S,T",        0x46600000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pavgb",              "D,S,T",        0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pavgb",              "D,S,T",        0x4b200008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pavgh",              "D,S,T",        0x46400000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pavgh",              "D,S,T",        0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pavgh",              "D,S,T",        0x4b000008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqb",            "D,S,T",        0x46c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqb",            "D,S,T",        0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqb",            "D,S,T",        0x4b800009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqh",            "D,S,T",        0x46800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqh",            "D,S,T",        0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqh",            "D,S,T",        0x4b400009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpeqw",            "D,S,T",        0x46400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpeqw",            "D,S,T",        0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpeqw",            "D,S,T",        0x4b000009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgtb",            "D,S,T",        0x46e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgtb",            "D,S,T",        0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgtb",            "D,S,T",        0x4ba00009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgth",            "D,S,T",        0x46a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgth",            "D,S,T",        0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgth",            "D,S,T",        0x4b600009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pcmpgtw",            "D,S,T",        0x46600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pcmpgtw",            "D,S,T",        0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pcmpgtw",            "D,S,T",        0x4b200009, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pextrh",             "D,S,T",        0x45c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pextrh",             "D,S,T",        0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pextrh",             "D,S,T",        0x4b40000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_0",           "D,S,T",        0x47800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_0",           "D,S,T",        0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_0",           "D,S,T",        0x4b800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_1",           "D,S,T",        0x47a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_1",           "D,S,T",        0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_1",           "D,S,T",        0x4ba00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_2",           "D,S,T",        0x47c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_2",           "D,S,T",        0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_2",           "D,S,T",        0x4bc00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pinsrh_3",           "D,S,T",        0x47e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pinsrh_3",           "D,S,T",        0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pinsrh_3",           "D,S,T",        0x4be00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaddhw",            "D,S,T",        0x45e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaddhw",            "D,S,T",        0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaddhw",            "D,S,T",        0x4b60000e, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaxsh",             "D,S,T",        0x46800000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaxsh",             "D,S,T",        0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaxsh",             "D,S,T",        0x4b400008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmaxub",             "D,S,T",        0x46c00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmaxub",             "D,S,T",        0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmaxub",             "D,S,T",        0x4b800008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pminsh",             "D,S,T",        0x46a00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pminsh",             "D,S,T",        0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pminsh",             "D,S,T",        0x4b600008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pminub",             "D,S,T",        0x46e00000, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pminub",             "D,S,T",        0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pminub",             "D,S,T",        0x4ba00008, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmovmskb",           "D,S",          0x46a00005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"pmovmskb",           "D,S",          0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2F|IL3A,      0,      0 },
+{"pmovmskb",           "D,S",          0x4ba0000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              0,              LMMI,   0 },
 {"pmulhuh",            "D,S,T",        0x46e00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmulhuh",            "D,S,T",        0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmulhuh",            "D,S,T",        0x4ba0000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmulhh",             "D,S,T",        0x46a00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmulhh",             "D,S,T",        0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmulhh",             "D,S,T",        0x4b60000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmullh",             "D,S,T",        0x46800002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmullh",             "D,S,T",        0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmullh",             "D,S,T",        0x4b40000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pmuluw",             "D,S,T",        0x46c00002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pmuluw",             "D,S,T",        0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pmuluw",             "D,S,T",        0x4b80000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"pasubub",            "D,S,T",        0x45a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pasubub",            "D,S,T",        0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pasubub",            "D,S,T",        0x4b20000d, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"biadd",              "D,S",          0x46800005, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2E,           0,      0 },
-{"biadd",              "D,S",          0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              IL2F|IL3A,      0,      0 },
+{"biadd",              "D,S",          0x4b80000f, 0xffff003f, WR_1|RD_2|FP_D,         0,              0,              LMMI,   0 },
 {"pshufh",             "D,S,T",        0x47000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"pshufh",             "D,S,T",        0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"pshufh",             "D,S,T",        0x4b000002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllh",              "D,S,T",        0x46600002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psllh",              "D,S,T",        0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psllh",              "D,S,T",        0x4b20000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllh",              "d,t,<",        0x70000034, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psllw",              "D,S,T",        0x46400002, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psllw",              "D,S,T",        0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psllw",              "D,S,T",        0x4b00000a, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psllw",              "d,t,<",        0x7000003c, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrah",              "D,S,T",        0x46a00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrah",              "D,S,T",        0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrah",              "D,S,T",        0x4b60000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrah",              "d,t,<",        0x70000037, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psraw",              "D,S,T",        0x46800003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psraw",              "D,S,T",        0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psraw",              "D,S,T",        0x4b40000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psraw",              "d,t,<",        0x7000003f, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrlh",              "D,S,T",        0x46600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrlh",              "D,S,T",        0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrlh",              "D,S,T",        0x4b20000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrlh",              "d,t,<",        0x70000036, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psrlw",              "D,S,T",        0x46400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psrlw",              "D,S,T",        0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psrlw",              "D,S,T",        0x4b00000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psrlw",              "d,t,<",        0x7000003e, 0xffe0003f, WR_1|RD_2,              0,              MMI,            0,      0 },
 {"psubb",              "D,S,T",        0x47c00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubb",              "D,S,T",        0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubb",              "D,S,T",        0x4bc00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubb",              "d,s,t",        0x70000248, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubh",              "D,S,T",        0x47400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubh",              "D,S,T",        0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubh",              "D,S,T",        0x4b400001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubh",              "d,s,t",        0x70000148, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubw",              "D,S,T",        0x47600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubw",              "D,S,T",        0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubw",              "D,S,T",        0x4b600001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubw",              "d,s,t",        0x70000048, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubd",              "D,S,T",        0x47e00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubd",              "D,S,T",        0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubd",              "D,S,T",        0x4be00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsb",             "D,S,T",        0x47800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubsb",             "D,S,T",        0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubsb",             "D,S,T",        0x4b800001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsb",             "d,s,t",        0x70000648, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubsh",             "D,S,T",        0x47000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubsh",             "D,S,T",        0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubsh",             "D,S,T",        0x4b000001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubsh",             "d,s,t",        0x70000548, 0xfc0007ff, WR_1|RD_2|RD_3,         0,              MMI,            0,      0 },
 {"psubusb",            "D,S,T",        0x47a00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubusb",            "D,S,T",        0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubusb",            "D,S,T",        0x4ba00001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"psubush",            "D,S,T",        0x47200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"psubush",            "D,S,T",        0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"psubush",            "D,S,T",        0x4b200001, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhbh",          "D,S,T",        0x47600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhbh",          "D,S,T",        0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhbh",          "D,S,T",        0x4b600003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhhw",          "D,S,T",        0x47200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhhw",          "D,S,T",        0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhhw",          "D,S,T",        0x4b200003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpckhwd",          "D,S,T",        0x46e00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpckhwd",          "D,S,T",        0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpckhwd",          "D,S,T",        0x4ba0000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklbh",          "D,S,T",        0x47400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklbh",          "D,S,T",        0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklbh",          "D,S,T",        0x4b400003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklhw",          "D,S,T",        0x47000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklhw",          "D,S,T",        0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklhw",          "D,S,T",        0x4b000003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"punpcklwd",          "D,S,T",        0x46c00003, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2E,           0,      0 },
-{"punpcklwd",          "D,S,T",        0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              IL2F|IL3A,      0,      0 },
+{"punpcklwd",          "D,S,T",        0x4b80000b, 0xffe0003f, WR_1|RD_2|RD_3|FP_D,    0,              0,              LMMI,   0 },
 {"sequ",               "S,T",          0x46800032, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2E,           0,      0 },
-{"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              IL2F|IL3A,      0,      0 },
+{"sequ",               "S,T",          0x4b80000c, 0xffe007ff, RD_1|RD_2|WR_CC|FP_D,   0,              0,              LMMI,   0 },
 /* MIPS Enhanced VA Scheme */
 {"lbue",               "t,+j(b)",      0x7c000028, 0xfc00007f, WR_1|RD_3|LM,           0,              0,              EVA,    0 },
 {"lbue",               "t,A(b)",       0,    (int) M_LBUE_AB,  INSN_MACRO,             0,              0,              EVA,    0 },
@@ -3150,6 +3169,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"ctcmsa",             "+l,d",         0x783e0019, 0xffff003f, RD_2|CM,                0,              0,              MSA,    0 },
 {"cfcmsa",             "+k,+n",        0x787e0019, 0xffff003f, WR_1|CM,                0,              0,              MSA,    0 },
 {"move.v",             "+d,+e",        0x78be0019, 0xffff003f, WR_1|RD_2,              0,              0,              MSA,    0 },
+{"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I37,            MSA,    0 },
+{"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I69,            MSA64,  0 },
+
+/* interAptiv MR2 instruction extensions.  */
+{"restore",            "-m",           0x7000001f, 0xfc00603f, WR_31|NODS,             MOD_SP,         IAMR2,          0,      0 },
+{"save",               "-m",           0x7000201f, 0xfc00603f, NODS,                   RD_31|MOD_SP,   IAMR2,          0,      0 },
 
 /* User Defined Instruction.  */
 {"udi0",               "s,t,d,+1",     0x70000010, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
@@ -3216,10 +3241,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"udi15",              "s,t,+2",       0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
 {"udi15",              "s,+3",         0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
 {"udi15",              "+4",           0x7000001f, 0xfc00003f, UDI,                    0,              I33,            0,      0 },
-{"lsa",                        "d,v,t,+~",     0x00000005, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I37,            MSA,    0 },
-{"dlsa",               "d,v,t,+~",     0x00000015, 0xfc00073f, WR_1|RD_2|RD_3,         0,              I69,            MSA64,  0 },
-/* MIPS r6.  */
 
+/* MIPS r6.  */
 {"aui",                        "t,s,u",        0x3c000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
 {"auipc",              "s,u",          0xec1e0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
 {"daui",               "t,s,u",        0x74000000, 0xfc000000, WR_1|RD_2,              0,              I37,            0,      0 },
@@ -3335,6 +3358,20 @@ const struct mips_opcode mips_builtin_opcodes[] =
 
 {"aluipc",             "s,u",          0xec1f0000, 0xfc1f0000, WR_1,                   RD_pc,          I37,            0,      0 },
 
+/* MIPS cyclic redundancy check (CRC) ASE.  */
+{"crc32b",             "t,s,-d",       0x7c00000f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32h",             "t,s,-d",       0x7c00004f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32w",             "t,s,-d",       0x7c00008f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32d",             "t,s,-d",       0x7c0000cf, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC64,  0 },
+{"crc32cb",            "t,s,-d",       0x7c00010f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32ch",            "t,s,-d",       0x7c00014f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32cw",            "t,s,-d",       0x7c00018f, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC,    0 },
+{"crc32cd",            "t,s,-d",       0x7c0001cf, 0xfc00ffff, MOD_1|RD_2,             0,              0,              CRC64,  0 },
+
+/* MIPS Global INValidate (GINV) ASE.  */
+{"ginvi",              "s",            0x7c00003d, 0xfc1fffff, RD_1,                   0,              0,              GINV,   0 },
+{"ginvt",              "s,+\\",        0x7c0000bd, 0xfc1ffcff, RD_1,                   0,              0,              GINV,   0 },
+
 /* No hazard protection on coprocessor instructions--they shouldn't
    change the state of the processor and if they do it's up to the
    user to put in nops as necessary.  These are at the end so that the