rename CFG_ macros to CONFIG_SYS

[people/ms/u-boot.git] / post / cpu / ppc4xx / ether.c

diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c
index 45f292b92fec17679381a9f3ba900a6b1c1a99b9..e40e19be235faf48d1288317a14eb05b5be6e130 100644 (file)
--- a/post/cpu/ppc4xx/ether.c
+++ b/post/cpu/ppc4xx/ether.c
@@ -37,11 +37,9 @@
  *   TEST_NUM - number of tests
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_ETHER
+#if CONFIG_POST & CONFIG_SYS_POST_ETHER
 
 #include <asm/cache.h>
 #include <asm/io.h>
@@ -117,11 +115,11 @@ static void ether_post_init (int devnum, int hw_addr)
        sync ();
 #endif
        /* reset emac */
-       out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+       out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
        sync ();
 
        for (i = 0;; i++) {
-               if (!(in32 (EMAC_M0 + hw_addr) & EMAC_M0_SRST))
+               if (!(in_be32 ((void*)(EMAC_M0 + hw_addr)) & EMAC_M0_SRST))
                        break;
                if (i >= 1000) {
                        printf ("Timeout resetting EMAC\n");
@@ -144,7 +142,7 @@ static void ether_post_init (int devnum, int hw_addr)
        else
                mode_reg |= EMAC_M1_OBCI_GT100;
 
-       out32 (EMAC_M1 + hw_addr, mode_reg);
+       out_be32 ((void*)(EMAC_M1 + hw_addr), mode_reg);
 
 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
 
@@ -169,6 +167,8 @@ static void ether_post_init (int devnum, int hw_addr)
        rx.ctrl = MAL_TX_CTRL_WRAP | MAL_RX_CTRL_EMPTY;
        rx.data_len = 0;
        rx.data_ptr = (char*)L1_CACHE_ALIGN((u32)rx_buf);
+       flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
+       flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
 
        switch (devnum) {
        case 1:
@@ -209,41 +209,41 @@ static void ether_post_init (int devnum, int hw_addr)
        mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum));
 
        /* set internal loopback mode */
-#ifdef CFG_POST_ETHER_EXT_LOOPBACK
-       out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 |
-              EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
-              EMAC_M1_MF_100MBPS | EMAC_M1_IST |
-              in32 (EMAC_M1));
+#ifdef CONFIG_SYS_POST_ETHER_EXT_LOOPBACK
+       out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | 0 |
+                 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+                 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+                 in_be32 ((void*)(EMAC_M1 + hw_addr)));
 #else
-       out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE |
-              EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
-              EMAC_M1_MF_100MBPS | EMAC_M1_IST |
-              in32 (EMAC_M1));
+       out_be32 ((void*)(EMAC_M1 + hw_addr), EMAC_M1_FDE | EMAC_M1_ILE |
+                 EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K |
+                 EMAC_M1_MF_100MBPS | EMAC_M1_IST |
+                 in_be32 ((void*)(EMAC_M1 + hw_addr)));
 #endif
 
        /* set transmit enable & receive enable */
-       out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE);
+       out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_TXE | EMAC_M0_RXE);
 
        /* enable broadcast address */
-       out32 (EMAC_RXM + hw_addr, EMAC_RMR_BAE);
+       out_be32 ((void*)(EMAC_RXM + hw_addr), EMAC_RMR_BAE);
 
        /* set transmit request threshold register */
-       out32 (EMAC_TRTR + hw_addr, 0x18000000);        /* 256 byte threshold */
+       out_be32 ((void*)(EMAC_TRTR + hw_addr), 0x18000000);    /* 256 byte threshold */
 
        /* set receive  low/high water mark register */
 #if defined(CONFIG_440)
        /* 440s has a 64 byte burst length */
-       out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x80009000);
+       out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x80009000);
 #else
        /* 405s have a 16 byte burst length */
-       out32 (EMAC_RX_HI_LO_WMARK + hw_addr, 0x0f002000);
+       out_be32 ((void*)(EMAC_RX_HI_LO_WMARK + hw_addr), 0x0f002000);
 #endif /* defined(CONFIG_440) */
-       out32 (EMAC_TXM1 + hw_addr, 0xf8640000);
+       out_be32 ((void*)(EMAC_TXM1 + hw_addr), 0xf8640000);
 
        /* Set fifo limit entry in tx mode 0 */
-       out32 (EMAC_TXM0 + hw_addr, 0x00000003);
+       out_be32 ((void*)(EMAC_TXM0 + hw_addr), 0x00000003);
        /* Frame gap set */
-       out32 (EMAC_I_FRAME_GAP_REG + hw_addr, 0x00000008);
+       out_be32 ((void*)(EMAC_I_FRAME_GAP_REG + hw_addr), 0x00000008);
        sync ();
 }
 
@@ -270,7 +270,7 @@ static void ether_post_halt (int devnum, int hw_addr)
                udelay (1000);
        }
        /* emac reset */
-       out32 (EMAC_M0 + hw_addr, EMAC_M0_SRST);
+       out_be32 ((void*)(EMAC_M0 + hw_addr), EMAC_M0_SRST);
 
 #if defined(CONFIG_440SPE) || defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
        /* remove clocks for EMAC internal loopback  */
@@ -290,14 +290,17 @@ static void ether_post_send (int devnum, int hw_addr, void *packet, int length)
                        return;
                }
                udelay (1000);
+               invalidate_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
        }
        tx.ctrl = MAL_TX_CTRL_READY | MAL_TX_CTRL_WRAP | MAL_TX_CTRL_LAST |
                EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP;
        tx.data_len = length;
        memcpy (tx.data_ptr, packet, length);
+       flush_dcache_range((u32)&tx, (u32)&tx + sizeof(mal_desc_t));
+       flush_dcache_range((u32)tx.data_ptr, (u32)tx.data_ptr + length);
        sync ();
 
-       out32 (EMAC_TXM0 + hw_addr, in32 (EMAC_TXM0 + hw_addr) | EMAC_TXM0_GNP0);
+       out_be32 ((void*)(EMAC_TXM0 + hw_addr), in_be32 ((void*)(EMAC_TXM0 + hw_addr)) | EMAC_TXM0_GNP0);
        sync ();
 }
 
@@ -312,13 +315,17 @@ static int ether_post_recv (int devnum, int hw_addr, void *packet, int max_lengt
                        return 0;
                }
                udelay (1000);
+               invalidate_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
        }
        length = rx.data_len - 4;
-       if (length <= max_length)
+       if (length <= max_length) {
+               invalidate_dcache_range((u32)rx.data_ptr, (u32)rx.data_ptr + length);
                memcpy(packet, rx.data_ptr, length);
+       }
        sync ();
 
        rx.ctrl |= MAL_RX_CTRL_EMPTY;
+       flush_dcache_range((u32)&rx, (u32)&rx + sizeof(mal_desc_t));
        sync ();
 
        return length;
@@ -399,8 +406,8 @@ int ether_post_test (int flags)
        int i;
 
        /* Allocate tx & rx packet buffers */
-       tx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
-       rx_buf = malloc (PKTSIZE_ALIGN + CFG_CACHELINE_SIZE);
+       tx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
+       rx_buf = malloc (PKTSIZE_ALIGN + CONFIG_SYS_CACHELINE_SIZE);
 
        if (!tx_buf || !rx_buf) {
                printf ("Failed to allocate packet buffers\n");
@@ -420,5 +427,4 @@ out_free:
        return res;
 }
 
-#endif /* CONFIG_POST & CFG_POST_ETHER */
-#endif /* CONFIG_POST */
+#endif /* CONFIG_POST & CONFIG_SYS_POST_ETHER */