post: use ARRAY_SIZE

[people/ms/u-boot.git] / post / cpu / ppc4xx / spr.c

diff --git a/post/cpu/ppc4xx/spr.c b/post/cpu/ppc4xx/spr.c
index f62526a1716e9f60f071228dedb8f00668894440..3f5e96593a47a75afd95e13ae21dd19c325337e7 100644 (file)
--- a/post/cpu/ppc4xx/spr.c
+++ b/post/cpu/ppc4xx/spr.c
@@ -2,6 +2,8 @@
  * (C) Copyright 2007
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * Author: Igor Lisitsin <igor@emcraft.com>
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -33,18 +35,23 @@
  * corresponding table value.
  */
 
-#ifdef CONFIG_POST
-
 #include <post.h>
 
-#if CONFIG_POST & CFG_POST_SPR
+#if CONFIG_POST & CONFIG_SYS_POST_SPR
 
-static struct
-{
-    int number;
-    char * name;
-    unsigned long mask;
-    unsigned long value;
+#include <asm/processor.h>
+
+#ifdef CONFIG_4xx_DCACHE
+#include <asm/mmu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+#endif
+
+static struct {
+       int number;
+       char * name;
+       unsigned long mask;
+       unsigned long value;
 } spr_test_list [] = {
        /* Standard Special-Purpose Registers */
 
@@ -60,14 +67,18 @@ static struct
        {0x113, "SPRG3",        0x00000000,     0x00000000},
        {0x11f, "PVR",          0x00000000,     0x00000000},
 
-       /* Additional Special-Purpose Registers */
-
+       /* Additional Special-Purpose Registers.
+        * The values must match the initialization
+        * values from arch/powerpc/cpu/ppc4xx/start.S
+        */
        {0x30,  "PID",          0x00000000,     0x00000000},
        {0x3a,  "CSRR0",        0x00000000,     0x00000000},
        {0x3b,  "CSRR1",        0x00000000,     0x00000000},
        {0x3d,  "DEAR",         0x00000000,     0x00000000},
        {0x3e,  "ESR",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x3f,  "IVPR",         0xffff0000,     0x00000000},
+#endif
        {0x100, "USPRG0",       0x00000000,     0x00000000},
        {0x104, "SPRG4",        0x00000000,     0x00000000},
        {0x105, "SPRG5",        0x00000000,     0x00000000},
@@ -75,7 +86,9 @@ static struct
        {0x107, "SPRG7",        0x00000000,     0x00000000},
        {0x10c, "TBL",          0x00000000,     0x00000000},
        {0x10d, "TBU",          0x00000000,     0x00000000},
+#ifdef CONFIG_440
        {0x11e, "PIR",          0x0000000f,     0x00000000},
+#endif
        {0x130, "DBSR",         0x00000000,     0x00000000},
        {0x134, "DBCR0",        0x00000000,     0x00000000},
        {0x135, "DBCR1",        0x00000000,     0x00000000},
@@ -90,22 +103,24 @@ static struct
        {0x13f, "DVC2",         0x00000000,     0x00000000},
        {0x150, "TSR",          0x00000000,     0x00000000},
        {0x154, "TCR",          0x00000000,     0x00000000},
-       {0x190, "IVOR0",        0x00000000,     0x00000000},
-       {0x191, "IVOR1",        0x00000000,     0x00000000},
-       {0x192, "IVOR2",        0x00000000,     0x00000000},
-       {0x193, "IVOR3",        0x00000000,     0x00000000},
-       {0x194, "IVOR4",        0x00000000,     0x00000000},
-       {0x195, "IVOR5",        0x00000000,     0x00000000},
-       {0x196, "IVOR6",        0x00000000,     0x00000000},
-       {0x197, "IVOR7",        0x00000000,     0x00000000},
-       {0x198, "IVOR8",        0x00000000,     0x00000000},
+#ifdef CONFIG_440
+       {0x190, "IVOR0",        0x0000fff0,     0x00000100},
+       {0x191, "IVOR1",        0x0000fff0,     0x00000200},
+       {0x192, "IVOR2",        0x0000fff0,     0x00000300},
+       {0x193, "IVOR3",        0x0000fff0,     0x00000400},
+       {0x194, "IVOR4",        0x0000fff0,     0x00000500},
+       {0x195, "IVOR5",        0x0000fff0,     0x00000600},
+       {0x196, "IVOR6",        0x0000fff0,     0x00000700},
+       {0x197, "IVOR7",        0x0000fff0,     0x00000800},
+       {0x198, "IVOR8",        0x0000fff0,     0x00000c00},
        {0x199, "IVOR9",        0x00000000,     0x00000000},
-       {0x19a, "IVOR10",       0x00000000,     0x00000000},
+       {0x19a, "IVOR10",       0x0000fff0,     0x00000900},
        {0x19b, "IVOR11",       0x00000000,     0x00000000},
        {0x19c, "IVOR12",       0x00000000,     0x00000000},
-       {0x19d, "IVOR13",       0x00000000,     0x00000000},
-       {0x19e, "IVOR14",       0x00000000,     0x00000000},
-       {0x19f, "IVOR15",       0x00000000,     0x00000000},
+       {0x19d, "IVOR13",       0x0000fff0,     0x00001300},
+       {0x19e, "IVOR14",       0x0000fff0,     0x00001400},
+       {0x19f, "IVOR15",       0x0000fff0,     0x00002000},
+#endif
        {0x23a, "MCSRR0",       0x00000000,     0x00000000},
        {0x23b, "MCSRR1",       0x00000000,     0x00000000},
        {0x23c, "MCSR",         0x00000000,     0x00000000},
@@ -126,8 +141,10 @@ static struct
        {0x395, "DTV1",         0x00000000,     0x00000000},
        {0x396, "DTV2",         0x00000000,     0x00000000},
        {0x397, "DTV3",         0x00000000,     0x00000000},
-       {0x398, "DVLIM",        0x00000000,     0x00000000},
-       {0x399, "IVLIM",        0x00000000,     0x00000000},
+#ifdef CONFIG_440
+       {0x398, "DVLIM",        0x0fc1f83f,     0x0001f800},
+       {0x399, "IVLIM",        0x0fc1f83f,     0x0001f800},
+#endif
        {0x39b, "RSTCFG",       0x00000000,     0x00000000},
        {0x39c, "DCDBTRL",      0x00000000,     0x00000000},
        {0x39d, "DCDBTRH",      0x00000000,     0x00000000},
@@ -139,8 +156,7 @@ static struct
        {0x3f3, "DBDR",         0x00000000,     0x00000000},
 };
 
-static int spr_test_list_size =
-               sizeof (spr_test_list) / sizeof (spr_test_list[0]);
+static int spr_test_list_size = ARRAY_SIZE(spr_test_list);
 
 int spr_post_test (int flags)
 {
@@ -153,6 +169,10 @@ int spr_post_test (int flags)
        };
        unsigned long (*get_spr) (void) = (void *) code;
 
+#ifdef CONFIG_4xx_DCACHE
+       /* disable cache */
+       change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
        for (i = 0; i < spr_test_list_size; i++) {
                int num = spr_test_list[i].number;
 
@@ -169,8 +189,12 @@ int spr_post_test (int flags)
                        ret = -1;
                }
        }
+#ifdef CONFIG_4xx_DCACHE
+       /* enable cache */
+       change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
 
        return ret;
 }
-#endif /* CONFIG_POST & CFG_POST_SPR */
-#endif /* CONFIG_POST */
+
+#endif /* CONFIG_POST & CONFIG_SYS_POST_SPR */