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- $(am__EXEEXT_4) $(am__EXEEXT_5) $(am__EXEEXT_6) \
- $(am__EXEEXT_7)
+check_PROGRAMS = $(am__EXEEXT_9) $(am__EXEEXT_10)
+noinst_PROGRAMS = $(am__EXEEXT_11) $(am__EXEEXT_12) $(am__EXEEXT_13) \
+ $(am__EXEEXT_14) $(am__EXEEXT_15) $(am__EXEEXT_16) \
+ $(am__EXEEXT_17) $(am__EXEEXT_18) $(am__EXEEXT_19) \
+ $(am__EXEEXT_20) $(am__EXEEXT_21) $(am__EXEEXT_22) \
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+ $(am__EXEEXT_41) $(am__EXEEXT_42)
+EXTRA_PROGRAMS = $(am__EXEEXT_1) testsuite/common/bits-gen$(EXEEXT) \
+ testsuite/common/fpu-tst$(EXEEXT) $(am__EXEEXT_2) \
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+ $(am__EXEEXT_7) $(am__EXEEXT_8)
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@ENABLE_SIM_TRUE@ $(srcroot)/include/sim/callback.h \
@ENABLE_SIM_TRUE@ $(srcroot)/include/sim/sim.h
@SIM_ENABLE_HW_TRUE@ $(SIM_COMMON_HW_OBJS) \
@SIM_ENABLE_HW_TRUE@ $(SIM_HW_SOCKSER)
-@SIM_ENABLE_IGEN_TRUE@am__append_3 = igen/libigen.a
-@SIM_ENABLE_IGEN_TRUE@am__append_4 = $(igen_IGEN_TOOLS)
-@SIM_ENABLE_IGEN_TRUE@am__append_5 = $(igen_IGEN_TOOLS)
TESTS = testsuite/common/bits32m0$(EXEEXT) \
testsuite/common/bits32m31$(EXEEXT) \
testsuite/common/bits64m0$(EXEEXT) \
testsuite/common/bits64m63$(EXEEXT) \
testsuite/common/alu-tst$(EXEEXT)
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_6 = aarch64/libsim.a
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_7 = aarch64/run
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_8 = arm/libsim.a
-@SIM_ENABLE_ARCH_arm_TRUE@am__append_9 = arm/run
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_10 = avr/libsim.a
-@SIM_ENABLE_ARCH_avr_TRUE@am__append_11 = avr/run
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_12 = bfin/libsim.a
-@SIM_ENABLE_ARCH_bfin_TRUE@am__append_13 = bfin/run
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_14 = bpf/libsim.a
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_15 = bpf/run
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_16 = \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-le.h \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/eng-be.h
-
-@SIM_ENABLE_ARCH_bpf_TRUE@am__append_17 = $(bpf_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = cr16/libsim.a
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_19 = cr16/run
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_20 = cr16/simops.h
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_21 = cr16/gencode
-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_22 = $(cr16_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/libsim.a
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = cris/run
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_25 = cris/rvdummy
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_26 = \
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_3 = aarch64/libsim.a
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__append_4 = aarch64/run
+@SIM_ENABLE_ARCH_arm_TRUE@am__append_5 = arm/libsim.a
+@SIM_ENABLE_ARCH_arm_TRUE@am__append_6 = arm/run
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_7 = avr/libsim.a
+@SIM_ENABLE_ARCH_avr_TRUE@am__append_8 = avr/run
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_9 = bfin/libsim.a
+@SIM_ENABLE_ARCH_bfin_TRUE@am__append_10 = bfin/run
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_11 = bpf/libsim.a
+@SIM_ENABLE_ARCH_bpf_TRUE@am__append_12 = bpf/run
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_13 = cr16/libsim.a
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_14 = cr16/run
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/simops.h
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_16 = cr16/gencode
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
+@SIM_ENABLE_ARCH_cr16_TRUE@am__append_18 = $(cr16_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_19 = cris/libsim.a
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_20 = cris/run
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_21 = cris/rvdummy
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_22 = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
-@SIM_ENABLE_ARCH_cris_TRUE@am__append_27 = $(cris_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/libsim.a
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/run
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = d10v/simops.h
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_31 = d10v/gencode
-@SIM_ENABLE_ARCH_d10v_TRUE@am__append_32 = $(d10v_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = erc32/libsim.a
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = erc32/run erc32/sis
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_35 = sim-%D-install-exec-local
-@SIM_ENABLE_ARCH_erc32_TRUE@am__append_36 = sim-erc32-uninstall-local
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_37 = example-synacor/libsim.a
-@SIM_ENABLE_ARCH_examples_TRUE@am__append_38 = example-synacor/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/libsim.a
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = frv/run
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = frv/eng.h
-@SIM_ENABLE_ARCH_frv_TRUE@am__append_42 = $(frv_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 = ft32/libsim.a
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_44 = ft32/run
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 = h8300/libsim.a
-@SIM_ENABLE_ARCH_h8300_TRUE@am__append_46 = h8300/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/libsim.a
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = iq2000/run
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/engv10.h cris/engv32.h
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_26 = d10v/run
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_29 = d10v/simops.h
+@SIM_ENABLE_ARCH_d10v_TRUE@am__append_30 = $(d10v_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_31 = erc32/libsim.a
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_32 = erc32/run erc32/sis
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_33 = sim-%D-install-exec-local
+@SIM_ENABLE_ARCH_erc32_TRUE@am__append_34 = sim-erc32-uninstall-local
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_35 = example-synacor/libsim.a
+@SIM_ENABLE_ARCH_examples_TRUE@am__append_36 = example-synacor/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_37 = frv/libsim.a
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_38 = frv/run
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_39 = frv/eng.h
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_40 = frv/eng.h
+@SIM_ENABLE_ARCH_frv_TRUE@am__append_41 = $(frv_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_42 = ft32/libsim.a
+@SIM_ENABLE_ARCH_ft32_TRUE@am__append_43 = ft32/run
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_44 = h8300/libsim.a
+@SIM_ENABLE_ARCH_h8300_TRUE@am__append_45 = h8300/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/libsim.a
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = iq2000/run
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_48 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_49 = iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_50 = $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = lm32/libsim.a
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_52 = lm32/run
@SIM_ENABLE_ARCH_lm32_TRUE@am__append_53 = lm32/eng.h
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 = $(lm32_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 = m32c/libsim.a
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/run
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 = \
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_54 = lm32/eng.h
+@SIM_ENABLE_ARCH_lm32_TRUE@am__append_55 = $(lm32_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_56 = m32c/libsim.a
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_57 = m32c/run
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_58 = m32c/opc2c
+@SIM_ENABLE_ARCH_m32c_TRUE@am__append_59 = \
@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/r8c.c.log
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 = m32r/libsim.a
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = m32r/run
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_60 = m32r/libsim.a
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_61 = m32r/run
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng2.h
-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_62 = $(m32r_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_63 = m68hc11/libsim.a
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_64 = m68hc11/run
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/gencode
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = $(m68hc11_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_67 = mcore/libsim.a
-@SIM_ENABLE_ARCH_mcore_TRUE@am__append_68 = mcore/run
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_69 = microblaze/libsim.a
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_70 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_71 = \
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_63 = m32r/eng.h m32r/engx.h m32r/eng2.h
+@SIM_ENABLE_ARCH_m32r_TRUE@am__append_64 = $(m32r_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_65 = m68hc11/libsim.a
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_66 = m68hc11/run
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_67 = m68hc11/gencode
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__append_68 = $(m68hc11_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_69 = mcore/libsim.a
+@SIM_ENABLE_ARCH_mcore_TRUE@am__append_70 = mcore/run
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_71 = microblaze/libsim.a
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_72 = microblaze/run
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_73 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/engine.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/irun.o
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_72 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_74 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_support.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_semantics.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16_idecode.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/m16run.o
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_73 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_75 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_OBJ) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_74 = mips/libsim.a
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_75 = mips/run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/itable.h \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_76 = mips/libsim.a
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = mips/run
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/itable.h \
@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_77 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_79 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_SINGLE) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@ mips/stamp-gen-mode-single
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_78 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_80 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M16) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ $(mips_BUILT_SRC_FROM_GEN_MODE_M16_M32) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m16 \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@ mips/stamp-gen-mode-m16-m32
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_79 = \
+@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_81 = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-igen \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_80 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_81 = mips/multi-include.h mips/multi-run.c
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 = mn10300/libsim.a
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_83 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = $(mips_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_83 = mips/multi-include.h mips/multi-run.c
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_84 = mn10300/libsim.a
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = mn10300/run
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_86 = \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_85 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_86 = moxie/libsim.a
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_87 = moxie/run
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_88 = msp430/libsim.a
-@SIM_ENABLE_ARCH_msp430_TRUE@am__append_89 = msp430/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 = or1k/libsim.a
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_91 = or1k/run
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/eng.h
-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_94 = common/libcommon.a
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_95 = ppc/run ppc/psim
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_96 = pru/libsim.a
-@SIM_ENABLE_ARCH_pru_TRUE@am__append_97 = pru/run
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_98 = riscv/libsim.a
-@SIM_ENABLE_ARCH_riscv_TRUE@am__append_99 = riscv/run
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_100 = rl78/libsim.a
-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_101 = rl78/run
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_102 = rx/libsim.a
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_103 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = sh/libsim.a
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_106 = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_88 = moxie/libsim.a
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 = msp430/libsim.a
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/libsim.a
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_93 = or1k/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/libsim.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/defines.h ppc/icache.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h ppc/semantics.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h ppc/support.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h ppc/hw.h
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/defines.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-defines \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILD_OUTPUTS) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_IGEN_TOOLS) ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_101 = ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_102 = $(ppc_IGEN_TOOLS)
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_103 = pru/libsim.a
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_104 = pru/run
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_105 = riscv/libsim.a
+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 = rl78/libsim.a
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+@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 = rx/libsim.a
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/libsim.a
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_107 = sh/gencode
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-@SIM_ENABLE_ARCH_v850_TRUE@am__append_110 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_111 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
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+@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_112 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/m4/sim_ac_option_warnings.m4 \
$(top_srcdir)/m4/sim_ac_platform.m4 \
$(top_srcdir)/m4/sim_ac_toolchain.m4 \
+ $(top_srcdir)/../gdbsupport/libiberty.m4 \
$(top_srcdir)/frv/acinclude.m4 $(top_srcdir)/mips/acinclude.m4 \
+ $(top_srcdir)/ppc/acinclude.m4 \
$(top_srcdir)/riscv/acinclude.m4 $(top_srcdir)/rx/acinclude.m4 \
$(top_srcdir)/configure.ac
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
mips/.gdbinit mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit \
or1k/.gdbinit ppc/.gdbinit pru/.gdbinit riscv/.gdbinit \
rl78/.gdbinit rx/.gdbinit sh/.gdbinit erc32/.gdbinit \
- v850/.gdbinit example-synacor/.gdbinit arch-subdir.mk .gdbinit
+ v850/.gdbinit example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_VPATH_FILES =
LIBRARIES = $(noinst_LIBRARIES)
ARFLAGS = cru
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/simulator.o
am__dirstamp = $(am__leading_dot)dirstamp
am__objects_1 = common/callback.$(OBJEXT) common/portability.$(OBJEXT) \
- common/sim-load.$(OBJEXT) common/syscall.$(OBJEXT) \
- common/target-newlib-errno.$(OBJEXT) \
+ common/sim-load.$(OBJEXT) common/sim-signal.$(OBJEXT) \
+ common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
common/target-newlib-open.$(OBJEXT) \
common/target-newlib-signal.$(OBJEXT) \
common/target-newlib-syscall.$(OBJEXT) \
bfin_libsim_a_OBJECTS = $(am_bfin_libsim_a_OBJECTS) \
$(nodist_bfin_libsim_a_OBJECTS)
bpf_libsim_a_AR = $(AR) $(ARFLAGS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = $(patsubst \
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = bpf/bpf-sim.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
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-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o bpf/cgen-utils.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o bpf/cpu.o bpf/decode-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o bpf/sem-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o bpf/mloop-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o bpf/bpf.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o bpf/sim-if.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
@SIM_ENABLE_ARCH_bpf_TRUE@am_bpf_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.$(OBJEXT)
common_libcommon_a_LIBADD =
am_common_libcommon_a_OBJECTS = common/callback.$(OBJEXT) \
common/portability.$(OBJEXT) common/sim-load.$(OBJEXT) \
- common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
+ common/sim-signal.$(OBJEXT) common/syscall.$(OBJEXT) \
+ common/target-newlib-errno.$(OBJEXT) \
common/target-newlib-open.$(OBJEXT) \
common/target-newlib-signal.$(OBJEXT) \
common/target-newlib-syscall.$(OBJEXT) \
$(nodist_h8300_libsim_a_OBJECTS)
igen_libigen_a_AR = $(AR) $(ARFLAGS)
igen_libigen_a_LIBADD =
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-@SIM_ENABLE_IGEN_TRUE@ igen/table.$(OBJEXT) igen/lf.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/misc.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/filter_host.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/ld-decode.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/ld-cache.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/filter.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/ld-insn.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-model.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-itable.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-icache.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-semantics.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-idecode.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-support.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen-engine.$(OBJEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen.$(OBJEXT)
+am_igen_libigen_a_OBJECTS = igen/table.$(OBJEXT) igen/lf.$(OBJEXT) \
+ igen/misc.$(OBJEXT) igen/filter_host.$(OBJEXT) \
+ igen/ld-decode.$(OBJEXT) igen/ld-cache.$(OBJEXT) \
+ igen/filter.$(OBJEXT) igen/ld-insn.$(OBJEXT) \
+ igen/gen-model.$(OBJEXT) igen/gen-itable.$(OBJEXT) \
+ igen/gen-icache.$(OBJEXT) igen/gen-semantics.$(OBJEXT) \
+ igen/gen-idecode.$(OBJEXT) igen/gen-support.$(OBJEXT) \
+ igen/gen-engine.$(OBJEXT) igen/gen.$(OBJEXT)
igen_libigen_a_OBJECTS = $(am_igen_libigen_a_OBJECTS)
iq2000_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000_libsim_a_DEPENDENCIES = \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__DEPENDENCIES_2 = $(am__DEPENDENCIES_1) \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
-@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_71) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) \
+@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
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or1k_libsim_a_OBJECTS = $(am_or1k_libsim_a_OBJECTS) \
$(nodist_or1k_libsim_a_OBJECTS)
+ppc_libigen_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_DEPENDENCIES = igen/filter.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o igen/lf.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o
+@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libigen_a_OBJECTS = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/table.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.$(OBJEXT)
+ppc_libigen_a_OBJECTS = $(am_ppc_libigen_a_OBJECTS)
+ppc_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_DEPENDENCIES = ppc/debug.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o ppc/sim-endian.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o ppc/emul_generic.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o ppc/emul_chirp.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o ppc/emul_unix.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o ppc/vm.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o ppc/model.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o ppc/cpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o ppc/events.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o ppc/device.o ppc/tree.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o ppc/itable.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o ppc/icache.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o ppc/idecode.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o ppc/sim-fpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o ppc/pk_disklabel.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_ppc_TRUE@ %,ppc/%,$(sim_ppc_hw_obj)) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o ppc/gdb-sim.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o
+@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libsim_a_OBJECTS = $(am__objects_1)
+ppc_libsim_a_OBJECTS = $(am_ppc_libsim_a_OBJECTS)
pru_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_pru_TRUE@ %,pru/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/modules.$(OBJEXT)
v850_libsim_a_OBJECTS = $(am_v850_libsim_a_OBJECTS) \
$(nodist_v850_libsim_a_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/gen$(EXEEXT) igen/ld-cache$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/ld-decode$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/ld-insn$(EXEEXT) \
-@SIM_ENABLE_IGEN_TRUE@ igen/table$(EXEEXT)
-@SIM_ENABLE_IGEN_TRUE@am__EXEEXT_2 = $(am__EXEEXT_1)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_3 = cr16/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_4 = d10v/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_5 = m32c/opc2c$(EXEEXT)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_6 = m68hc11/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_7 = sh/gencode$(EXEEXT)
-am__EXEEXT_8 = testsuite/common/bits32m0$(EXEEXT) \
+am__EXEEXT_1 = $(IGEN) igen/filter$(EXEEXT) igen/gen$(EXEEXT) \
+ igen/ld-cache$(EXEEXT) igen/ld-decode$(EXEEXT) \
+ igen/ld-insn$(EXEEXT) igen/table$(EXEEXT)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_2 = cr16/gencode$(EXEEXT)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_3 = d10v/gencode$(EXEEXT)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_4 = m32c/opc2c$(EXEEXT)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_5 = m68hc11/gencode$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_6 = $(PPC_IGEN) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache$(EXEEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode$(EXEEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_7 = $(am__EXEEXT_6)
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+am__EXEEXT_9 = testsuite/common/bits32m0$(EXEEXT) \
testsuite/common/bits32m31$(EXEEXT) \
testsuite/common/bits64m0$(EXEEXT) \
testsuite/common/bits64m63$(EXEEXT) \
testsuite/common/alu-tst$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_9 = cris/rvdummy$(EXEEXT)
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_10 = aarch64/run$(EXEEXT)
-@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_11 = arm/run$(EXEEXT)
-@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_12 = avr/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_13 = bfin/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_14 = bpf/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_15 = cr16/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_16 = cris/run$(EXEEXT)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_17 = d10v/run$(EXEEXT)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_18 = erc32/run$(EXEEXT) \
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_10 = cris/rvdummy$(EXEEXT)
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_11 = aarch64/run$(EXEEXT)
+@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_12 = arm/run$(EXEEXT)
+@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_13 = avr/run$(EXEEXT)
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+@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_15 = bpf/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_16 = cr16/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_17 = cris/run$(EXEEXT)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_18 = d10v/run$(EXEEXT)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_19 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis$(EXEEXT)
-@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_19 = \
+@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_20 = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/run$(EXEEXT)
-@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_20 = frv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_21 = ft32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_22 = h8300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_23 = iq2000/run$(EXEEXT)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_24 = lm32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_25 = m32c/run$(EXEEXT)
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-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_27 = m68hc11/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_28 = mcore/run$(EXEEXT)
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_29 = \
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+@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_22 = ft32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_23 = h8300/run$(EXEEXT)
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+@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_29 = mcore/run$(EXEEXT)
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_30 = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_30 = mips/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_31 = mn10300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_32 = moxie/run$(EXEEXT)
-@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_33 = msp430/run$(EXEEXT)
-@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_34 = or1k/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_35 = ppc/run$(EXEEXT) \
-@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim$(EXEEXT)
-@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_36 = pru/run$(EXEEXT)
-@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_37 = riscv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_38 = rl78/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_39 = rx/run$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_40 = sh/run$(EXEEXT)
-@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_41 = v850/run$(EXEEXT)
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+@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_32 = mn10300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_33 = moxie/run$(EXEEXT)
+@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_34 = msp430/run$(EXEEXT)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_35 = or1k/run$(EXEEXT)
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+@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_39 = rl78/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_40 = rx/run$(EXEEXT)
+@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_41 = sh/run$(EXEEXT)
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PROGRAMS = $(noinst_PROGRAMS)
am_aarch64_run_OBJECTS =
aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
@SIM_ENABLE_ARCH_h8300_TRUE@ $(am__DEPENDENCIES_4)
am_igen_filter_OBJECTS =
igen_filter_OBJECTS = $(am_igen_filter_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_filter_DEPENDENCIES = igen/filter-main.o \
-@SIM_ENABLE_IGEN_TRUE@ igen/libigen.a
+igen_filter_DEPENDENCIES = igen/filter-main.o igen/libigen.a
am_igen_gen_OBJECTS =
igen_gen_OBJECTS = $(am_igen_gen_OBJECTS)
-@SIM_ENABLE_IGEN_TRUE@igen_gen_DEPENDENCIES = igen/gen-main.o \
-@SIM_ENABLE_IGEN_TRUE@ igen/libigen.a
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SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
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common/callback.c \
common/portability.c \
common/sim-load.c \
+ common/sim-signal.c \
common/syscall.c \
common/target-newlib-errno.c \
common/target-newlib-open.c \
sim-command.o sim-config.o sim-core.o sim-cpu.o sim-endian.o \
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GEN_MODULES_C_SRCS = \
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$(LIBGNU_EXTRA_LIBS)
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CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s"
CGENFLAGS = -v
CGEN_CPU_DIR = $(cgendir)/cpu
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
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# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
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-@SIM_ENABLE_IGEN_TRUE@ igen/ld-decode \
-@SIM_ENABLE_IGEN_TRUE@ igen/ld-insn \
-@SIM_ENABLE_IGEN_TRUE@ igen/table
+IGEN = igen/igen$(EXEEXT)
+IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(IGEN) $(IGEN_FLAGS_SMP)
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+ igen/table.c \
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+ igen/misc.c \
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+ igen/ld-decode.c \
+ igen/ld-cache.c \
+ igen/filter.c \
+ igen/ld-insn.c \
+ igen/gen-model.c \
+ igen/gen-itable.c \
+ igen/gen-icache.c \
+ igen/gen-semantics.c \
+ igen/gen-idecode.c \
+ igen/gen-support.c \
+ igen/gen-engine.c \
+ igen/gen.c
+
+igen_igen_SOURCES = igen/igen.c
+igen_igen_LDADD = igen/libigen.a
+igen_filter_SOURCES =
+igen_filter_LDADD = igen/filter-main.o igen/libigen.a
+igen_gen_SOURCES =
+igen_gen_LDADD = igen/gen-main.o igen/libigen.a
+igen_ld_cache_SOURCES =
+igen_ld_cache_LDADD = igen/ld-cache-main.o igen/libigen.a
+igen_ld_decode_SOURCES =
+igen_ld_decode_LDADD = igen/ld-decode-main.o igen/libigen.a
+igen_ld_insn_SOURCES =
+igen_ld_insn_LDADD = igen/ld-insn-main.o igen/libigen.a
+igen_table_SOURCES =
+igen_table_LDADD = igen/table-main.o igen/libigen.a
+igen_IGEN_TOOLS = \
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+ igen/filter \
+ igen/gen \
+ igen/ld-cache \
+ igen/ld-decode \
+ igen/ld-insn \
+ igen/table
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@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.c
@SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-sim.o \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
-@SIM_ENABLE_ARCH_bpf_TRUE@ \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-run.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-scache.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-utils.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cpu.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-if.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES =
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf_BUILD_OUTPUTS = \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.c \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-le \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.c \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-be
-
@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
+@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_CFLAG_WNO_SHADOW_LOCAL)
+@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE)
@SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.c
@SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_frv_TRUE@AM_CPPFLAGS_frv = $(SIM_FRV_TRAPDUMP_FLAGS)
-@SIM_ENABLE_ARCH_frv_TRUE@AM_CFLAGS_frv_memory.o = -Wno-error
@SIM_ENABLE_ARCH_frv_TRUE@AM_CFLAGS_frv_sem.o = -Wno-error
@SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.c
# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu2.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpux.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r2.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32rx.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop2.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloopx.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sem.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sim_if.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_traps.o = -Wno-error
@SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
-@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_71) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_72) $(am__append_73)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_77) $(am__append_78) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79)
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.c \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/stamp-mloop
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES =
+@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -DHAVE_COMMON_FPU \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_smp) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_xor_endian) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_bitsize) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_timebase) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_float) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_monitor) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_model) $(sim_ppc_default_model) $(sim_ppc_model_issue) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_switch)
+
+@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc_options.o = '-DOPCODE_RULES="$(IGEN_OPCODE_RULES)"' '-DIGEN_FLAGS="$(ppc_IGEN_FLAGS)"'
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_SOURCES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(common_libcommon_a_SOURCES)
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/debug.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-endian.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_generic.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_chirp.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_unix.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/vm.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/events.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/tree.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-fpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/pk_disklabel.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst %,ppc/%,$(sim_ppc_hw_obj)) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gdb-sim.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.c
+
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \
-@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_SOURCES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/table.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.c
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_LIBADD = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/lf.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_SOURCES = ppc/igen.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_LDADD = ppc/libigen.a
+
+# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
+# leak detection while running it.
+@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN = ppc/igen$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(PPC_IGEN) $(ppc_IGEN_FLAGS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_FLAGS = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_decode_mechanism@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_dup@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_jump@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_filter@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_icache@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_igen_smp@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_line_nr@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILT_SRC_FROM_IGEN = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.c
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILD_OUTPUTS = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILT_SRC_FROM_IGEN) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-igen ppc/hw.c ppc/hw.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-hw ppc/stamp-pk
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_OPCODE_RULES = ppc/@sim_ppc_opcode@
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_SOURCES =
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_LDADD = ppc/ld-cache-main.o ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_SOURCES =
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_LDADD = ppc/ld-decode-main.o ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_SOURCES =
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_LDADD = ppc/ld-insn-main.o ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_TOOLS = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(PPC_IGEN) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn
+
+@SIM_ENABLE_ARCH_ppc_TRUE@IGEN_OPCODE_RULES = @sim_ppc_opcode@
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_HW_SRC = $(sim_ppc_hw_src:%=ppc/%)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_PACKAGE_SRC = ppc/pk_disklabel.c
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdocdir = $(docdir)/ppc
@SIM_ENABLE_ARCH_ppc_TRUE@ppcdoc_DATA = ppc/BUGS ppc/INSTALL ppc/README ppc/RUN
@SIM_ENABLE_ARCH_pru_TRUE@nodist_pru_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_sh_TRUE@sh_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/gencode$(EXEEXT) \
+@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
+@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/table.c
@SIM_ENABLE_ARCH_sh_TRUE@sh_gencode_SOURCES = sh/gencode.c
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_INSN = $(srcdir)/v850/v850.igen
@SIM_ENABLE_ARCH_v850_TRUE@v850_IGEN_DC = $(srcdir)/v850/v850.dc
all: $(BUILT_SOURCES) config.h
- $(MAKE) $(AM_MAKEFLAGS) all-recursive
+ $(MAKE) $(AM_MAKEFLAGS) all-am
.SUFFIXES:
.SUFFIXES: .c .lo .log .o .obj .test .test$(EXEEXT) .trs
cd $(top_builddir) && $(SHELL) ./config.status $@
example-synacor/.gdbinit: $(top_builddir)/config.status $(top_srcdir)/common/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
-arch-subdir.mk: $(top_builddir)/config.status $(srcdir)/arch-subdir.mk.in
- cd $(top_builddir) && $(SHELL) ./config.status $@
.gdbinit: $(top_builddir)/config.status $(srcdir)/gdbinit.in
cd $(top_builddir) && $(SHELL) ./config.status $@
common/$(DEPDIR)/$(am__dirstamp)
common/sim-load.$(OBJEXT): common/$(am__dirstamp) \
common/$(DEPDIR)/$(am__dirstamp)
+common/sim-signal.$(OBJEXT): common/$(am__dirstamp) \
+ common/$(DEPDIR)/$(am__dirstamp)
common/syscall.$(OBJEXT): common/$(am__dirstamp) \
common/$(DEPDIR)/$(am__dirstamp)
common/target-newlib-errno.$(OBJEXT): common/$(am__dirstamp) \
igen/$(DEPDIR)/$(am__dirstamp)
igen/gen.$(OBJEXT): igen/$(am__dirstamp) \
igen/$(DEPDIR)/$(am__dirstamp)
-
-@SIM_ENABLE_IGEN_FALSE@igen/libigen.a: $(igen_libigen_a_OBJECTS) $(igen_libigen_a_DEPENDENCIES) $(EXTRA_igen_libigen_a_DEPENDENCIES) igen/$(am__dirstamp)
-@SIM_ENABLE_IGEN_FALSE@ $(AM_V_at)-rm -f igen/libigen.a
-@SIM_ENABLE_IGEN_FALSE@ $(AM_V_AR)$(igen_libigen_a_AR) igen/libigen.a $(igen_libigen_a_OBJECTS) $(igen_libigen_a_LIBADD)
-@SIM_ENABLE_IGEN_FALSE@ $(AM_V_at)$(RANLIB) igen/libigen.a
iq2000/$(am__dirstamp):
@$(MKDIR_P) iq2000
@: > iq2000/$(am__dirstamp)
$(AM_V_at)-rm -f or1k/libsim.a
$(AM_V_AR)$(or1k_libsim_a_AR) or1k/libsim.a $(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD)
$(AM_V_at)$(RANLIB) or1k/libsim.a
+ppc/$(am__dirstamp):
+ @$(MKDIR_P) ppc
+ @: > ppc/$(am__dirstamp)
+ppc/$(DEPDIR)/$(am__dirstamp):
+ @$(MKDIR_P) ppc/$(DEPDIR)
+ @: > ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/table.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/lf-ppc.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/dumpf.$(OBJEXT): ppc/$(am__dirstamp) ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/ld-decode.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/ld-cache.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/filter-ppc.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/ld-insn.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/gen-model.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/gen-itable.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/gen-icache.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/gen-semantics.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/gen-idecode.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+ppc/gen-support.$(OBJEXT): ppc/$(am__dirstamp) \
+ ppc/$(DEPDIR)/$(am__dirstamp)
+
+@SIM_ENABLE_ARCH_ppc_FALSE@ppc/libigen.a: $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_DEPENDENCIES) $(EXTRA_ppc_libigen_a_DEPENDENCIES) ppc/$(am__dirstamp)
+@SIM_ENABLE_ARCH_ppc_FALSE@ $(AM_V_at)-rm -f ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_FALSE@ $(AM_V_AR)$(ppc_libigen_a_AR) ppc/libigen.a $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_LIBADD)
+@SIM_ENABLE_ARCH_ppc_FALSE@ $(AM_V_at)$(RANLIB) ppc/libigen.a
+
+ppc/libsim.a: $(ppc_libsim_a_OBJECTS) $(ppc_libsim_a_DEPENDENCIES) $(EXTRA_ppc_libsim_a_DEPENDENCIES) ppc/$(am__dirstamp)
+ $(AM_V_at)-rm -f ppc/libsim.a
+ $(AM_V_AR)$(ppc_libsim_a_AR) ppc/libsim.a $(ppc_libsim_a_OBJECTS) $(ppc_libsim_a_LIBADD)
+ $(AM_V_at)$(RANLIB) ppc/libsim.a
pru/$(am__dirstamp):
@$(MKDIR_P) pru
@: > pru/$(am__dirstamp)
igen/igen.$(OBJEXT): igen/$(am__dirstamp) \
igen/$(DEPDIR)/$(am__dirstamp)
-@SIM_ENABLE_IGEN_FALSE@igen/igen$(EXEEXT): $(igen_igen_OBJECTS) $(igen_igen_DEPENDENCIES) $(EXTRA_igen_igen_DEPENDENCIES) igen/$(am__dirstamp)
-@SIM_ENABLE_IGEN_FALSE@ @rm -f igen/igen$(EXEEXT)
-@SIM_ENABLE_IGEN_FALSE@ $(AM_V_CCLD)$(LINK) $(igen_igen_OBJECTS) $(igen_igen_LDADD) $(LIBS)
-
igen/ld-cache$(EXEEXT): $(igen_ld_cache_OBJECTS) $(igen_ld_cache_DEPENDENCIES) $(EXTRA_igen_ld_cache_DEPENDENCIES) igen/$(am__dirstamp)
@rm -f igen/ld-cache$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(igen_ld_cache_OBJECTS) $(igen_ld_cache_LDADD) $(LIBS)
or1k/run$(EXEEXT): $(or1k_run_OBJECTS) $(or1k_run_DEPENDENCIES) $(EXTRA_or1k_run_DEPENDENCIES) or1k/$(am__dirstamp)
@rm -f or1k/run$(EXEEXT)
$(AM_V_CCLD)$(LINK) $(or1k_run_OBJECTS) $(or1k_run_LDADD) $(LIBS)
-ppc/$(am__dirstamp):
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-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-le:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le"; $(CGEN_GEN_DEFS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-le.h: @CGEN_MAINT@ bpf/cgen-defs-le
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-be:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be"; $(CGEN_GEN_DEFS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-be.h: @CGEN_MAINT@ bpf/cgen-defs-be
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-le:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-le.c bpf/decode-le.c bpf/decode-le.h: @CGEN_MAINT@ bpf/cgen-decode-vle
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-be:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-be.c bpf/decode-be.c bpf/decode-be.h: @CGEN_MAINT@ bpf/cgen-decode-be
@SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD): cr16/hw-config.h
+@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.o: cr16/modules.c
+
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_cr16_TRUE@-@am__include@ cr16/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_cr16_TRUE@ $(AM_V_GEN)$< >$@
@SIM_ENABLE_ARCH_cris_TRUE@$(cris_libsim_a_OBJECTS) $(cris_libsim_a_LIBADD): cris/hw-config.h
+@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.o: cris/modules.c
+
@SIM_ENABLE_ARCH_cris_TRUE@cris/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_cris_TRUE@-@am__include@ cris/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv10f.c cris/engv10.h: cris/stamp-mloop-v10f ; @true
-@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f: $(srccom)/genmloop.sh cris/mloop.in
-@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f: cris/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_cris_TRUE@ -mono -no-fast -pbb -switch semcrisv10f-switch.c \
-@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv10f \
-@SIM_ENABLE_ARCH_cris_TRUE@ -infile $(srcdir)/cris/mloop.in -outfile-prefix cris/ -outfile-suffix -v10f
+@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv10f -outfile-suffix -v10f
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v10f.hin cris/engv10.h
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v10f.cin cris/mloopv10f.c
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv32f.c cris/engv32.h: cris/stamp-mloop-v32f ; @true
-@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f: $(srccom)/genmloop.sh cris/mloop.in
-@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f: cris/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_cris_TRUE@ -mono -no-fast -pbb -switch semcrisv32f-switch.c \
-@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv32f \
-@SIM_ENABLE_ARCH_cris_TRUE@ -infile $(srcdir)/cris/mloop.in -outfile-prefix cris/ -outfile-suffix -v32f
+@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv32f -outfile-suffix -v32f
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v32f.hin cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v32f.cin cris/mloopv32f.c
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-arch:
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)mach=crisv10,crisv32 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_cris_TRUE@cris/arch.h cris/arch.c cris/cpuall.h: @CGEN_MAINT@ cris/cgen-arch
+@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/arch.h $(srcdir)/cris/arch.c $(srcdir)/cris/cpuall.h: @CGEN_MAINT@ cris/cgen-arch
@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v10f:
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv10-switch.c $(srcdir)/cris/semcrisv10f-switch.c
-@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv10.h cris/cpuv10.c cris/semcrisv10f-switch.c cris/modelv10.c cris/decodev10.c cris/decodev10.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v10f
+@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/cpuv10.h $(srcdir)/cris/cpuv10.c $(srcdir)/cris/semcrisv10f-switch.c $(srcdir)/cris/modelv10.c $(srcdir)/cris/decodev10.c $(srcdir)/cris/decodev10.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v10f
@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v32f:
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv32-switch.c $(srcdir)/cris/semcrisv32f-switch.c
-@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv32.h cris/cpuv32.c cris/semcrisv32f-switch.c cris/modelv32.c cris/decodev32.c cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f
+@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/cpuv32.h $(srcdir)/cris/cpuv32.c $(srcdir)/cris/semcrisv32f-switch.c $(srcdir)/cris/modelv32.c $(srcdir)/cris/decodev32.c $(srcdir)/cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f
@SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD): d10v/hw-config.h
+@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.o: d10v/modules.c
+
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_d10v_TRUE@-@am__include@ d10v/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_d10v_TRUE@ $(AM_V_GEN)$< >$@
@SIM_ENABLE_ARCH_erc32_TRUE@$(erc32_libsim_a_OBJECTS) $(erc32_libsim_a_LIBADD): erc32/hw-config.h
+@SIM_ENABLE_ARCH_erc32_TRUE@erc32/modules.o: erc32/modules.c
+
@SIM_ENABLE_ARCH_erc32_TRUE@erc32/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_erc32_TRUE@-@am__include@ erc32/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_erc32_TRUE@ rm -f $(DESTDIR)$(bindir)/sis
@SIM_ENABLE_ARCH_examples_TRUE@$(example_synacor_libsim_a_OBJECTS) $(example_synacor_libsim_a_LIBADD): example-synacor/hw-config.h
+@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/modules.o: example-synacor/modules.c
+
@SIM_ENABLE_ARCH_examples_TRUE@example-synacor/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_examples_TRUE@-@am__include@ example-synacor/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_frv_TRUE@$(frv_libsim_a_OBJECTS) $(frv_libsim_a_LIBADD): frv/hw-config.h
+@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.o: frv/modules.c
+
@SIM_ENABLE_ARCH_frv_TRUE@frv/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_frv_TRUE@-@am__include@ frv/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: $(srccom)/genmloop.sh frv/mloop.in
-@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: frv/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_frv_TRUE@ -mono -scache -parallel-generic-write -parallel-only \
-@SIM_ENABLE_ARCH_frv_TRUE@ -cpu frvbf \
-@SIM_ENABLE_ARCH_frv_TRUE@ -infile $(srcdir)/frv/mloop.in -outfile-prefix frv/
+@SIM_ENABLE_ARCH_frv_TRUE@ -cpu frvbf
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/eng.hin frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_frv_TRUE@frv/arch.h frv/arch.c frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch
+@SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/arch.h $(srcdir)/frv/arch.c $(srcdir)/frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
+@SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/cpu.h $(srcdir)/frv/sem.c $(srcdir)/frv/model.c $(srcdir)/frv/decode.c $(srcdir)/frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h
+@SIM_ENABLE_ARCH_ft32_TRUE@ft32/modules.o: ft32/modules.c
+
@SIM_ENABLE_ARCH_ft32_TRUE@ft32/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_ft32_TRUE@-@am__include@ ft32/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_h8300_TRUE@$(h8300_libsim_a_OBJECTS) $(h8300_libsim_a_LIBADD): h8300/hw-config.h
+@SIM_ENABLE_ARCH_h8300_TRUE@h8300/modules.o: h8300/modules.c
+
@SIM_ENABLE_ARCH_h8300_TRUE@h8300/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_h8300_TRUE@-@am__include@ h8300/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_iq2000_TRUE@$(iq2000_libsim_a_OBJECTS) $(iq2000_libsim_a_LIBADD): iq2000/hw-config.h
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.o: iq2000/modules.c
+
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_iq2000_TRUE@-@am__include@ iq2000/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: $(srccom)/genmloop.sh iq2000/mloop.in
-@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: iq2000/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_iq2000_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_iq2000_TRUE@ -cpu iq2000bf \
-@SIM_ENABLE_ARCH_iq2000_TRUE@ -infile $(srcdir)/iq2000/mloop.in -outfile-prefix iq2000/
+@SIM_ENABLE_ARCH_iq2000_TRUE@ -cpu iq2000bf
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/eng.hin iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/mloop.cin iq2000/mloop.c
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-arch:
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)mach=iq2000 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/arch.h iq2000/arch.c iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch
+@SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/arch.h $(srcdir)/iq2000/arch.c $(srcdir)/iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode:
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cpu.h iq2000/sem.c iq2000/sem-switch.c iq2000/model.c iq2000/decode.c iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
+@SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/cpu.h $(srcdir)/iq2000/sem.c $(srcdir)/iq2000/sem-switch.c $(srcdir)/iq2000/model.c $(srcdir)/iq2000/decode.c $(srcdir)/iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
@SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.o: lm32/modules.c
+
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_lm32_TRUE@-@am__include@ lm32/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: $(srccom)/genmloop.sh lm32/mloop.in
-@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: lm32/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_lm32_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_lm32_TRUE@ -cpu lm32bf \
-@SIM_ENABLE_ARCH_lm32_TRUE@ -infile $(srcdir)/lm32/mloop.in -outfile-prefix lm32/
+@SIM_ENABLE_ARCH_lm32_TRUE@ -cpu lm32bf
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/eng.hin lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/mloop.cin lm32/mloop.c
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-arch:
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_lm32_TRUE@lm32/arch.h lm32/arch.c lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch
+@SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/arch.h $(srcdir)/lm32/arch.c $(srcdir)/lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode:
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cpu.h lm32/sem.c lm32/sem-switch.c lm32/model.c lm32/decode.c lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
+@SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/cpu.h $(srcdir)/lm32/sem.c $(srcdir)/lm32/sem-switch.c $(srcdir)/lm32/model.c $(srcdir)/lm32/decode.c $(srcdir)/lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
@SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h
+@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.o: m32c/modules.c
+
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_m32c_TRUE@-@am__include@ m32c/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_m32c_TRUE@ $(AM_V_at)mv $@.tmp $@
@SIM_ENABLE_ARCH_m32r_TRUE@$(m32r_libsim_a_OBJECTS) $(m32r_libsim_a_LIBADD): m32r/hw-config.h
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.o: m32r/modules.c
+
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_m32r_TRUE@-@am__include@ m32r/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: $(srccom)/genmloop.sh m32r/mloop.in
-@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: m32r/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rbf \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloop.in -outfile-prefix m32r/
+@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rbf
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng.hin m32r/eng.h
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop.cin m32r/mloop.c
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h: m32r/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: $(srccom)/genmloop.sh m32r/mloop.in
-@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h: m32r/stamp-mloop-x ; @true
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: m32r/mloopx.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch semx-switch.c \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rxf \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloopx.in -outfile-prefix m32r/ -outfile-suffix x
+@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rxf -outfile-suffix x
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/engx.hin m32r/engx.h
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloopx.cin m32r/mloopx.c
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h: m32r/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: $(srccom)/genmloop.sh m32r/mloop.in
-@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h: m32r/stamp-mloop-2 ; @true
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: m32r/mloop2.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32r2f \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloop2.in -outfile-prefix m32r/ -outfile-suffix 2
+@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32r2f -outfile-suffix 2
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng2.hin m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop2.cin m32r/mloop2.c
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-arch:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/arch.h m32r/arch.c m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/arch.h $(srcdir)/m32r/arch.c $(srcdir)/m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rbf mach=m32r FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu.h m32r/sem.c m32r/sem-switch.c m32r/model.c m32r/decode.c m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu.h $(srcdir)/m32r/sem.c $(srcdir)/m32r/sem-switch.c $(srcdir)/m32r/model.c $(srcdir)/m32r/decode.c $(srcdir)/m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-x:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpux.h m32r/semx-switch.c m32r/modelx.c m32r/decodex.c m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpux.h $(srcdir)/m32r/semx-switch.c $(srcdir)/m32r/modelx.c $(srcdir)/m32r/decodex.c $(srcdir)/m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu2.h m32r/sem2-switch.c m32r/model2.c m32r/decode2.c m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu2.h $(srcdir)/m32r/sem2-switch.c $(srcdir)/m32r/model2.c $(srcdir)/m32r/decode2.c $(srcdir)/m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
@SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h
+@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.o: m68hc11/modules.c
+
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_m68hc11_TRUE@-@am__include@ m68hc11/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_m68hc11_TRUE@ $(AM_V_GEN)$< -m6812 >$@
@SIM_ENABLE_ARCH_mcore_TRUE@$(mcore_libsim_a_OBJECTS) $(mcore_libsim_a_LIBADD): mcore/hw-config.h
+@SIM_ENABLE_ARCH_mcore_TRUE@mcore/modules.o: mcore/modules.c
+
@SIM_ENABLE_ARCH_mcore_TRUE@mcore/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_mcore_TRUE@-@am__include@ mcore/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_microblaze_TRUE@$(microblaze_libsim_a_OBJECTS) $(microblaze_libsim_a_LIBADD): microblaze/hw-config.h
+@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/modules.o: microblaze/modules.c
+
@SIM_ENABLE_ARCH_microblaze_TRUE@microblaze/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_microblaze_TRUE@-@am__include@ microblaze/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_mips_TRUE@$(mips_libsim_a_OBJECTS) $(mips_libsim_a_LIBADD): mips/hw-config.h
+@SIM_ENABLE_ARCH_mips_TRUE@mips/modules.o: mips/modules.c
+
@SIM_ENABLE_ARCH_mips_TRUE@mips/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_mips_TRUE@-@am__include@ mips/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_mips_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_mn10300_TRUE@$(mn10300_libsim_a_OBJECTS) $(mn10300_libsim_a_LIBADD): mn10300/hw-config.h
+@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/modules.o: mn10300/modules.c
+
@SIM_ENABLE_ARCH_mn10300_TRUE@mn10300/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_mn10300_TRUE@-@am__include@ mn10300/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_mn10300_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_moxie_TRUE@$(moxie_libsim_a_OBJECTS) $(moxie_libsim_a_LIBADD): moxie/hw-config.h
+@SIM_ENABLE_ARCH_moxie_TRUE@moxie/modules.o: moxie/modules.c
+
@SIM_ENABLE_ARCH_moxie_TRUE@moxie/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_moxie_TRUE@-@am__include@ moxie/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_moxie_TRUE@ fi
@SIM_ENABLE_ARCH_msp430_TRUE@$(msp430_libsim_a_OBJECTS) $(msp430_libsim_a_LIBADD): msp430/hw-config.h
+@SIM_ENABLE_ARCH_msp430_TRUE@msp430/modules.o: msp430/modules.c
+
@SIM_ENABLE_ARCH_msp430_TRUE@msp430/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_msp430_TRUE@-@am__include@ msp430/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_or1k_TRUE@$(or1k_libsim_a_OBJECTS) $(or1k_libsim_a_LIBADD): or1k/hw-config.h
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.o: or1k/modules.c
+
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_or1k_TRUE@-@am__include@ or1k/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: $(srccom)/genmloop.sh or1k/mloop.in
-@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: or1k/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_or1k_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_or1k_TRUE@ -cpu or1k32bf \
-@SIM_ENABLE_ARCH_or1k_TRUE@ -infile $(srcdir)/or1k/mloop.in -outfile-prefix or1k/
+@SIM_ENABLE_ARCH_or1k_TRUE@ -cpu or1k32bf
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/eng.hin or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/mloop.cin or1k/mloop.c
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-arch:
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)mach=or32,or32nd FLAGS="with-scache"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_or1k_TRUE@or1k/arch.h or1k/arch.c or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch
+@SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/arch.h $(srcdir)/or1k/arch.c $(srcdir)/or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-cpu-decode:
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)cpu=or1k32bf mach=or32,or32nd FLAGS="with-scache" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cpu.h or1k/cpu.c or1k/model.c or1k/sem.c or1k/sem-switch.c or1k/decode.c or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode
+@SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/cpu.h $(srcdir)/or1k/cpu.c $(srcdir)/or1k/model.c $(srcdir)/or1k/sem.c $(srcdir)/or1k/sem-switch.c $(srcdir)/or1k/decode.c $(srcdir)/or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc/psim$(EXEEXT): ppc/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)ln $< $@ 2>/dev/null || $(LN_S) $< $@ 2>/dev/null || cp -p $< $@
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc/libsim.a: common/libcommon.a
-@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: common/%.c ; $(SIM_COMPILE)
+@SIM_ENABLE_ARCH_ppc_TRUE@-@am__include@ ppc/$(DEPDIR)/*.Po
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: ppc/%.c | ppc/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
-@SIM_ENABLE_ARCH_ppc_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/defines.h: ppc/stamp-defines ; @true
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-defines: config.h Makefile
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(SED) -n -e '/^#define HAVE_.*1$$/{ s/ 1$$/",/; s/.* HAVE_/"HAVE_/; p }' < config.h > ppc/defines.hin
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/defines.hin ppc/defines.h
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.c: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp)
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --source $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.h
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h
+
+@SIM_ENABLE_ARCH_ppc_TRUE@$(ppc_BUILT_SRC_FROM_IGEN): ppc/stamp-igen
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-igen: ppc/powerpc.igen ppc/altivec.igen ppc/e500.igen $(ppc_IGEN_OPCODE_RULES) $(PPC_IGEN)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(PPC_IGEN_RUN) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -o $(srcdir)/$(ppc_IGEN_OPCODE_RULES) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -I $(srcdir)/ppc -i $(srcdir)/ppc/powerpc.igen \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n icache.h -hc ppc/icache.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n icache.c -c ppc/icache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n semantics.h -hs ppc/semantics.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n semantics.c -s ppc/semantics.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n idecode.h -hd ppc/idecode.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n idecode.c -d ppc/idecode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n itable.h -ht ppc/itable.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n itable.c -t ppc/itable.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n model.h -hm ppc/model.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n model.c -m ppc/model.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n support.h -hf ppc/support.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n support.c -f ppc/support.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/libigen.a: $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_DEPENDENCIES) $(EXTRA_ppc_libigen_a_DEPENDENCIES) ppc/$(am__dirstamp)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)-rm -f $@
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_LIBADD)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(RANLIB_FOR_BUILD) $@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/igen$(EXEEXT): $(ppc_igen_OBJECTS) $(ppc_igen_DEPENDENCIES) ppc/$(am__dirstamp)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(ppc_igen_OBJECTS) $(ppc_igen_LDADD)
+
+@SIM_ENABLE_ARCH_ppc_TRUE@$(ppc_libigen_a_OBJECTS) $(ppc_igen_OBJECTS): ppc/%.o: ppc/%.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -I$(srcdir)/igen -I$(srcdir)/ppc -c $< -o $@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%-main.o: ppc/%.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/hw.c ppc/hw.h: ppc/stamp-hw ; @true
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-hw: Makefile $(ppc_HW_SRC) $(srcroot)/move-if-change
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)\
+@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_HW_SRC) ; do \
+@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for hw in $$f ; do echo $$hw ; done \
+@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*\(hw_.*\)\.c/\1/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/extern const device_descriptor /' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_device_descriptor\[\];/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ > ppc/hw.hin; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_HW_SRC) ; do \
+@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for hw in $$f ; do echo $$hw ; done \
+@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*\(hw_.*\)\.c/\1/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/ /' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_device_descriptor,/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ > ppc/hw.cin
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/hw.hin ppc/hw.h
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/hw.cin ppc/hw.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/hw.c ppc/hw.h: ppc/stamp-igen
+@SIM_ENABLE_ARCH_ppc_TRUE@$(srcdir)/ppc/pk.h: @MAINT@ ppc/stamp-pk ; @true
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-pk: $(srcdir)/ppc/Makefile.in $(ppc_PACKAGE_SRC) $(srcroot)/move-if-change
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)echo "/* Generated file by local.mk; do not edit. */" > ppc/pk.hin; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_PACKAGE_SRC) ; do \
+@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for pk in $$f ; do echo $$pk ; done \
+@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*pk_\(.*\)\.c/\1/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/extern package_create_instance_callback pk_/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_create_instance;/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ >> ppc/pk.hin
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/pk.hin $(srcdir)/ppc/pk.h
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): pru/hw-config.h
+@SIM_ENABLE_ARCH_pru_TRUE@pru/modules.o: pru/modules.c
+
@SIM_ENABLE_ARCH_pru_TRUE@pru/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_pru_TRUE@-@am__include@ pru/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_riscv_TRUE@$(riscv_libsim_a_OBJECTS) $(riscv_libsim_a_LIBADD): riscv/hw-config.h
+@SIM_ENABLE_ARCH_riscv_TRUE@riscv/modules.o: riscv/modules.c
+
@SIM_ENABLE_ARCH_riscv_TRUE@riscv/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_riscv_TRUE@-@am__include@ riscv/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_rl78_TRUE@$(rl78_libsim_a_OBJECTS) $(rl78_libsim_a_LIBADD): rl78/hw-config.h
+@SIM_ENABLE_ARCH_rl78_TRUE@rl78/modules.o: rl78/modules.c
+
@SIM_ENABLE_ARCH_rl78_TRUE@rl78/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_rl78_TRUE@-@am__include@ rl78/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_rx_TRUE@$(rx_libsim_a_OBJECTS) $(rx_libsim_a_LIBADD): rx/hw-config.h
+@SIM_ENABLE_ARCH_rx_TRUE@rx/modules.o: rx/modules.c
+
@SIM_ENABLE_ARCH_rx_TRUE@rx/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_rx_TRUE@-@am__include@ rx/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_sh_TRUE@$(sh_libsim_a_OBJECTS) $(sh_libsim_a_LIBADD): sh/hw-config.h
+@SIM_ENABLE_ARCH_sh_TRUE@sh/modules.o: sh/modules.c
+
@SIM_ENABLE_ARCH_sh_TRUE@sh/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_sh_TRUE@-@am__include@ sh/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_sh_TRUE@ $(AM_V_GEN)$< -s >$@
@SIM_ENABLE_ARCH_v850_TRUE@$(v850_libsim_a_OBJECTS) $(v850_libsim_a_LIBADD): v850/hw-config.h
+@SIM_ENABLE_ARCH_v850_TRUE@v850/modules.o: v850/modules.c
+
@SIM_ENABLE_ARCH_v850_TRUE@v850/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_v850_TRUE@-@am__include@ v850/$(DEPDIR)/*.Po
@SIM_ENABLE_ARCH_v850_TRUE@ -n irun.c -r v850/irun.c
@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)touch $@
-all-recursive: $(SIM_ALL_RECURSIVE_DEPS)
-
install-data-local: installdirs $(SIM_INSTALL_DATA_LOCAL_DEPS)
$(AM_V_at)$(MKDIR_P) $(DESTDIR)$(libdir)
lib=`echo sim | sed '$(program_transform_name)'`; \
projects / thirdparty / binutils-gdb.git / blobdiff