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-@SIM_ENABLE_ARCH_cr16_TRUE@am__append_15 = cr16/libsim.a
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@SIM_ENABLE_ARCH_cr16_TRUE@am__append_17 = cr16/simops.h
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-@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = \
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@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv10.h \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/engv32.h
+@SIM_ENABLE_ARCH_cris_TRUE@am__append_23 = cris/engv10.h cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@am__append_24 = $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_25 = d10v/libsim.a
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@SIM_ENABLE_ARCH_d10v_TRUE@am__append_27 = d10v/simops.h
@SIM_ENABLE_ARCH_d10v_TRUE@am__append_28 = d10v/gencode
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-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_40 = ft32/libsim.a
-@SIM_ENABLE_ARCH_ft32_TRUE@am__append_41 = ft32/run
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-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_45 = iq2000/run
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_46 = iq2000/eng.h
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__append_47 = $(iq2000_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_48 = lm32/libsim.a
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-@SIM_ENABLE_ARCH_lm32_TRUE@am__append_51 = $(lm32_BUILD_OUTPUTS)
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-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_54 = m32c/opc2c
-@SIM_ENABLE_ARCH_m32c_TRUE@am__append_55 = \
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@SIM_ENABLE_ARCH_m32c_TRUE@ $(m32c_BUILD_OUTPUTS) \
@SIM_ENABLE_ARCH_m32c_TRUE@ m32c/m32c.c.log \
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-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_58 = \
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@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/eng.h \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/engx.h \
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-@SIM_ENABLE_ARCH_m32r_TRUE@am__append_59 = $(m32r_BUILD_OUTPUTS)
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-@SIM_ENABLE_ARCH_microblaze_TRUE@am__append_67 = microblaze/run
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_68 = \
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-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_69 = \
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-@SIM_ENABLE_ARCH_mips_TRUE@am__append_73 = mips/itable.h \
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@SIM_ENABLE_ARCH_mips_TRUE@ $(SIM_MIPS_MULTI_SRC)
-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_SINGLE_TRUE@am__append_74 = \
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-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_M16_TRUE@am__append_75 = \
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-@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@am__append_76 = \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ $(SIM_MIPS_MULTI_SRC) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/stamp-gen-mode-multi-run
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_77 = $(mips_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_mips_TRUE@am__append_78 = mips/multi-include.h mips/multi-run.c
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-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_80 = mn10300/run
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_81 = \
+@SIM_ENABLE_ARCH_mips_TRUE@am__append_82 = $(mips_BUILD_OUTPUTS)
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@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/icache.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/idecode.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/semantics.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/itable.h \
@SIM_ENABLE_ARCH_mn10300_TRUE@ mn10300/engine.h
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_82 = $(mn10300_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__append_83 = moxie/libsim.a
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-@SIM_ENABLE_ARCH_or1k_TRUE@am__append_90 = $(or1k_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_91 = common/libcommon.a
-@SIM_ENABLE_ARCH_ppc_TRUE@am__append_92 = ppc/run
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-@SIM_ENABLE_ARCH_pru_TRUE@am__append_94 = pru/run
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-@SIM_ENABLE_ARCH_rl78_TRUE@am__append_97 = rl78/libsim.a
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-@SIM_ENABLE_ARCH_rx_TRUE@am__append_99 = rx/libsim.a
-@SIM_ENABLE_ARCH_rx_TRUE@am__append_100 = rx/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_101 = sh/libsim.a
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_102 = sh/run
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_103 = \
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__append_87 = $(mn10300_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_88 = moxie/libsim.a
+@SIM_ENABLE_ARCH_moxie_TRUE@am__append_89 = moxie/run
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_90 = msp430/libsim.a
+@SIM_ENABLE_ARCH_msp430_TRUE@am__append_91 = msp430/run
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_92 = or1k/libsim.a
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+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_94 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_95 = or1k/eng.h
+@SIM_ENABLE_ARCH_or1k_TRUE@am__append_96 = $(or1k_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_97 = ppc/libsim.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_98 = ppc/run
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_99 = ppc/defines.h ppc/icache.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h ppc/semantics.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.h ppc/support.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.h ppc/hw.h
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_100 = ppc/defines.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/stamp-defines \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_BUILD_OUTPUTS) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(ppc_IGEN_TOOLS) ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_101 = ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am__append_102 = $(ppc_IGEN_TOOLS)
+@SIM_ENABLE_ARCH_pru_TRUE@am__append_103 = pru/libsim.a
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+@SIM_ENABLE_ARCH_riscv_TRUE@am__append_106 = riscv/run
+@SIM_ENABLE_ARCH_rl78_TRUE@am__append_107 = rl78/libsim.a
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+@SIM_ENABLE_ARCH_rx_TRUE@am__append_109 = rx/libsim.a
+@SIM_ENABLE_ARCH_rx_TRUE@am__append_110 = rx/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_111 = sh/libsim.a
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_112 = sh/run
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_113 = \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/code.c \
@SIM_ENABLE_ARCH_sh_TRUE@ sh/ppi.c
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_104 = sh/gencode
-@SIM_ENABLE_ARCH_sh_TRUE@am__append_105 = $(sh_BUILD_OUTPUTS)
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_106 = v850/libsim.a
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_107 = v850/run
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_108 = \
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_114 = sh/gencode
+@SIM_ENABLE_ARCH_sh_TRUE@am__append_115 = $(sh_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_116 = v850/libsim.a
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_117 = v850/run
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@SIM_ENABLE_ARCH_v850_TRUE@ v850/icache.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/idecode.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/semantics.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/itable.h \
@SIM_ENABLE_ARCH_v850_TRUE@ v850/engine.h
-@SIM_ENABLE_ARCH_v850_TRUE@am__append_109 = $(v850_BUILD_OUTPUTS)
+@SIM_ENABLE_ARCH_v850_TRUE@am__append_119 = $(v850_BUILD_OUTPUTS)
subdir = .
ACLOCAL_M4 = $(top_srcdir)/aclocal.m4
am__aclocal_m4_deps = $(top_srcdir)/../config/acx.m4 \
$(top_srcdir)/m4/sim_ac_option_warnings.m4 \
$(top_srcdir)/m4/sim_ac_platform.m4 \
$(top_srcdir)/m4/sim_ac_toolchain.m4 \
+ $(top_srcdir)/../gdbsupport/libiberty.m4 \
$(top_srcdir)/frv/acinclude.m4 $(top_srcdir)/mips/acinclude.m4 \
+ $(top_srcdir)/ppc/acinclude.m4 \
$(top_srcdir)/riscv/acinclude.m4 $(top_srcdir)/rx/acinclude.m4 \
$(top_srcdir)/configure.ac
am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \
mips/.gdbinit mn10300/.gdbinit moxie/.gdbinit msp430/.gdbinit \
or1k/.gdbinit ppc/.gdbinit pru/.gdbinit riscv/.gdbinit \
rl78/.gdbinit rx/.gdbinit sh/.gdbinit erc32/.gdbinit \
- v850/.gdbinit example-synacor/.gdbinit arch-subdir.mk .gdbinit
+ v850/.gdbinit example-synacor/.gdbinit .gdbinit
CONFIG_CLEAN_VPATH_FILES =
LIBRARIES = $(noinst_LIBRARIES)
ARFLAGS = cru
@SIM_ENABLE_ARCH_aarch64_TRUE@ aarch64/simulator.o
am__dirstamp = $(am__leading_dot)dirstamp
am__objects_1 = common/callback.$(OBJEXT) common/portability.$(OBJEXT) \
- common/sim-load.$(OBJEXT) common/syscall.$(OBJEXT) \
- common/target-newlib-errno.$(OBJEXT) \
+ common/sim-load.$(OBJEXT) common/sim-signal.$(OBJEXT) \
+ common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
common/target-newlib-open.$(OBJEXT) \
common/target-newlib-signal.$(OBJEXT) \
common/target-newlib-syscall.$(OBJEXT) \
bfin_libsim_a_OBJECTS = $(am_bfin_libsim_a_OBJECTS) \
$(nodist_bfin_libsim_a_OBJECTS)
bpf_libsim_a_AR = $(AR) $(ARFLAGS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = $(patsubst \
+@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_DEPENDENCIES = bpf/bpf-sim.o \
+@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst \
@SIM_ENABLE_ARCH_bpf_TRUE@ %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-run.o bpf/cgen-scache.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o bpf/cgen-utils.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o bpf/cpu.o bpf/decode-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o bpf/sem-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o bpf/mloop-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o bpf/bpf.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o bpf/sim-if.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
@SIM_ENABLE_ARCH_bpf_TRUE@am_bpf_libsim_a_OBJECTS = $(am__objects_1)
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_OBJECTS = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.$(OBJEXT)
common_libcommon_a_LIBADD =
am_common_libcommon_a_OBJECTS = common/callback.$(OBJEXT) \
common/portability.$(OBJEXT) common/sim-load.$(OBJEXT) \
- common/syscall.$(OBJEXT) common/target-newlib-errno.$(OBJEXT) \
+ common/sim-signal.$(OBJEXT) common/syscall.$(OBJEXT) \
+ common/target-newlib-errno.$(OBJEXT) \
common/target-newlib-open.$(OBJEXT) \
common/target-newlib-signal.$(OBJEXT) \
common/target-newlib-syscall.$(OBJEXT) \
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@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/itable.o \
@SIM_ENABLE_ARCH_mips_TRUE@@SIM_MIPS_GEN_MODE_MULTI_TRUE@ mips/multi-run.o
-@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_68) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_69) \
+@SIM_ENABLE_ARCH_mips_TRUE@am__DEPENDENCIES_3 = $(am__append_73) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_2)
@SIM_ENABLE_ARCH_mips_TRUE@mips_libsim_a_DEPENDENCIES = mips/interp.o \
@SIM_ENABLE_ARCH_mips_TRUE@ $(am__DEPENDENCIES_3) $(patsubst \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/modules.$(OBJEXT)
or1k_libsim_a_OBJECTS = $(am_or1k_libsim_a_OBJECTS) \
$(nodist_or1k_libsim_a_OBJECTS)
+ppc_libigen_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_DEPENDENCIES = igen/filter.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o igen/lf.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o
+@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libigen_a_OBJECTS = \
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+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.$(OBJEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.$(OBJEXT)
+ppc_libigen_a_OBJECTS = $(am_ppc_libigen_a_OBJECTS)
+ppc_libsim_a_AR = $(AR) $(ARFLAGS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_DEPENDENCIES = ppc/debug.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o ppc/sim-endian.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o ppc/emul_generic.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o ppc/emul_chirp.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o ppc/emul_unix.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o ppc/vm.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o ppc/model.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o ppc/cpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o ppc/events.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o ppc/device.o ppc/tree.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o ppc/itable.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o ppc/icache.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o ppc/idecode.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o ppc/sim-fpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o ppc/pk_disklabel.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst \
+@SIM_ENABLE_ARCH_ppc_TRUE@ %,ppc/%,$(sim_ppc_hw_obj)) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o ppc/gdb-sim.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o
+@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_libsim_a_OBJECTS = $(am__objects_1)
+ppc_libsim_a_OBJECTS = $(am_ppc_libsim_a_OBJECTS)
pru_libsim_a_AR = $(AR) $(ARFLAGS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_libsim_a_DEPENDENCIES = $(patsubst \
@SIM_ENABLE_ARCH_pru_TRUE@ %,pru/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_3 = d10v/gencode$(EXEEXT)
@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_4 = m32c/opc2c$(EXEEXT)
@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_5 = m68hc11/gencode$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_6 = sh/gencode$(EXEEXT)
-am__EXEEXT_7 = testsuite/common/bits32m0$(EXEEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_6 = $(PPC_IGEN) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache$(EXEEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode$(EXEEXT) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_7 = $(am__EXEEXT_6)
+@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_8 = sh/gencode$(EXEEXT)
+am__EXEEXT_9 = testsuite/common/bits32m0$(EXEEXT) \
testsuite/common/bits32m31$(EXEEXT) \
testsuite/common/bits64m0$(EXEEXT) \
testsuite/common/bits64m63$(EXEEXT) \
testsuite/common/alu-tst$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_8 = cris/rvdummy$(EXEEXT)
-@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_9 = aarch64/run$(EXEEXT)
-@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_10 = arm/run$(EXEEXT)
-@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_11 = avr/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_12 = bfin/run$(EXEEXT)
-@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_13 = bpf/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_14 = cr16/run$(EXEEXT)
-@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_15 = cris/run$(EXEEXT)
-@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_16 = d10v/run$(EXEEXT)
-@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_17 = erc32/run$(EXEEXT) \
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_10 = cris/rvdummy$(EXEEXT)
+@SIM_ENABLE_ARCH_aarch64_TRUE@am__EXEEXT_11 = aarch64/run$(EXEEXT)
+@SIM_ENABLE_ARCH_arm_TRUE@am__EXEEXT_12 = arm/run$(EXEEXT)
+@SIM_ENABLE_ARCH_avr_TRUE@am__EXEEXT_13 = avr/run$(EXEEXT)
+@SIM_ENABLE_ARCH_bfin_TRUE@am__EXEEXT_14 = bfin/run$(EXEEXT)
+@SIM_ENABLE_ARCH_bpf_TRUE@am__EXEEXT_15 = bpf/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cr16_TRUE@am__EXEEXT_16 = cr16/run$(EXEEXT)
+@SIM_ENABLE_ARCH_cris_TRUE@am__EXEEXT_17 = cris/run$(EXEEXT)
+@SIM_ENABLE_ARCH_d10v_TRUE@am__EXEEXT_18 = d10v/run$(EXEEXT)
+@SIM_ENABLE_ARCH_erc32_TRUE@am__EXEEXT_19 = erc32/run$(EXEEXT) \
@SIM_ENABLE_ARCH_erc32_TRUE@ erc32/sis$(EXEEXT)
-@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_18 = \
+@SIM_ENABLE_ARCH_examples_TRUE@am__EXEEXT_20 = \
@SIM_ENABLE_ARCH_examples_TRUE@ example-synacor/run$(EXEEXT)
-@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_19 = frv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_20 = ft32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_21 = h8300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_22 = iq2000/run$(EXEEXT)
-@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_23 = lm32/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_24 = m32c/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_25 = m32r/run$(EXEEXT)
-@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_26 = m68hc11/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_27 = mcore/run$(EXEEXT)
-@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_28 = \
+@SIM_ENABLE_ARCH_frv_TRUE@am__EXEEXT_21 = frv/run$(EXEEXT)
+@SIM_ENABLE_ARCH_ft32_TRUE@am__EXEEXT_22 = ft32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_h8300_TRUE@am__EXEEXT_23 = h8300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_iq2000_TRUE@am__EXEEXT_24 = iq2000/run$(EXEEXT)
+@SIM_ENABLE_ARCH_lm32_TRUE@am__EXEEXT_25 = lm32/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m32c_TRUE@am__EXEEXT_26 = m32c/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m32r_TRUE@am__EXEEXT_27 = m32r/run$(EXEEXT)
+@SIM_ENABLE_ARCH_m68hc11_TRUE@am__EXEEXT_28 = m68hc11/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mcore_TRUE@am__EXEEXT_29 = mcore/run$(EXEEXT)
+@SIM_ENABLE_ARCH_microblaze_TRUE@am__EXEEXT_30 = \
@SIM_ENABLE_ARCH_microblaze_TRUE@ microblaze/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_29 = mips/run$(EXEEXT)
-@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_30 = mn10300/run$(EXEEXT)
-@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_31 = moxie/run$(EXEEXT)
-@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_32 = msp430/run$(EXEEXT)
-@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_33 = or1k/run$(EXEEXT)
-@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_34 = ppc/run$(EXEEXT)
-@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_35 = pru/run$(EXEEXT)
-@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_36 = riscv/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_37 = rl78/run$(EXEEXT)
-@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_38 = rx/run$(EXEEXT)
-@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_39 = sh/run$(EXEEXT)
-@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_40 = v850/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mips_TRUE@am__EXEEXT_31 = mips/run$(EXEEXT)
+@SIM_ENABLE_ARCH_mn10300_TRUE@am__EXEEXT_32 = mn10300/run$(EXEEXT)
+@SIM_ENABLE_ARCH_moxie_TRUE@am__EXEEXT_33 = moxie/run$(EXEEXT)
+@SIM_ENABLE_ARCH_msp430_TRUE@am__EXEEXT_34 = msp430/run$(EXEEXT)
+@SIM_ENABLE_ARCH_or1k_TRUE@am__EXEEXT_35 = or1k/run$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@am__EXEEXT_36 = ppc/run$(EXEEXT)
+@SIM_ENABLE_ARCH_pru_TRUE@am__EXEEXT_37 = pru/run$(EXEEXT)
+@SIM_ENABLE_ARCH_riscv_TRUE@am__EXEEXT_38 = riscv/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rl78_TRUE@am__EXEEXT_39 = rl78/run$(EXEEXT)
+@SIM_ENABLE_ARCH_rx_TRUE@am__EXEEXT_40 = rx/run$(EXEEXT)
+@SIM_ENABLE_ARCH_sh_TRUE@am__EXEEXT_41 = sh/run$(EXEEXT)
+@SIM_ENABLE_ARCH_v850_TRUE@am__EXEEXT_42 = v850/run$(EXEEXT)
PROGRAMS = $(noinst_PROGRAMS)
am_aarch64_run_OBJECTS =
aarch64_run_OBJECTS = $(am_aarch64_run_OBJECTS)
or1k_run_OBJECTS = $(am_or1k_run_OBJECTS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k_run_DEPENDENCIES = or1k/nrun.o \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/libsim.a $(am__DEPENDENCIES_4)
-am_ppc_run_OBJECTS =
+@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_igen_OBJECTS = ppc/igen.$(OBJEXT)
+ppc_igen_OBJECTS = $(am_ppc_igen_OBJECTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_DEPENDENCIES = ppc/libigen.a
+am_ppc_ld_cache_OBJECTS =
+ppc_ld_cache_OBJECTS = $(am_ppc_ld_cache_OBJECTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_cache_DEPENDENCIES = \
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+am_ppc_ld_decode_OBJECTS =
+ppc_ld_decode_OBJECTS = $(am_ppc_ld_decode_OBJECTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_decode_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode-main.o ppc/libigen.a
+am_ppc_ld_insn_OBJECTS =
+ppc_ld_insn_OBJECTS = $(am_ppc_ld_insn_OBJECTS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_ld_insn_DEPENDENCIES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn-main.o ppc/libigen.a
+@SIM_ENABLE_ARCH_ppc_TRUE@am_ppc_run_OBJECTS = ppc/main.$(OBJEXT)
ppc_run_OBJECTS = $(am_ppc_run_OBJECTS)
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_DEPENDENCIES = ppc/main.o \
-@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a $(am__DEPENDENCIES_4)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_DEPENDENCIES = ppc/libsim.a \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(am__DEPENDENCIES_4)
am_pru_run_OBJECTS =
pru_run_OBJECTS = $(am_pru_run_OBJECTS)
@SIM_ENABLE_ARCH_pru_TRUE@pru_run_DEPENDENCIES = pru/nrun.o \
$(nodist_mn10300_libsim_a_SOURCES) $(moxie_libsim_a_SOURCES) \
$(nodist_moxie_libsim_a_SOURCES) $(msp430_libsim_a_SOURCES) \
$(nodist_msp430_libsim_a_SOURCES) $(or1k_libsim_a_SOURCES) \
- $(nodist_or1k_libsim_a_SOURCES) $(pru_libsim_a_SOURCES) \
+ $(nodist_or1k_libsim_a_SOURCES) $(ppc_libigen_a_SOURCES) \
+ $(ppc_libsim_a_SOURCES) $(pru_libsim_a_SOURCES) \
$(nodist_pru_libsim_a_SOURCES) $(riscv_libsim_a_SOURCES) \
$(nodist_riscv_libsim_a_SOURCES) $(rl78_libsim_a_SOURCES) \
$(nodist_rl78_libsim_a_SOURCES) $(rx_libsim_a_SOURCES) \
$(m68hc11_run_SOURCES) $(mcore_run_SOURCES) \
$(microblaze_run_SOURCES) $(mips_run_SOURCES) \
$(mn10300_run_SOURCES) $(moxie_run_SOURCES) \
- $(msp430_run_SOURCES) $(or1k_run_SOURCES) $(ppc_run_SOURCES) \
- $(pru_run_SOURCES) $(riscv_run_SOURCES) $(rl78_run_SOURCES) \
- $(rx_run_SOURCES) $(sh_gencode_SOURCES) $(sh_run_SOURCES) \
+ $(msp430_run_SOURCES) $(or1k_run_SOURCES) $(ppc_igen_SOURCES) \
+ $(ppc_ld_cache_SOURCES) $(ppc_ld_decode_SOURCES) \
+ $(ppc_ld_insn_SOURCES) $(ppc_run_SOURCES) $(pru_run_SOURCES) \
+ $(riscv_run_SOURCES) $(rl78_run_SOURCES) $(rx_run_SOURCES) \
+ $(sh_gencode_SOURCES) $(sh_run_SOURCES) \
testsuite/common/alu-tst.c testsuite/common/bits-gen.c \
testsuite/common/bits32m0.c testsuite/common/bits32m31.c \
testsuite/common/bits64m0.c testsuite/common/bits64m63.c \
testsuite/common/fpu-tst.c $(v850_run_SOURCES)
-RECURSIVE_TARGETS = all-recursive check-recursive cscopelist-recursive \
- ctags-recursive dvi-recursive html-recursive info-recursive \
- install-data-recursive install-dvi-recursive \
- install-exec-recursive install-html-recursive \
- install-info-recursive install-pdf-recursive \
- install-ps-recursive install-recursive installcheck-recursive \
- installdirs-recursive pdf-recursive ps-recursive \
- tags-recursive uninstall-recursive
am__can_run_installinfo = \
case $$AM_UPDATE_INFO_DIR in \
n|no|NO) false;; \
am__pkginclude_HEADERS_DIST = $(srcroot)/include/sim/callback.h \
$(srcroot)/include/sim/sim.h
HEADERS = $(pkginclude_HEADERS)
-RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \
- distclean-recursive maintainer-clean-recursive
-am__recursive_targets = \
- $(RECURSIVE_TARGETS) \
- $(RECURSIVE_CLEAN_TARGETS) \
- $(am__extra_recursive_targets)
-AM_RECURSIVE_TARGETS = $(am__recursive_targets:-recursive=) TAGS CTAGS \
- cscope check recheck
am__tagged_files = $(HEADERS) $(SOURCES) $(TAGS_FILES) \
$(LISP)config.h.in
# Read a list of newline-separated strings from the standard input,
ETAGS = etags
CTAGS = ctags
CSCOPE = cscope
+AM_RECURSIVE_TARGETS = cscope check recheck
DEJATOOL = $(PACKAGE)
RUNTESTDEFAULTFLAGS = --tool $$tool --srcdir $$srcdir
EXPECT = expect
TEST_LOG_DRIVER = $(SHELL) $(top_srcdir)/../test-driver
TEST_LOG_COMPILE = $(TEST_LOG_COMPILER) $(AM_TEST_LOG_FLAGS) \
$(TEST_LOG_FLAGS)
-DIST_SUBDIRS = $(SUBDIRS)
ACLOCAL = @ACLOCAL@
AMTAR = @AMTAR@
AM_DEFAULT_VERBOSITY = @AM_DEFAULT_VERBOSITY@
AUTOHEADER = @AUTOHEADER@
AUTOMAKE = @AUTOMAKE@
AWK = @AWK@
+BUILD_WARN_CFLAGS = @BUILD_WARN_CFLAGS@
+BUILD_WERROR_CFLAGS = @BUILD_WERROR_CFLAGS@
CC = @CC@
CCDEPMODE = @CCDEPMODE@
CC_FOR_BUILD = @CC_FOR_BUILD@
SED = @SED@
SET_MAKE = @SET_MAKE@
SHELL = @SHELL@
+SIM_CFLAG_WNO_SHADOW_LOCAL = @SIM_CFLAG_WNO_SHADOW_LOCAL@
+SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE = @SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE@
SIM_ENABLED_ARCHES = @SIM_ENABLED_ARCHES@
SIM_FRV_TRAPDUMP_FLAGS = @SIM_FRV_TRAPDUMP_FLAGS@
SIM_HW_CFLAGS = @SIM_HW_CFLAGS@
psdir = @psdir@
sbindir = @sbindir@
sharedstatedir = @sharedstatedir@
+sim_ppc_bitsize = @sim_ppc_bitsize@
+sim_ppc_decode_mechanism = @sim_ppc_decode_mechanism@
+sim_ppc_default_model = @sim_ppc_default_model@
+sim_ppc_dup = @sim_ppc_dup@
+sim_ppc_filter = @sim_ppc_filter@
+sim_ppc_float = @sim_ppc_float@
+sim_ppc_hw_obj = @sim_ppc_hw_obj@
+sim_ppc_hw_src = @sim_ppc_hw_src@
+sim_ppc_icache = @sim_ppc_icache@
+sim_ppc_igen_smp = @sim_ppc_igen_smp@
+sim_ppc_jump = @sim_ppc_jump@
+sim_ppc_line_nr = @sim_ppc_line_nr@
+sim_ppc_model = @sim_ppc_model@
+sim_ppc_model_issue = @sim_ppc_model_issue@
+sim_ppc_monitor = @sim_ppc_monitor@
+sim_ppc_opcode = @sim_ppc_opcode@
+sim_ppc_smp = @sim_ppc_smp@
+sim_ppc_switch = @sim_ppc_switch@
+sim_ppc_timebase = @sim_ppc_timebase@
+sim_ppc_xor_endian = @sim_ppc_xor_endian@
srcdir = @srcdir@
-subdirs = @subdirs@
sysconfdir = @sysconfdir@
target = @target@
target_alias = @target_alias@
GNULIB_PARENT_DIR = ..
srccom = $(srcdir)/common
srcroot = $(srcdir)/..
-SUBDIRS = @subdirs@
pkginclude_HEADERS = $(am__append_1)
-EXTRA_LIBRARIES = igen/libigen.a
+EXTRA_LIBRARIES = igen/libigen.a $(am__append_101)
noinst_LIBRARIES = common/libcommon.a $(am__append_3) $(am__append_5) \
$(am__append_7) $(am__append_9) $(am__append_11) \
- $(am__append_15) $(am__append_20) $(am__append_25) \
- $(am__append_30) $(am__append_34) $(am__append_36) \
- $(am__append_40) $(am__append_42) $(am__append_44) \
- $(am__append_48) $(am__append_52) $(am__append_56) \
- $(am__append_60) $(am__append_64) $(am__append_66) \
- $(am__append_71) $(am__append_79) $(am__append_83) \
- $(am__append_85) $(am__append_87) $(am__append_93) \
- $(am__append_95) $(am__append_97) $(am__append_99) \
- $(am__append_101) $(am__append_106)
-BUILT_SOURCES = $(am__append_13) $(am__append_17) $(am__append_23) \
- $(am__append_27) $(am__append_38) $(am__append_46) \
- $(am__append_50) $(am__append_58) $(am__append_73) \
- $(am__append_81) $(am__append_89) $(am__append_103) \
- $(am__append_108)
+ $(am__append_13) $(am__append_19) $(am__append_25) \
+ $(am__append_31) $(am__append_35) $(am__append_37) \
+ $(am__append_42) $(am__append_44) $(am__append_46) \
+ $(am__append_51) $(am__append_56) $(am__append_60) \
+ $(am__append_65) $(am__append_69) $(am__append_71) \
+ $(am__append_76) $(am__append_84) $(am__append_88) \
+ $(am__append_90) $(am__append_92) $(am__append_97) \
+ $(am__append_103) $(am__append_105) $(am__append_107) \
+ $(am__append_109) $(am__append_111) $(am__append_116)
+BUILT_SOURCES = $(am__append_15) $(am__append_22) $(am__append_27) \
+ $(am__append_39) $(am__append_48) $(am__append_53) \
+ $(am__append_62) $(am__append_78) $(am__append_86) \
+ $(am__append_94) $(am__append_99) $(am__append_113) \
+ $(am__append_118)
CLEANFILES = common/version.c common/version.c-stamp \
testsuite/common/bits-gen testsuite/common/bits32m0.c \
testsuite/common/bits32m31.c testsuite/common/bits64m0.c \
- testsuite/common/bits64m63.c
-DISTCLEANFILES = $(am__append_78)
+ testsuite/common/bits64m63.c $(am__append_17) $(am__append_23) \
+ $(am__append_29) $(am__append_40) $(am__append_49) \
+ $(am__append_54) $(am__append_63) $(am__append_95)
+DISTCLEANFILES = $(am__append_83)
MOSTLYCLEANFILES = core $(SIM_ENABLED_ARCHES:%=%/*.o) \
$(SIM_ENABLED_ARCHES:%=%/hw-config.h) \
$(SIM_ENABLED_ARCHES:%=%/stamp-hw) \
$(SIM_ENABLED_ARCHES:%=%/modules.c) \
$(SIM_ENABLED_ARCHES:%=%/stamp-modules) $(igen_IGEN_TOOLS) \
- site-sim-config.exp testrun.log testrun.sum $(am__append_14) \
- $(am__append_19) $(am__append_24) $(am__append_29) \
- $(am__append_39) $(am__append_47) $(am__append_51) \
- $(am__append_55) $(am__append_59) $(am__append_63) \
- $(am__append_77) $(am__append_82) $(am__append_90) \
- $(am__append_105) $(am__append_109)
+ igen/libigen.a site-sim-config.exp testrun.log testrun.sum \
+ $(am__append_18) $(am__append_24) $(am__append_30) \
+ $(am__append_41) $(am__append_50) $(am__append_55) \
+ $(am__append_59) $(am__append_64) $(am__append_68) \
+ $(am__append_82) $(am__append_87) $(am__append_96) \
+ $(am__append_100) $(am__append_115) $(am__append_119)
+CONFIG_STATUS_DEPENDENCIES = $(srcroot)/bfd/development.sh
AM_CFLAGS = \
$(WERROR_CFLAGS) \
$(WARN_CFLAGS) \
-,_,$(@D)_$(@F))) -I$(srcdir)/common -DSIM_TOPDIR_BUILD
AM_CPPFLAGS_FOR_BUILD = -I$(srcroot)/include $(SIM_HW_CFLAGS) \
$(SIM_INLINE) -I$(srcdir)/common
-COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD)
+COMPILE_FOR_BUILD = $(CC_FOR_BUILD) $(AM_CPPFLAGS_FOR_BUILD) $(CPPFLAGS_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(BUILD_WERROR_CFLAGS) $(BUILD_WARN_CFLAGS)
LINK_FOR_BUILD = $(CC_FOR_BUILD) $(CFLAGS_FOR_BUILD) $(LDFLAGS_FOR_BUILD) -o $@
-SIM_ALL_RECURSIVE_DEPS = $(am__append_91)
SIM_INSTALL_DATA_LOCAL_DEPS =
-SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_32)
-SIM_UNINSTALL_LOCAL_DEPS = $(am__append_33)
+SIM_INSTALL_EXEC_LOCAL_DEPS = $(am__append_33)
+SIM_UNINSTALL_LOCAL_DEPS = $(am__append_34)
SIM_DEPBASE = $(@D)/$(DEPDIR)/$(@F:.o=)
SIM_COMPILE = \
$(AM_V_CC)$(COMPILE) -MT $@ -MD -MP -MF $(SIM_DEPBASE).Tpo -c -o $@ $< && \
common/callback.c \
common/portability.c \
common/sim-load.c \
+ common/sim-signal.c \
common/syscall.c \
common/target-newlib-errno.c \
common/target-newlib-open.c \
sim-command.o sim-config.o sim-core.o sim-cpu.o sim-endian.o \
sim-engine.o sim-events.o sim-fpu.o sim-hload.o sim-hrw.o \
sim-io.o sim-info.o sim-memopt.o sim-model.o sim-module.o \
- sim-options.o sim-profile.o sim-reason.o sim-reg.o \
- sim-signal.o sim-stop.o sim-syscall.o sim-trace.o sim-utils.o \
- sim-watch.o $(am__append_2)
+ sim-options.o sim-profile.o sim-reason.o sim-reg.o sim-stop.o \
+ sim-syscall.o sim-trace.o sim-utils.o sim-watch.o \
+ $(am__append_2)
SIM_HW_DEVICES = cfi core pal glue
am_arch_d = $(subst -,_,$(@D))
GEN_MODULES_C_SRCS = \
$(LIBGNU) \
$(LIBGNU_EXTRA_LIBS)
-GUILE = $(or $(wildcard ../guile/libguile/guile),guile)
+GUILE = guile
CGEN = "$(GUILE) -l $(cgendir)/guile.scm -s"
CGENFLAGS = -v
CGEN_CPU_DIR = $(cgendir)/cpu
$(@D) "$$FLAGS" $$cpu "$$isa" $$mach "$$SUFFIX" \
$(CGEN_ARCHFILE) ignored $$opcfile
+CGEN_GEN_MLOOP = \
+ $(SHELL) $(srccom)/lineno.sh \
+ $(srccom)/genmloop.sh \
+ $@.lineno.sh \
+ -shell $(SHELL) -awk $(AWK) -lineno $(srccom)/lineno.sh \
+ -infile $< -outfile-prefix $(@D)/
+
# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_bfin_TRUE@ bfin_wp \
@SIM_ENABLE_ARCH_bfin_TRUE@ eth_phy
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf = -DWITH_TARGET_WORD_BITSIZE=64
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_mloop_le.o = -DWANT_ISA_EBPFLE
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_mloop_be.o = -DWANT_ISA_EBPFBE
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_decode_le.o = -DWANT_ISA_EBPFLE
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_decode_be.o = -DWANT_ISA_EBPFBE
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_sem_le.o = -DWANT_ISA_EBPFLE
-@SIM_ENABLE_ARCH_bpf_TRUE@AM_CPPFLAGS_bpf_sem_be.o = -DWANT_ISA_EBPFBE
@SIM_ENABLE_ARCH_bpf_TRUE@nodist_bpf_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/modules.c
@SIM_ENABLE_ARCH_bpf_TRUE@ $(common_libcommon_a_SOURCES)
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-sim.o \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/%,$(SIM_NEW_COMMON_OBJS)) \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(patsubst %,bpf/dv-%.o,$(SIM_HW_DEVICES)) \
-@SIM_ENABLE_ARCH_bpf_TRUE@ \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-run.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-scache.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-trace.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cgen-utils.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/arch.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/cpu.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/decode-be.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sem-be.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/bpf-helpers.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-if.o \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/traps.o
+@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/sim-resume.o
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_SOURCES =
@SIM_ENABLE_ARCH_bpf_TRUE@bpf_run_LDADD = \
@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/libsim.a \
@SIM_ENABLE_ARCH_bpf_TRUE@ $(SIM_COMMON_LIBS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf_BUILD_OUTPUTS = \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-le.c \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-le \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/mloop-be.c \
-@SIM_ENABLE_ARCH_bpf_TRUE@ bpf/stamp-mloop-be
-
@SIM_ENABLE_ARCH_cr16_TRUE@nodist_cr16_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cr16_TRUE@ cr16/modules.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_SOURCES = cr16/gencode.c
@SIM_ENABLE_ARCH_cr16_TRUE@cr16_gencode_LDADD = cr16/cr16-opc.o
+@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv10f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE) \
+@SIM_ENABLE_ARCH_cris_TRUE@ $(SIM_CFLAG_WNO_SHADOW_LOCAL)
+@SIM_ENABLE_ARCH_cris_TRUE@AM_CFLAGS_cris_mloopv32f.o = $(SIM_CFLAG_WNO_UNUSED_BUT_SET_VARIABLE)
@SIM_ENABLE_ARCH_cris_TRUE@nodist_cris_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_cris_TRUE@ cris/modules.c
@SIM_ENABLE_ARCH_examples_TRUE@ $(SIM_COMMON_LIBS)
@SIM_ENABLE_ARCH_frv_TRUE@AM_CPPFLAGS_frv = $(SIM_FRV_TRAPDUMP_FLAGS)
-@SIM_ENABLE_ARCH_frv_TRUE@AM_CFLAGS_frv_memory.o = -Wno-error
@SIM_ENABLE_ARCH_frv_TRUE@AM_CFLAGS_frv_sem.o = -Wno-error
@SIM_ENABLE_ARCH_frv_TRUE@nodist_frv_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_frv_TRUE@ frv/modules.c
# opc2c leaks memory, and therefore makes AddressSanitizer unhappy. Disable
# leak detection while running it.
@SIM_ENABLE_ARCH_m32c_TRUE@m32c_OPC2C_RUN = ASAN_OPTIONS=detect_leaks=0 m32c/opc2c$(EXEEXT)
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpu2.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_cpux.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32r2.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_m32rx.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloop2.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_mloopx.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sem.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_sim_if.o = -Wno-error
-@SIM_ENABLE_ARCH_m32r_TRUE@AM_CFLAGS_m32r_traps.o = -Wno-error
@SIM_ENABLE_ARCH_m32r_TRUE@nodist_m32r_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_m32r_TRUE@ m32r/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_TARGET_WORD_BITSIZE=@SIM_MIPS_BITSIZE@ -DWITH_TARGET_WORD_MSB=WITH_TARGET_WORD_BITSIZE-1 \
@SIM_ENABLE_ARCH_mips_TRUE@ -DWITH_FLOATING_POINT=HARD_FLOATING_POINT -DWITH_TARGET_FLOATING_POINT_BITSIZE=@SIM_MIPS_FPU_BITSIZE@
-@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_68) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_69) $(am__append_70)
+@SIM_ENABLE_ARCH_mips_TRUE@mips_GEN_OBJ = $(am__append_73) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75)
@SIM_ENABLE_ARCH_mips_TRUE@nodist_mips_libsim_a_SOURCES = \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/modules.c
@SIM_ENABLE_ARCH_mips_TRUE@mips_BUILD_OUTPUTS = \
@SIM_ENABLE_ARCH_mips_TRUE@ $(mips_BUILT_SRC_FROM_IGEN_ITABLE) \
@SIM_ENABLE_ARCH_mips_TRUE@ mips/stamp-igen-itable \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_74) $(am__append_75) \
-@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_76)
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_79) $(am__append_80) \
+@SIM_ENABLE_ARCH_mips_TRUE@ $(am__append_81)
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_TRACE = # -G omit-line-numbers # -G trace-rule-selection -G trace-rule-rejection -G trace-entries # -G trace-all
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN = $(srcdir)/mips/mips.igen
@SIM_ENABLE_ARCH_mips_TRUE@mips_IGEN_INSN_INC = \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/mloop.c \
@SIM_ENABLE_ARCH_or1k_TRUE@ or1k/stamp-mloop
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES =
+@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -DHAVE_COMMON_FPU \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_smp) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_xor_endian) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_bitsize) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_timebase) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_float) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_monitor) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_model) $(sim_ppc_default_model) $(sim_ppc_model_issue) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(sim_ppc_switch)
+
+@SIM_ENABLE_ARCH_ppc_TRUE@AM_CPPFLAGS_ppc_options.o = '-DOPCODE_RULES="$(IGEN_OPCODE_RULES)"' '-DIGEN_FLAGS="$(ppc_IGEN_FLAGS)"'
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_SOURCES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(common_libcommon_a_SOURCES)
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libsim_a_LIBADD = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/debug.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/bits.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-endian.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/os_emul.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_generic.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_bugapi.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_chirp.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_netbsd.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/emul_unix.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/registers.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/vm.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/corefile.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/model.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/spreg.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/interrupts.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/events.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/cap.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/tree.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/device_table.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/itable.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/mon.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/semantics.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/support.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim-fpu.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/psim.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/pk_disklabel.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(patsubst %,ppc/%,$(sim_ppc_hw_obj)) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/options.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gdb-sim.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/sim_calls.o
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_SOURCES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.c
+
@SIM_ENABLE_ARCH_ppc_TRUE@ppc_run_LDADD = \
-@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/main.o \
@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/libsim.a \
@SIM_ENABLE_ARCH_ppc_TRUE@ $(SIM_COMMON_LIBS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_SOURCES = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/table.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/lf-ppc.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/dumpf.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-decode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-cache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/filter-ppc.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/ld-insn.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-model.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-itable.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-icache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-semantics.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-idecode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/gen-support.c
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_libigen_a_LIBADD = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/filter_host.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/lf.o \
+@SIM_ENABLE_ARCH_ppc_TRUE@ igen/misc.o
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_SOURCES = ppc/igen.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_igen_LDADD = ppc/libigen.a
+
+# igen leaks memory, and therefore makes AddressSanitizer unhappy. Disable
+# leak detection while running it.
+@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN = ppc/igen$(EXEEXT)
+@SIM_ENABLE_ARCH_ppc_TRUE@PPC_IGEN_RUN = ASAN_OPTIONS=detect_leaks=0 $(PPC_IGEN) $(ppc_IGEN_FLAGS)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_IGEN_FLAGS = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_decode_mechanism@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_dup@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_jump@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_filter@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_icache@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_igen_smp@ \
+@SIM_ENABLE_ARCH_ppc_TRUE@ @sim_ppc_line_nr@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc_BUILT_SRC_FROM_IGEN = \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/icache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ ppc/idecode.h \
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- am--refresh check check-DEJAGNU check-TESTS check-am clean \
- clean-checkPROGRAMS clean-cscope clean-generic clean-libtool \
- clean-noinstLIBRARIES clean-noinstPROGRAMS cscope \
- cscopelist-am ctags ctags-am distclean distclean-DEJAGNU \
- distclean-compile distclean-generic distclean-hdr \
- distclean-libtool distclean-tags dvi dvi-am html html-am info \
- info-am install install-am install-armdocDATA install-data \
- install-data-am install-data-local install-dtbDATA install-dvi \
- install-dvi-am install-erc32docDATA install-exec \
- install-exec-am install-exec-local install-frvdocDATA \
- install-html install-html-am install-info install-info-am \
- install-man install-or1kdocDATA install-pdf install-pdf-am \
+.MAKE: all check check-am install install-am install-strip
+
+.PHONY: CTAGS GTAGS TAGS all all-am am--refresh check check-DEJAGNU \
+ check-TESTS check-am clean clean-checkPROGRAMS clean-cscope \
+ clean-generic clean-libtool clean-noinstLIBRARIES \
+ clean-noinstPROGRAMS cscope cscopelist-am ctags ctags-am \
+ distclean distclean-DEJAGNU distclean-compile \
+ distclean-generic distclean-hdr distclean-libtool \
+ distclean-tags dvi dvi-am html html-am info info-am install \
+ install-am install-armdocDATA install-data install-data-am \
+ install-data-local install-dtbDATA install-dvi install-dvi-am \
+ install-erc32docDATA install-exec install-exec-am \
+ install-exec-local install-frvdocDATA install-html \
+ install-html-am install-info install-info-am install-man \
+ install-or1kdocDATA install-pdf install-pdf-am \
install-pkgincludeHEADERS install-ppcdocDATA install-ps \
install-ps-am install-rxdocDATA install-strip installcheck \
- installcheck-am installdirs installdirs-am maintainer-clean \
+ installcheck-am installdirs maintainer-clean \
maintainer-clean-generic mostlyclean mostlyclean-compile \
mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \
recheck tags tags-am uninstall uninstall-am \
@SIM_ENABLE_ARCH_bpf_TRUE@bpf/%.o: common/%.c ; $(SIM_COMPILE)
@SIM_ENABLE_ARCH_bpf_TRUE@-@am__include@ bpf/$(DEPDIR)/*.Po
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/modules.c: | $(bpf_BUILD_OUTPUTS)
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-le.c bpf/eng-le.h: bpf/stamp-mloop-le ; @true
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/stamp-mloop-le: $(srccom)/genmloop.sh bpf/mloop.in
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
-@SIM_ENABLE_ARCH_bpf_TRUE@ -mono -scache -prefix bpfbf_ebpfle -cpu bpfbf \
-@SIM_ENABLE_ARCH_bpf_TRUE@ -infile $(srcdir)/bpf/mloop.in \
-@SIM_ENABLE_ARCH_bpf_TRUE@ -outfile-prefix bpf/ -outfile-suffix -le
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/eng-le.hin bpf/eng-le.h
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/mloop-le.cin bpf/mloop-le.c
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)touch $@
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/mloop-be.c bpf/eng-be.h: bpf/stamp-mloop-be ; @true
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/stamp-mloop-be: $(srccom)/genmloop.sh bpf/mloop.in
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
-@SIM_ENABLE_ARCH_bpf_TRUE@ -mono -scache -prefix bpfbf_ebpfbe -cpu bpfbf \
-@SIM_ENABLE_ARCH_bpf_TRUE@ -infile $(srcdir)/bpf/mloop.in \
-@SIM_ENABLE_ARCH_bpf_TRUE@ -outfile-prefix bpf/ -outfile-suffix -be
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/eng-be.hin bpf/eng-be.h
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change bpf/mloop-be.cin bpf/mloop-be.c
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)touch $@
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen: bpf/cgen-arch bpf/cgen-cpu bpf/cgen-defs-le bpf/cgen-defs-be bpf/cgen-decode-le bpf/cgen-decode-be
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-arch:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)mach=bpf cpu=bpfbf FLAGS="with-scache"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/arch.h bpf/arch.c bpf/cpuall.h: @CGEN_MAINT@ bpf/cgen-arch
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-cpu:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle,ebpfbe cpu=bpfbf mach=bpf FLAGS="with-multiple-isa with-scache"; $(CGEN_GEN_CPU)
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_at)rm -f $(srcdir)/bpf/model.c
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cpu.h bpf/cpu.c bpf/model.c: @CGEN_MAINT@ bpf/cgen-cpu
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-le:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le"; $(CGEN_GEN_DEFS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-le.h: @CGEN_MAINT@ bpf/cgen-defs-le
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-defs-be:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be"; $(CGEN_GEN_DEFS)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/defs-be.h: @CGEN_MAINT@ bpf/cgen-defs-be
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-le:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfle cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-le" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-le.c bpf/decode-le.c bpf/decode-le.h: @CGEN_MAINT@ bpf/cgen-decode-vle
-
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/cgen-decode-be:
-@SIM_ENABLE_ARCH_bpf_TRUE@ $(AM_V_GEN)isa=ebpfbe cpu=bpfbf mach=bpf FLAGS="with-scache" SUFFIX="-be" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_DECODE)
-@SIM_ENABLE_ARCH_bpf_TRUE@bpf/sem-be.c bpf/decode-be.c bpf/decode-be.h: @CGEN_MAINT@ bpf/cgen-decode-be
@SIM_ENABLE_ARCH_cr16_TRUE@$(cr16_libsim_a_OBJECTS) $(cr16_libsim_a_LIBADD): cr16/hw-config.h
@SIM_ENABLE_ARCH_cr16_TRUE@cr16/modules.o: cr16/modules.c
@SIM_ENABLE_ARCH_cris_TRUE@cris/modules.c: | $(cris_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv10f.c cris/engv10.h: cris/stamp-mloop-v10f ; @true
-@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f: $(srccom)/genmloop.sh cris/mloop.in
-@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v10f: cris/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_cris_TRUE@ -mono -no-fast -pbb -switch semcrisv10f-switch.c \
-@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv10f \
-@SIM_ENABLE_ARCH_cris_TRUE@ -infile $(srcdir)/cris/mloop.in -outfile-prefix cris/ -outfile-suffix -v10f
+@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv10f -outfile-suffix -v10f
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v10f.hin cris/engv10.h
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v10f.cin cris/mloopv10f.c
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_cris_TRUE@cris/mloopv32f.c cris/engv32.h: cris/stamp-mloop-v32f ; @true
-@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f: $(srccom)/genmloop.sh cris/mloop.in
-@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_cris_TRUE@cris/stamp-mloop-v32f: cris/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_cris_TRUE@ -mono -no-fast -pbb -switch semcrisv32f-switch.c \
-@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv32f \
-@SIM_ENABLE_ARCH_cris_TRUE@ -infile $(srcdir)/cris/mloop.in -outfile-prefix cris/ -outfile-suffix -v32f
+@SIM_ENABLE_ARCH_cris_TRUE@ -cpu crisv32f -outfile-suffix -v32f
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/eng-v32f.hin cris/engv32.h
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change cris/mloop-v32f.cin cris/mloopv32f.c
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-arch:
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)mach=crisv10,crisv32 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_cris_TRUE@cris/arch.h cris/arch.c cris/cpuall.h: @CGEN_MAINT@ cris/cgen-arch
+@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/arch.h $(srcdir)/cris/arch.c $(srcdir)/cris/cpuall.h: @CGEN_MAINT@ cris/cgen-arch
@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v10f:
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=crisv10f mach=crisv10 SUFFIX=v10 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv10-switch.c $(srcdir)/cris/semcrisv10f-switch.c
-@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv10.h cris/cpuv10.c cris/semcrisv10f-switch.c cris/modelv10.c cris/decodev10.c cris/decodev10.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v10f
+@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/cpuv10.h $(srcdir)/cris/cpuv10.c $(srcdir)/cris/semcrisv10f-switch.c $(srcdir)/cris/modelv10.c $(srcdir)/cris/decodev10.c $(srcdir)/cris/decodev10.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v10f
@SIM_ENABLE_ARCH_cris_TRUE@cris/cgen-cpu-decode-v32f:
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_GEN)cpu=crisv32f mach=crisv32 SUFFIX=v32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
@SIM_ENABLE_ARCH_cris_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $(srcdir)/cris/semv32-switch.c $(srcdir)/cris/semcrisv32f-switch.c
-@SIM_ENABLE_ARCH_cris_TRUE@cris/cpuv32.h cris/cpuv32.c cris/semcrisv32f-switch.c cris/modelv32.c cris/decodev32.c cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f
+@SIM_ENABLE_ARCH_cris_TRUE@$(srcdir)/cris/cpuv32.h $(srcdir)/cris/cpuv32.c $(srcdir)/cris/semcrisv32f-switch.c $(srcdir)/cris/modelv32.c $(srcdir)/cris/decodev32.c $(srcdir)/cris/decodev32.h: @CGEN_MAINT@ cris/cgen-cpu-decode-v32f
@SIM_ENABLE_ARCH_d10v_TRUE@$(d10v_libsim_a_OBJECTS) $(d10v_libsim_a_LIBADD): d10v/hw-config.h
@SIM_ENABLE_ARCH_d10v_TRUE@d10v/modules.o: d10v/modules.c
@SIM_ENABLE_ARCH_frv_TRUE@frv/modules.c: | $(frv_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_frv_TRUE@frv/mloop.c frv/eng.h: frv/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: $(srccom)/genmloop.sh frv/mloop.in
-@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_frv_TRUE@frv/stamp-mloop: frv/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_frv_TRUE@ -mono -scache -parallel-generic-write -parallel-only \
-@SIM_ENABLE_ARCH_frv_TRUE@ -cpu frvbf \
-@SIM_ENABLE_ARCH_frv_TRUE@ -infile $(srcdir)/frv/mloop.in -outfile-prefix frv/
+@SIM_ENABLE_ARCH_frv_TRUE@ -cpu frvbf
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/eng.hin frv/eng.h
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change frv/mloop.cin frv/mloop.c
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-arch:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_frv_TRUE@frv/arch.h frv/arch.c frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch
+@SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/arch.h $(srcdir)/frv/arch.c $(srcdir)/frv/cpuall.h: @CGEN_MAINT@ frv/cgen-arch
@SIM_ENABLE_ARCH_frv_TRUE@frv/cgen-cpu-decode:
@SIM_ENABLE_ARCH_frv_TRUE@ $(AM_V_GEN)cpu=frvbf mach=frv,fr550,fr500,fr450,fr400,tomcat,simple FLAGS="with-scache with-profile=fn with-generic-write with-parallel-only" EXTRAFILES="$(CGEN_CPU_SEM)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_frv_TRUE@frv/cpu.h frv/sem.c frv/model.c frv/decode.c frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
+@SIM_ENABLE_ARCH_frv_TRUE@$(srcdir)/frv/cpu.h $(srcdir)/frv/sem.c $(srcdir)/frv/model.c $(srcdir)/frv/decode.c $(srcdir)/frv/decode.h: @CGEN_MAINT@ frv/cgen-cpu-decode
@SIM_ENABLE_ARCH_ft32_TRUE@$(ft32_libsim_a_OBJECTS) $(ft32_libsim_a_LIBADD): ft32/hw-config.h
@SIM_ENABLE_ARCH_ft32_TRUE@ft32/modules.o: ft32/modules.c
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/modules.c: | $(iq2000_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/mloop.c iq2000/eng.h: iq2000/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: $(srccom)/genmloop.sh iq2000/mloop.in
-@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/stamp-mloop: iq2000/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_iq2000_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_iq2000_TRUE@ -cpu iq2000bf \
-@SIM_ENABLE_ARCH_iq2000_TRUE@ -infile $(srcdir)/iq2000/mloop.in -outfile-prefix iq2000/
+@SIM_ENABLE_ARCH_iq2000_TRUE@ -cpu iq2000bf
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/eng.hin iq2000/eng.h
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change iq2000/mloop.cin iq2000/mloop.c
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-arch:
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)mach=iq2000 FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/arch.h iq2000/arch.c iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch
+@SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/arch.h $(srcdir)/iq2000/arch.c $(srcdir)/iq2000/cpuall.h: @CGEN_MAINT@ iq2000/cgen-arch
@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cgen-cpu-decode:
@SIM_ENABLE_ARCH_iq2000_TRUE@ $(AM_V_GEN)cpu=iq2000bf mach=iq2000 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_iq2000_TRUE@iq2000/cpu.h iq2000/sem.c iq2000/sem-switch.c iq2000/model.c iq2000/decode.c iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
+@SIM_ENABLE_ARCH_iq2000_TRUE@$(srcdir)/iq2000/cpu.h $(srcdir)/iq2000/sem.c $(srcdir)/iq2000/sem-switch.c $(srcdir)/iq2000/model.c $(srcdir)/iq2000/decode.c $(srcdir)/iq2000/decode.h: @CGEN_MAINT@ iq2000/cgen-cpu-decode
@SIM_ENABLE_ARCH_lm32_TRUE@$(lm32_libsim_a_OBJECTS) $(lm32_libsim_a_LIBADD): lm32/hw-config.h
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.o: lm32/modules.c
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/modules.c: | $(lm32_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/mloop.c lm32/eng.h: lm32/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: $(srccom)/genmloop.sh lm32/mloop.in
-@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_lm32_TRUE@lm32/stamp-mloop: lm32/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_lm32_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_lm32_TRUE@ -cpu lm32bf \
-@SIM_ENABLE_ARCH_lm32_TRUE@ -infile $(srcdir)/lm32/mloop.in -outfile-prefix lm32/
+@SIM_ENABLE_ARCH_lm32_TRUE@ -cpu lm32bf
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/eng.hin lm32/eng.h
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change lm32/mloop.cin lm32/mloop.c
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-arch:
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_lm32_TRUE@lm32/arch.h lm32/arch.c lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch
+@SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/arch.h $(srcdir)/lm32/arch.c $(srcdir)/lm32/cpuall.h: @CGEN_MAINT@ lm32/cgen-arch
@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cgen-cpu-decode:
@SIM_ENABLE_ARCH_lm32_TRUE@ $(AM_V_GEN)cpu=lm32bf mach=lm32 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_lm32_TRUE@lm32/cpu.h lm32/sem.c lm32/sem-switch.c lm32/model.c lm32/decode.c lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
+@SIM_ENABLE_ARCH_lm32_TRUE@$(srcdir)/lm32/cpu.h $(srcdir)/lm32/sem.c $(srcdir)/lm32/sem-switch.c $(srcdir)/lm32/model.c $(srcdir)/lm32/decode.c $(srcdir)/lm32/decode.h: @CGEN_MAINT@ lm32/cgen-cpu-decode
@SIM_ENABLE_ARCH_m32c_TRUE@$(m32c_libsim_a_OBJECTS) $(m32c_libsim_a_LIBADD): m32c/hw-config.h
@SIM_ENABLE_ARCH_m32c_TRUE@m32c/modules.o: m32c/modules.c
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/modules.c: | $(m32r_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop.c m32r/eng.h: m32r/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: $(srccom)/genmloop.sh m32r/mloop.in
-@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop: m32r/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rbf \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloop.in -outfile-prefix m32r/
+@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rbf
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng.hin m32r/eng.h
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop.cin m32r/mloop.c
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloopx.c m32r/engx.h: m32r/stamp-mloop-x ; @true
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: $(srccom)/genmloop.sh m32r/mloop.in
-@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-x: m32r/mloopx.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch semx-switch.c \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rxf \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloopx.in -outfile-prefix m32r/ -outfile-suffix x
+@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32rxf -outfile-suffix x
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/engx.hin m32r/engx.h
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloopx.cin m32r/mloopx.c
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/mloop2.c m32r/eng2.h: m32r/stamp-mloop-2 ; @true
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: $(srccom)/genmloop.sh m32r/mloop.in
-@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_m32r_TRUE@m32r/stamp-mloop-2: m32r/mloop2.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_m32r_TRUE@ -mono -no-fast -pbb -parallel-write -switch sem2-switch.c \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32r2f \
-@SIM_ENABLE_ARCH_m32r_TRUE@ -infile $(srcdir)/m32r/mloop2.in -outfile-prefix m32r/ -outfile-suffix 2
+@SIM_ENABLE_ARCH_m32r_TRUE@ -cpu m32r2f -outfile-suffix 2
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/eng2.hin m32r/eng2.h
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change m32r/mloop2.cin m32r/mloop2.c
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-arch:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)mach=all FLAGS="with-scache with-profile=fn"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/arch.h m32r/arch.c m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/arch.h $(srcdir)/m32r/arch.c $(srcdir)/m32r/cpuall.h: @CGEN_MAINT@ m32r/cgen-arch
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rbf mach=m32r FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu.h m32r/sem.c m32r/sem-switch.c m32r/model.c m32r/decode.c m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu.h $(srcdir)/m32r/sem.c $(srcdir)/m32r/sem-switch.c $(srcdir)/m32r/model.c $(srcdir)/m32r/decode.c $(srcdir)/m32r/decode.h: @CGEN_MAINT@ m32r/cgen-cpu-decode
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-x:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32rxf mach=m32rx SUFFIX=x FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpux.h m32r/semx-switch.c m32r/modelx.c m32r/decodex.c m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpux.h $(srcdir)/m32r/semx-switch.c $(srcdir)/m32r/modelx.c $(srcdir)/m32r/decodex.c $(srcdir)/m32r/decodex.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-x
@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cgen-cpu-decode-2:
@SIM_ENABLE_ARCH_m32r_TRUE@ $(AM_V_GEN)cpu=m32r2f mach=m32r2 SUFFIX=2 FLAGS="with-scache with-profile=fn" EXTRAFILES="$(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_m32r_TRUE@m32r/cpu2.h m32r/sem2-switch.c m32r/model2.c m32r/decode2.c m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
+@SIM_ENABLE_ARCH_m32r_TRUE@$(srcdir)/m32r/cpu2.h $(srcdir)/m32r/sem2-switch.c $(srcdir)/m32r/model2.c $(srcdir)/m32r/decode2.c $(srcdir)/m32r/decode2.h: @CGEN_MAINT@ m32r/cgen-cpu-decode-2
@SIM_ENABLE_ARCH_m68hc11_TRUE@$(m68hc11_libsim_a_OBJECTS) $(m68hc11_libsim_a_LIBADD): m68hc11/hw-config.h
@SIM_ENABLE_ARCH_m68hc11_TRUE@m68hc11/modules.o: m68hc11/modules.c
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/modules.c: | $(or1k_BUILD_OUTPUTS)
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/mloop.c or1k/eng.h: or1k/stamp-mloop ; @true
-@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: $(srccom)/genmloop.sh or1k/mloop.in
-@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)$(SHELL) $(srccom)/genmloop.sh -shell $(SHELL) \
+@SIM_ENABLE_ARCH_or1k_TRUE@or1k/stamp-mloop: or1k/mloop.in $(srccom)/genmloop.sh
+@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)$(CGEN_GEN_MLOOP) \
@SIM_ENABLE_ARCH_or1k_TRUE@ -mono -fast -pbb -switch sem-switch.c \
-@SIM_ENABLE_ARCH_or1k_TRUE@ -cpu or1k32bf \
-@SIM_ENABLE_ARCH_or1k_TRUE@ -infile $(srcdir)/or1k/mloop.in -outfile-prefix or1k/
+@SIM_ENABLE_ARCH_or1k_TRUE@ -cpu or1k32bf
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/eng.hin or1k/eng.h
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change or1k/mloop.cin or1k/mloop.c
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-arch:
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)mach=or32,or32nd FLAGS="with-scache"; $(CGEN_GEN_ARCH)
-@SIM_ENABLE_ARCH_or1k_TRUE@or1k/arch.h or1k/arch.c or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch
+@SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/arch.h $(srcdir)/or1k/arch.c $(srcdir)/or1k/cpuall.h: @CGEN_MAINT@ or1k/cgen-arch
@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cgen-cpu-decode:
@SIM_ENABLE_ARCH_or1k_TRUE@ $(AM_V_GEN)cpu=or1k32bf mach=or32,or32nd FLAGS="with-scache" EXTRAFILES="$(CGEN_CPU_SEM) $(CGEN_CPU_SEMSW)"; $(CGEN_GEN_CPU_DECODE)
-@SIM_ENABLE_ARCH_or1k_TRUE@or1k/cpu.h or1k/cpu.c or1k/model.c or1k/sem.c or1k/sem-switch.c or1k/decode.c or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc/libsim.a: common/libcommon.a
-@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_or1k_TRUE@$(srcdir)/or1k/cpu.h $(srcdir)/or1k/cpu.c $(srcdir)/or1k/model.c $(srcdir)/or1k/sem.c $(srcdir)/or1k/sem-switch.c $(srcdir)/or1k/decode.c $(srcdir)/or1k/decode.h: @CGEN_MAINT@ or1k/cgen-cpu-decode
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: common/%.c ; $(SIM_COMPILE)
+@SIM_ENABLE_ARCH_ppc_TRUE@-@am__include@ ppc/$(DEPDIR)/*.Po
-@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%.o: ppc/%.c | ppc/libsim.a $(SIM_ALL_RECURSIVE_DEPS)
-@SIM_ENABLE_ARCH_ppc_TRUE@ $(MAKE) $(AM_MAKEFLAGS) -C $(@D) $(@F)
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/defines.h: ppc/stamp-defines ; @true
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-defines: config.h Makefile
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(SED) -n -e '/^#define HAVE_.*1$$/{ s/ 1$$/",/; s/.* HAVE_/"HAVE_/; p }' < config.h > ppc/defines.hin
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/defines.hin ppc/defines.h
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_ppc_TRUE@ppc/spreg.c: @MAINT@ ppc/ppc-spr-table ppc/spreg-gen.py ppc/$(am__dirstamp)
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --source $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(srcdir)/ppc/spreg-gen.py --header $@.tmp
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change $@.tmp $(srcdir)/ppc/spreg.h
@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $(srcdir)/ppc/spreg.h
+
+@SIM_ENABLE_ARCH_ppc_TRUE@$(ppc_BUILT_SRC_FROM_IGEN): ppc/stamp-igen
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-igen: ppc/powerpc.igen ppc/altivec.igen ppc/e500.igen $(ppc_IGEN_OPCODE_RULES) $(PPC_IGEN)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)$(PPC_IGEN_RUN) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -o $(srcdir)/$(ppc_IGEN_OPCODE_RULES) \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -I $(srcdir)/ppc -i $(srcdir)/ppc/powerpc.igen \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n icache.h -hc ppc/icache.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n icache.c -c ppc/icache.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n semantics.h -hs ppc/semantics.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n semantics.c -s ppc/semantics.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n idecode.h -hd ppc/idecode.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n idecode.c -d ppc/idecode.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n itable.h -ht ppc/itable.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n itable.c -t ppc/itable.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n model.h -hm ppc/model.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n model.c -m ppc/model.c \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n support.h -hf ppc/support.h \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -n support.c -f ppc/support.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/libigen.a: $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_DEPENDENCIES) $(EXTRA_ppc_libigen_a_DEPENDENCIES) ppc/$(am__dirstamp)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)-rm -f $@
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_AR)$(AR_FOR_BUILD) $(ARFLAGS) $@ $(ppc_libigen_a_OBJECTS) $(ppc_libigen_a_LIBADD)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(RANLIB_FOR_BUILD) $@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/igen$(EXEEXT): $(ppc_igen_OBJECTS) $(ppc_igen_DEPENDENCIES) ppc/$(am__dirstamp)
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CCLD)$(LINK_FOR_BUILD) $(ppc_igen_OBJECTS) $(ppc_igen_LDADD)
+
+@SIM_ENABLE_ARCH_ppc_TRUE@$(ppc_libigen_a_OBJECTS) $(ppc_igen_OBJECTS): ppc/%.o: ppc/%.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -I$(srcdir)/igen -I$(srcdir)/ppc -c $< -o $@
+
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/%-main.o: ppc/%.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_CC)$(COMPILE_FOR_BUILD) -DMAIN -c $< -o $@
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/hw.c ppc/hw.h: ppc/stamp-hw ; @true
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-hw: Makefile $(ppc_HW_SRC) $(srcroot)/move-if-change
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)\
+@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_HW_SRC) ; do \
+@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for hw in $$f ; do echo $$hw ; done \
+@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*\(hw_.*\)\.c/\1/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/extern const device_descriptor /' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_device_descriptor\[\];/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ > ppc/hw.hin; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_HW_SRC) ; do \
+@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for hw in $$f ; do echo $$hw ; done \
+@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*\(hw_.*\)\.c/\1/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/ /' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_device_descriptor,/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ > ppc/hw.cin
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/hw.hin ppc/hw.h
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/hw.cin ppc/hw.c
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/hw.c ppc/hw.h: ppc/stamp-igen
+@SIM_ENABLE_ARCH_ppc_TRUE@$(srcdir)/ppc/pk.h: @MAINT@ ppc/stamp-pk ; @true
+@SIM_ENABLE_ARCH_ppc_TRUE@ppc/stamp-pk: $(srcdir)/ppc/Makefile.in $(ppc_PACKAGE_SRC) $(srcroot)/move-if-change
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_GEN)echo "/* Generated file by local.mk; do not edit. */" > ppc/pk.hin; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ f=""; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for i in $(ppc_PACKAGE_SRC) ; do \
+@SIM_ENABLE_ARCH_ppc_TRUE@ case " $$f " in \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *" $$i "*) ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ *) f="$$f $$i" ;; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ esac ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ done ; \
+@SIM_ENABLE_ARCH_ppc_TRUE@ for pk in $$f ; do echo $$pk ; done \
+@SIM_ENABLE_ARCH_ppc_TRUE@ | sed -e 's/^.*pk_\(.*\)\.c/\1/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/^/extern package_create_instance_callback pk_/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ -e 's/$$/_create_instance;/' \
+@SIM_ENABLE_ARCH_ppc_TRUE@ >> ppc/pk.hin
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)$(SHELL) $(srcroot)/move-if-change ppc/pk.hin $(srcdir)/ppc/pk.h
+@SIM_ENABLE_ARCH_ppc_TRUE@ $(AM_V_at)touch $@
@SIM_ENABLE_ARCH_pru_TRUE@$(pru_libsim_a_OBJECTS) $(pru_libsim_a_LIBADD): pru/hw-config.h
@SIM_ENABLE_ARCH_pru_TRUE@pru/modules.o: pru/modules.c
@SIM_ENABLE_ARCH_v850_TRUE@ -n irun.c -r v850/irun.c
@SIM_ENABLE_ARCH_v850_TRUE@ $(AM_V_at)touch $@
-all-recursive: $(SIM_ALL_RECURSIVE_DEPS)
-
install-data-local: installdirs $(SIM_INSTALL_DATA_LOCAL_DEPS)
$(AM_V_at)$(MKDIR_P) $(DESTDIR)$(libdir)
lib=`echo sim | sed '$(program_transform_name)'`; \