#include <ctype.h>
#include <limits.h>
#include "ansidecl.h"
-#include "callback.h"
+#include "gdb/callback.h"
#include "opcode/d10v.h"
#include "bfd.h"
#define DEBUG_MEMSIZE 0x00000008
#define DEBUG_INSTRUCTION 0x00000010
#define DEBUG_TRAP 0x00000020
+#define DEBUG_MEMORY 0x00000040
#ifndef DEBUG
#define DEBUG (DEBUG_TRACE | DEBUG_VALUES | DEBUG_LINE_NUMBER)
extern int d10v_debug;
-#include "remote-sim.h"
+#include "gdb/remote-sim.h"
#include "sim-config.h"
#include "sim-types.h"
int cycles;
int unit;
int exec_type;
- void (*func)();
+ void (*func)(SIM_DESC, SIM_CPU *);
int numops;
int operands[9];
};
} \
while (0)
+/* d10v memory: There are three separate d10v memory regions IMEM,
+ UMEM and DMEM. The IMEM and DMEM are further broken down into
+ blocks (very like VM pages). */
+
+enum
+{
+ IMAP_BLOCK_SIZE = 0x20000,
+ DMAP_BLOCK_SIZE = 0x4000,
+};
+
+/* Implement the three memory regions using sparse arrays. Allocate
+ memory using ``segments''. A segment must be at least as large as
+ a BLOCK - ensures that an access that doesn't cross a block
+ boundary can't cross a segment boundary */
+
+enum
+{
+ SEGMENT_SIZE = 0x20000, /* 128KB - MAX(IMAP_BLOCK_SIZE,DMAP_BLOCK_SIZE) */
+ IMEM_SEGMENTS = 8, /* 1MB */
+ DMEM_SEGMENTS = 8, /* 1MB */
+ UMEM_SEGMENTS = 128 /* 16MB */
+};
+
+struct d10v_memory
+{
+ uint8 *insn[IMEM_SEGMENTS];
+ uint8 *data[DMEM_SEGMENTS];
+ uint8 *unif[UMEM_SEGMENTS];
+};
+
struct _state
{
reg_t regs[16]; /* general-purpose registers */
reg_t cregs[16]; /* control registers */
#define CREG(N) (State.cregs[(N)] + 0)
-#define SET_CREG(N,VAL) move_to_cr ((N), 0, (VAL))
+#define SET_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 0)
+#define SET_HW_CREG(N,VAL) move_to_cr (sd, cpu, (N), 0, (VAL), 1)
reg_t sp[2]; /* holding area for SPI(0)/SPU(1) */
#define HELD_SP(N) (State.sp[(N)] + 0)
} trace;
uint8 exe;
- int exception;
int pc_changed;
- /* NOTE: everything below this line is not reset by sim_create_inferior() */
- uint8 *imem;
- uint8 *dmem;
- uint8 *umem[128];
+ /* NOTE: everything below this line is not reset by
+ sim_create_inferior() */
+
+ struct d10v_memory mem;
+
enum _ins_type ins_type;
-} State;
+};
+
+extern struct _state State;
-extern host_callback *d10v_callback;
extern uint16 OP[4];
extern struct simops Simops[];
-extern asection *text;
-extern bfd_vma text_start;
-extern bfd_vma text_end;
-extern bfd *prog_bfd;
enum
{
#define PSW CREG (PSW_CR)
#define SET_PSW(VAL) SET_CREG (PSW_CR, (VAL))
-#define SET_PSW_BIT(MASK,VAL) move_to_cr (PSW_CR, ~(MASK), (VAL) ? (MASK) : 0)
+#define SET_HW_PSW(VAL) SET_HW_CREG (PSW_CR, (VAL))
+#define SET_PSW_BIT(MASK,VAL) move_to_cr (sd, cpu, PSW_CR, ~((reg_t) MASK), (VAL) ? (MASK) : 0, 1)
#define PSW_SM ((PSW & PSW_SM_BIT) != 0)
#define SET_PSW_SM(VAL) SET_PSW_BIT (PSW_SM_BIT, (VAL))
#define SIG_D10V_STOP -1
#define SIG_D10V_EXIT -2
+#define SIG_D10V_BUS -3
+
+/* TODO: Resolve conflicts with common headers. */
+#undef SEXT8
+#undef SEXT16
+#undef SEXT32
+#undef MASK32
#define SEXT3(x) ((((x)&0x7)^(~3))+4)
#define INC_ADDR(x,i) \
do \
{ \
- if (PSW_MD && GPR (x) == (MOD_E & ~((i) - 1))) \
- SET_GPR (x, MOD_S); \
+ int test_i = i < 0 ? i : ~((i) - 1); \
+ if (PSW_MD && GPR (x) == (MOD_E & test_i)) \
+ SET_GPR (x, MOD_S & test_i); \
else \
SET_GPR (x, GPR (x) + (i)); \
} \
while (0)
-extern uint8 *dmem_addr PARAMS ((uint32));
-extern uint8 *imem_addr PARAMS ((uint32));
-extern bfd_vma decode_pc PARAMS ((void));
+extern uint8 *dmem_addr (SIM_DESC, SIM_CPU *, uint16 offset);
+extern uint8 *imem_addr (SIM_DESC, SIM_CPU *, uint32);
+extern bfd_vma decode_pc (void);
-#define RB(x) (*(dmem_addr(x)))
+#define RB(x) (*(dmem_addr (sd, cpu, x)))
#define SB(addr,data) ( RB(addr) = (data & 0xff))
#if defined(__GNUC__) && defined(__OPTIMIZE__) && !defined(NO_ENDIAN_INLINE)
#undef ENDIAN_INLINE
#else
-extern uint32 get_longword PARAMS ((uint8 *));
-extern uint16 get_word PARAMS ((uint8 *));
-extern int64 get_longlong PARAMS ((uint8 *));
-extern void write_word PARAMS ((uint8 *addr, uint16 data));
-extern void write_longword PARAMS ((uint8 *addr, uint32 data));
-extern void write_longlong PARAMS ((uint8 *addr, int64 data));
+extern uint32 get_longword (uint8 *);
+extern uint16 get_word (uint8 *);
+extern int64 get_longlong (uint8 *);
+extern void write_word (uint8 *addr, uint16 data);
+extern void write_longword (uint8 *addr, uint32 data);
+extern void write_longlong (uint8 *addr, int64 data);
#endif
-#define SW(addr,data) write_word(dmem_addr(addr),data)
-#define RW(x) get_word(dmem_addr(x))
-#define SLW(addr,data) write_longword(dmem_addr(addr),data)
-#define RLW(x) get_longword(dmem_addr(x))
+#define SW(addr,data) write_word (dmem_addr (sd, cpu, addr), data)
+#define RW(x) get_word (dmem_addr (sd, cpu, x))
+#define SLW(addr,data) write_longword (dmem_addr (sd, cpu, addr), data)
+#define RLW(x) get_longword (dmem_addr (sd, cpu, x))
#define READ_16(x) get_word(x)
#define WRITE_16(addr,data) write_word(addr,data)
#define READ_64(x) get_longlong(x)
#define WRITE_64(addr,data) write_longlong(addr,data)
-#define IMAP0 RW(0xff00)
-#define IMAP1 RW(0xff02)
-#define DMAP RW(0xff04)
-#define SET_IMAP0(x) SW(0xff00,x)
-#define SET_IMAP1(x) SW(0xff02,x)
-#define SET_DMAP(x) SW(0xff04,x)
-
#define JMP(x) do { SET_PC (x); State.pc_changed = 1; } while (0)
#define RIE_VECTOR_START 0xffc2
#define DBT_VECTOR_START 0xffd4
#define SDBT_VECTOR_START 0xffd5
-extern reg_t move_to_cr PARAMS ((int cr, reg_t mask, reg_t val));
+/* Scedule a store of VAL into cr[CR]. MASK indicates the bits in
+ cr[CR] that should not be modified (i.e. cr[CR] = (cr[CR] & MASK) |
+ (VAL & ~MASK)). In addition, unless PSW_HW_P, a VAL intended for
+ PSW is masked for zero bits. */
+
+extern reg_t move_to_cr (SIM_DESC, SIM_CPU *, int cr, reg_t mask, reg_t val, int psw_hw_p);
projects / thirdparty / binutils-gdb.git / blobdiff