+Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-05-08 Felix Lee <flee@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-03-03 DJ Delorie <dj@cygnus.com>
+
+ * configure.in: add termcap and -luser32 for host=cygwin
+ * configure: regenerate
+
+1999-02-11 Hugo Tyson <hmt@cygnus.co.uk>
+
+ * exec.c (dispatch_instruction):
+ Correct the sense of the
+ if (!sparclite) {
+ sregs->trap = TRAP_UNIMP;
+ break;
+ }
+ clause that has been pasted around: it's correct in the SCAN and
+ DIVScc (divide step) cases (where it was probably originally
+ written?), but reversed in the SDIV, SDIVcc, UDIV, UDIVcc cases
+ ie. instructions only in the SPARC V8 or SPARClite 86x
+ architectures. It was also present when not required for SMUL,
+ SMULcc, UMUL, UMULcc instructions that are present in all
+ architectures.
+
+1999-01-25 Hugo Tyson <hmt@cygnus.co.uk>
+
+ * interf.c (run_sim): Fix a bug in the main loop's handling of
+ annulled delay slot instructions. There is precedent for this
+ change; the _other_ main loop in sis.c gets it right according to
+ my reading of the code.
+
+ The bug is: if an interrupt happens when the next instruction
+ (at sregs->pc) is annulled, the trap is taken (by execute_trap())
+ with the current values of PC and NPC, so when the trap returns,
+ the annulled instruction is indeed executed. Another giveaway is
+ that the annul flag is cleared in execute_trap(): the information
+ is demonstrably discarded.
+
+ The solution is: perform annulling before looking for traps, in
+ fact it's neater to do annulling, see if there's an interrupt and
+ if not, do the instruction, then handle traps be they generated by
+ interrupts pending or by the instruction we might just have done.
+ That's what the sis.c one does.
+
+1999-01-20 Hugo Tyson <hmt@cygnus.co.uk>
+
+ * sis.h: Add asr17 register for support of SparcLITE (at least the
+ Hitachi ones I find before me)
+
+ * exec.c (dispatch_instruction): Case WRY: Allow write of asr17 if
+ sparclite. Other ASR numbers than 17 or 0 (Y) trap out.
+ Case RDY: Allow read of asr17 if sparclite. Other ASRs ditto.
+ (execute_trap): Do single-vector-trapping if asr17 bit 0 is set.
+ (init_regs): Initialize y and asr17.
+ NB: In instruction-set space, the Y register is asr0; the
+ instructions have different names for human reasons only.
+
+ * sis.c:
+ * interf.c: Set boolean mode variable dumbio if invoked with
+ argument "-dumbio" and mention it of verbose.
+ * erc32.c: if "dumbio" is set, do not assume that there is a
+ terminal type device attached to stdin/stdout. Do not set
+ buffering or mess with tcsetattr or do any read operations in
+ order to make UART interrupts; not input data is supported.
+ This is necessary to allow the sim to be used within the eCos
+ testing infrastructure where stdin/stdout are pipes to a TCL
+ program; the sim hangs otherwise.
+
+Thu Jul 23 07:17:03 1998 Mark Alexander <marka@cygnus.com>
+
+ * exec.c (dispatch_instruction): Add SPARClite 'scan' instruction.
+
+Tue Jul 7 21:12:41 1998 Mark Alexander <marka@cygnus.com>
+
+ * func.c (bfd_load): Add special handling of a.out executables.
+
+Sat Jun 13 08:33:25 1998 Mark Alexander <marka@cygnus.com>
+
+ * func.c (bfd_load): Print correct endianness.
+ * interf.c (run_sim): Print debugging information if verbosity level
+ is greater than 2.
+ (sim_open): Repeated -v options now increment verbosity level.
+ (sim_store_register): Handle little-endian case.
+ (flush_window): Print debugging information if verbosity level
+ is greater then 2.
+
Tue Jun 2 15:20:35 1998 Mark Alexander <marka@cygnus.com>
* interf.c (sim_open): Use revamped memory_read, which makes
projects / thirdparty / binutils-gdb.git / blobdiff