#define TARGET_BIG_ENDIAN 1
-/* Cover fns for register access. */
-USI a_fr30_h_pc_get (SIM_CPU *);
-void a_fr30_h_pc_set (SIM_CPU *, USI);
-SI a_fr30_h_gr_get (SIM_CPU *, UINT);
-void a_fr30_h_gr_set (SIM_CPU *, UINT, SI);
-SI a_fr30_h_cr_get (SIM_CPU *, UINT);
-void a_fr30_h_cr_set (SIM_CPU *, UINT, SI);
-SI a_fr30_h_dr_get (SIM_CPU *, UINT);
-void a_fr30_h_dr_set (SIM_CPU *, UINT, SI);
-USI a_fr30_h_ps_get (SIM_CPU *);
-void a_fr30_h_ps_set (SIM_CPU *, USI);
-SI a_fr30_h_r13_get (SIM_CPU *);
-void a_fr30_h_r13_set (SIM_CPU *, SI);
-SI a_fr30_h_r14_get (SIM_CPU *);
-void a_fr30_h_r14_set (SIM_CPU *, SI);
-SI a_fr30_h_r15_get (SIM_CPU *);
-void a_fr30_h_r15_set (SIM_CPU *, SI);
-BI a_fr30_h_nbit_get (SIM_CPU *);
-void a_fr30_h_nbit_set (SIM_CPU *, BI);
-BI a_fr30_h_zbit_get (SIM_CPU *);
-void a_fr30_h_zbit_set (SIM_CPU *, BI);
-BI a_fr30_h_vbit_get (SIM_CPU *);
-void a_fr30_h_vbit_set (SIM_CPU *, BI);
-BI a_fr30_h_cbit_get (SIM_CPU *);
-void a_fr30_h_cbit_set (SIM_CPU *, BI);
-BI a_fr30_h_ibit_get (SIM_CPU *);
-void a_fr30_h_ibit_set (SIM_CPU *, BI);
-BI a_fr30_h_sbit_get (SIM_CPU *);
-void a_fr30_h_sbit_set (SIM_CPU *, BI);
-BI a_fr30_h_tbit_get (SIM_CPU *);
-void a_fr30_h_tbit_set (SIM_CPU *, BI);
-BI a_fr30_h_d0bit_get (SIM_CPU *);
-void a_fr30_h_d0bit_set (SIM_CPU *, BI);
-BI a_fr30_h_d1bit_get (SIM_CPU *);
-void a_fr30_h_d1bit_set (SIM_CPU *, BI);
-UQI a_fr30_h_ccr_get (SIM_CPU *);
-void a_fr30_h_ccr_set (SIM_CPU *, UQI);
-UQI a_fr30_h_scr_get (SIM_CPU *);
-void a_fr30_h_scr_set (SIM_CPU *, UQI);
-UQI a_fr30_h_ilm_get (SIM_CPU *);
-void a_fr30_h_ilm_set (SIM_CPU *, UQI);
-
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_FR30_1, MODEL_MAX