#define TARGET_BIG_ENDIAN 1
-/* Cover fns for register access. */
-USI a_m32r_h_pc_get (SIM_CPU *);
-void a_m32r_h_pc_set (SIM_CPU *, USI);
-SI a_m32r_h_gr_get (SIM_CPU *, UINT);
-void a_m32r_h_gr_set (SIM_CPU *, UINT, SI);
-USI a_m32r_h_cr_get (SIM_CPU *, UINT);
-void a_m32r_h_cr_set (SIM_CPU *, UINT, USI);
-DI a_m32r_h_accum_get (SIM_CPU *);
-void a_m32r_h_accum_set (SIM_CPU *, DI);
-DI a_m32r_h_accums_get (SIM_CPU *, UINT);
-void a_m32r_h_accums_set (SIM_CPU *, UINT, DI);
-BI a_m32r_h_cond_get (SIM_CPU *);
-void a_m32r_h_cond_set (SIM_CPU *, BI);
-UQI a_m32r_h_psw_get (SIM_CPU *);
-void a_m32r_h_psw_set (SIM_CPU *, UQI);
-UQI a_m32r_h_bpsw_get (SIM_CPU *);
-void a_m32r_h_bpsw_set (SIM_CPU *, UQI);
-UQI a_m32r_h_bbpsw_get (SIM_CPU *);
-void a_m32r_h_bbpsw_set (SIM_CPU *, UQI);
-BI a_m32r_h_lock_get (SIM_CPU *);
-void a_m32r_h_lock_set (SIM_CPU *, BI);
-
/* Enum declaration for model types. */
typedef enum model_type {
MODEL_M32R_D, MODEL_TEST