* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that

[thirdparty/binutils-gdb.git] / sim / m32r / mloopx.in

diff --git a/sim/m32r/mloopx.in b/sim/m32r/mloopx.in
index fca05cdc380f361a81ce5729a7bca7d32fada22d..6b084f4bfb1dcc7fc0be309892b5b6f9bcf3665e 100644 (file)
--- a/sim/m32r/mloopx.in
+++ b/sim/m32r/mloopx.in
@@ -36,7 +36,7 @@ EOF
 xinit)
 
 cat <<EOF
-  DECODE *d1,*d2;
+  const IDESC *d1,*d2;
   ARGBUF abufs[MAX_PARALLEL_INSNS];
   PAREXEC pbufs[MAX_PARALLEL_INSNS];
 EOF
@@ -57,6 +57,8 @@ cat <<EOF
       insn &= 0x7fff;
       d1 = m32rx_decode (current_cpu, pc, insn);
       abufs[0].insn = insn;
+      abufs[0].idesc = d1;
+      abufs[0].addr = pc; /* FIXME: wip */
       icount = 1;
     }
   else
@@ -66,6 +68,8 @@ cat <<EOF
        {
          d1 = m32rx_decode (current_cpu, pc, insn >> 16);
          abufs[0].insn = insn;
+         abufs[0].idesc = d1;
+         abufs[0].addr = pc; /* FIXME: wip */
          icount = 1;
        }
       else
@@ -74,14 +78,20 @@ cat <<EOF
            {
              d1 = m32rx_decode (current_cpu, pc, insn >> 16);
              abufs[0].insn = insn >> 16;
-             d2 = m32rx_decode (current_cpu, pc, insn & 0x7fff);
+             abufs[0].idesc = d1;
+             abufs[0].addr = pc; /* FIXME: wip */
+             d2 = m32rx_decode (current_cpu, pc + 2, insn & 0x7fff);
              abufs[1].insn = insn & 0x7fff;
+             abufs[1].idesc = d2;
+             abufs[1].addr = pc + 2; /* FIXME: wip */
              icount = 2;
            }
          else
            {
              d1 = m32rx_decode (current_cpu, pc, insn >> 16);
              abufs[0].insn = insn >> 16;
+             abufs[0].idesc = d1;
+             abufs[0].addr = pc; /* FIXME: wip */
              icount = 1;
            }
        }
@@ -90,7 +100,7 @@ cat <<EOF
   {
     int icount2 = icount;
     USI insn = abufs[0].insn;
-    DECODE *decode = d1;
+    const IDESC *decode = d1;
     /* decode, par_exec, and insn are refered to by readx.c.  */
     PAREXEC *par_exec = &pbufs[0];
     do
@@ -117,17 +127,20 @@ cat <<EOF
   PAREXEC *par_exec = &pbufs[0];
   PCADDR new_pc;
 
+#if 0 /* wip */
   /* If doing parallel execution, verify insns are in the right pipeline.  */
   if (icount == 2)
     {
-      ; /*wip*/
+      ...
     }
+#endif
 
-  TRACE_INSN_INIT (current_cpu);
+  m32r_model_init_insn_cycles (current_cpu, 1);
+  TRACE_INSN_INIT (current_cpu, 1);
   TRACE_INSN (current_cpu, d1->opcode, sem_arg, CPU (h_pc));
-  new_pc = (*d1->semantic) (current_cpu, sem_arg, par_exec);
-  TRACE_INSN_FINI (current_cpu);
-  PROFILE_COUNT_INSN (current_cpu, CPU (h_pc), CGEN_INSN_INDEX (d1->opcode));
+  new_pc = (*d1->sem_full) (current_cpu, sem_arg, par_exec);
+  m32r_model_update_insn_cycles (current_cpu, icount == 1);
+  TRACE_INSN_FINI (current_cpu, icount == 1);
 
   /* The result of the semantic fn is one of:
      - next address, branch only
@@ -136,39 +149,49 @@ cat <<EOF
      - NEW_PC_4, 4 byte non-branch insn
      */
 
+  /* The tests are ordered to try to favor the more frequent cases, while
+     keeping the over all costs down.  */
   if (new_pc == NEW_PC_4)
     CPU (h_pc) += 4;
-  else if (NEW_PC_BRANCH_P (new_pc))
-    CPU (h_pc) = new_pc;
-  else
+  else if (icount == 2)
     {
-      PCADDR pc = CPU (h_pc);
+      /* Note that we only get here if doing parallel execution.  */
 
-      CPU (h_pc) = pc + 2;
-      if (icount == 2)
+      if (new_pc == NEW_PC_SKIP)
        {
-         /* Note that we only get here if doing parallel execution.  */
-         if (new_pc == NEW_PC_SKIP)
-           {
-             /* ??? Need generic notion of bypassing an insn for the name of
-                this macro.  Annulled?  On the otherhand such tracing can go
-                in the sc/snc semantic fn.  */
-             ; /*TRACE_INSN_SKIPPED (current_cpu);*/
-           }
+         /* ??? Need generic notion of bypassing an insn for the name of
+            this macro.  Annulled?  On the otherhand such tracing can go
+            in the sc/snc semantic fn.  */
+         ; /*TRACE_INSN_SKIPPED (current_cpu);*/
+         CPU (h_pc) += 4;
+       }
+      else
+        {
+         PCADDR pc2;
+
+         ++sem_arg;
+         ++par_exec;
+         m32r_model_init_insn_cycles (current_cpu, 0);
+         TRACE_INSN_INIT (current_cpu, 0);
+         TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc) + 2);
+         /* pc2 isn't used.  It's assigned a value for debugging.  */
+         pc2 = (*d2->sem_full) (current_cpu, sem_arg, par_exec);
+         m32r_model_update_insn_cycles (current_cpu, 1);
+         TRACE_INSN_FINI (current_cpu, 1);
+
+         if (NEW_PC_BRANCH_P (new_pc))
+           CPU (h_pc) = new_pc;
          else
-           {
-             ++sem_arg;
-             ++par_exec;
-             TRACE_INSN_INIT (current_cpu);
-             TRACE_INSN (current_cpu, d2->opcode, sem_arg, CPU (h_pc));
-             /* new_pc isn't used.  It's assigned a value for debugging.  */
-             new_pc = (*d2->semantic) (current_cpu, sem_arg, par_exec);
-             TRACE_INSN_FINI (current_cpu);
-             PROFILE_COUNT_INSN (current_cpu, pc, CGEN_INSN_INDEX (d2->opcode));
-           }
-         CPU (h_pc) = pc + 4;
+           CPU (h_pc) += 4;
        }
+
+      /* Update count of parallel insns executed.  */
+      PROFILE_COUNT_PARINSNS (current_cpu);
     }
+  else if (NEW_PC_BRANCH_P (new_pc))
+    CPU (h_pc) = new_pc;
+  else
+    CPU (h_pc) += 2;
 }
 EOF