+Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-profile.o module.
+
+ * sim-main.h (WITH_PROFILE): Do not define, defined in
+ common/sim-config.h. Use sim-profile module.
+ (simPROFILE): Delete defintion.
+
+ * interp.c (PROFILE): Delete definition.
+ (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
+ (sim_close): Delete code writing profile histogram.
+ (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
+ Delete.
+ (sim_engine_run): Delete code profiling the PC.
+
+Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
+
+ * interp.c (sim_monitor): Make register pointers of type
+ unsigned_word*.
+
+ * sim-main.h: Make registers of type unsigned_word not
+ signed_word.
+
+Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+start-sanitize-r5900
+ * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
+ ...): Move to sim-main.h
+
+end-sanitize-r5900
+ * interp.c (sync_operation): Rename from SyncOperation, make
+ global, add SD argument.
+ (prefetch): Rename from Prefetch, make global, add SD argument.
+ (decode_coproc): Make global.
+
+ * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
+
+ * gencode.c (build_instruction): Generate DecodeCoproc not
+ decode_coproc calls.
+
+ * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
+ (SizeFGR): Move to sim-main.h
+ (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
+ simSIGINT, simJALDELAYSLOT): Move to sim-main.h
+ (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
+ sim-main.h.
+ (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
+ FP_RM_TOMINF, GETRM): Move to sim-main.h.
+ (Uncached, CachedNoncoherent, CachedCoherent, Cached,
+ isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
+ (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
+ BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
+
+ * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
+ exception.
+ (sim-alu.h): Include.
+ (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
+ (sim_cia): Typedef to instruction_address.
+
+Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (interp.o): Rename generated file engine.c to
+ oengine.c.
+
+ * interp.c: Update.
+
+Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
+
+Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For "FPSQRT", output correct
+ number of arguments to Recip.
+
+Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (interp.o): Depends on sim-main.h
+
+ * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
+
+ * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
+ ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
+ (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
+ STATE, DSSTATE): Define
+ (GPR, FGRIDX, ..): Define.
+
+ * interp.c (registers, register_widths, fpr_state, ipc, dspc,
+ pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
+ (GPR, FGRIDX, ...): Delete macros.
+
+ * interp.c: Update names to match defines from sim-main.h
+
+Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_monitor): Add SD argument.
+ (sim_warning): Delete. Replace calls with calls to
+ sim_io_eprintf.
+ (sim_error): Delete. Replace calls with sim_io_error.
+ (open_trace, writeout32, writeout16, getnum): Add SD argument.
+ (mips_set_profile): Rename from sim_set_profile. Add SD argument.
+ (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
+ argument.
+ (mips_size): Rename from sim_size. Add SD argument.
+
+ * interp.c (simulator): Delete global variable.
+ (callback): Delete global variable.
+ (mips_option_handler, sim_open, sim_write, sim_read,
+ sim_store_register, sim_fetch_register, sim_info, sim_do_command,
+ sim_size,sim_monitor): Use sim_io_* not callback->*.
+ (sim_open): ZALLOC simulator struct.
+ (PROFILE): Do not define.
+
+Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
+ support.h with corresponding code.
+
+ * sim-main.h (word64, uword64), support.h: Move definition to
+ sim-main.h.
+ (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
+
+ * support.h: Delete
+ * Makefile.in: Update dependencies
+ * interp.c: Do not include.
+
+Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (address_translation, load_memory, store_memory,
+ cache_op): Rename to from AddressTranslation et.al., make global,
+ add SD argument
+
+ * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
+ CacheOp): Define.
+
+ * interp.c (SignalException): Rename to signal_exception, make
+ global.
+
+ * interp.c (Interrupt, ...): Move definitions to sim-main.h.
+
+ * sim-main.h (SignalException, SignalExceptionInterrupt,
+ SignalExceptionInstructionFetch, SignalExceptionAddressStore,
+ SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
+ SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
+ Define.
+
+ * interp.c, support.h: Use.
+
+Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
+ to value_fpr / store_fpr. Add SD argument.
+ (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
+ Multiply, Divide, Recip, SquareRoot, Convert): Make global.
+
+ * sim-main.h (ValueFPR, StoreFPR): Define.
+
+Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_engine_run): Check consistency between configure
+ WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
+ and HASFPU.
+
+ * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
+ (mips_fpu): Configure WITH_FLOATING_POINT.
+ (mips_endian): Configure WITH_TARGET_ENDIAN.
+ * configure: Update.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+start-sanitize-r5900
+Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (MAX_REG): Allow up-to 128 registers.
+ (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
+ (REGISTER_SA): Ditto.
+ (sim_open): Initialize register_widths for r5900 specific
+ registers.
+ (sim_fetch_register, sim_store_register): Check for request of
+ r5900 specific SA register. Check for request for hi 64 bits of
+ r5900 specific registers.
+
+end-sanitize-r5900
+Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
+
+ * configure: Regenerated.
+
+Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
+
+ * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
+
+Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (print_igen_insn_models): Assume certain architectures
+ include all mips* instructions.
+ (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
+ instruction.
+
+ * Makefile.in (tmp.igen): Add target. Generate igen input from
+ gencode file.
+
+ * gencode.c (FEATURE_IGEN): Define.
+ (main): Add --igen option. Generate output in igen format.
+ (process_instructions): Format output according to igen option.
+ (print_igen_insn_format): New function.
+ (print_igen_insn_models): New function.
+ (process_instructions): Only issue warnings and ignore
+ instructions when no FEATURE_IGEN.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
+ MIPS targets.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
+ SIM_RESERVED_BITS): Delete, moved to common.
+ (SIM_EXTRA_CFLAGS): Update.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in: Configure non-strict memory alignment.
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (SDBBP,DERET): Added (3900) insns.
+ (RFE): Turn on for 3900.
+ * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
+ (dsstate): Made global.
+ (SUBTARGET_R3900): Added.
+ (CANCELDELAYSLOT): New.
+ (SignalException): Ignore SystemCall rather than ignore and
+ terminate. Add DebugBreakPoint handling.
+ (decode_coproc): New insns RFE, DERET; and new registers Debug
+ and DEPC protected by SUBTARGET_R3900.
+ (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
+ bits explicitly.
+ * Makefile.in,configure.in: Add mips subtarget option.
+ * configure: Update.
+
+Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c: Add r3900 (tx39).
+
+start-sanitize-tx19
+ * gencode.c: Fix some configuration problems by improving
+ the relationship between tx19 and tx39.
+end-sanitize-tx19
+
+Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (build_instruction): Don't need to subtract 4 for
+ JALR, just 2.
+
+Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
+
+ * interp.c: Correct some HASFPU problems.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (mips_options): Fix samples option short form, should
+ be `x'.
+
Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
* interp.c (sim_info): Enable info code. Was just returning.
projects / thirdparty / binutils-gdb.git / blobdiff