+Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-profile.o module.
+
+ * sim-main.h (WITH_PROFILE): Do not define, defined in
+ common/sim-config.h. Use sim-profile module.
+ (simPROFILE): Delete defintion.
+
+ * interp.c (PROFILE): Delete definition.
+ (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
+ (sim_close): Delete code writing profile histogram.
+ (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
+ Delete.
+ (sim_engine_run): Delete code profiling the PC.
+
+Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
+
+ * interp.c (sim_monitor): Make register pointers of type
+ unsigned_word*.
+
+ * sim-main.h: Make registers of type unsigned_word not
+ signed_word.
+
+Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+start-sanitize-r5900
+ * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
+ ...): Move to sim-main.h
+
+end-sanitize-r5900
+ * interp.c (sync_operation): Rename from SyncOperation, make
+ global, add SD argument.
+ (prefetch): Rename from Prefetch, make global, add SD argument.
+ (decode_coproc): Make global.
+
+ * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
+
+ * gencode.c (build_instruction): Generate DecodeCoproc not
+ decode_coproc calls.
+
+ * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
+ (SizeFGR): Move to sim-main.h
+ (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
+ simSIGINT, simJALDELAYSLOT): Move to sim-main.h
+ (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
+ sim-main.h.
+ (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
+ FP_RM_TOMINF, GETRM): Move to sim-main.h.
+ (Uncached, CachedNoncoherent, CachedCoherent, Cached,
+ isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
+ (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
+ BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
+
+ * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
+ exception.
+ (sim-alu.h): Include.
+ (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
+ (sim_cia): Typedef to instruction_address.
+
+Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (interp.o): Rename generated file engine.c to
+ oengine.c.
+
+ * interp.c: Update.
+
+Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
+
+Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For "FPSQRT", output correct
+ number of arguments to Recip.
+
+Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (interp.o): Depends on sim-main.h
+
+ * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
+
+ * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
+ ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
+ (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
+ STATE, DSSTATE): Define
+ (GPR, FGRIDX, ..): Define.
+
+ * interp.c (registers, register_widths, fpr_state, ipc, dspc,
+ pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
+ (GPR, FGRIDX, ...): Delete macros.
+
+ * interp.c: Update names to match defines from sim-main.h
+
+Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_monitor): Add SD argument.
+ (sim_warning): Delete. Replace calls with calls to
+ sim_io_eprintf.
+ (sim_error): Delete. Replace calls with sim_io_error.
+ (open_trace, writeout32, writeout16, getnum): Add SD argument.
+ (mips_set_profile): Rename from sim_set_profile. Add SD argument.
+ (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
+ argument.
+ (mips_size): Rename from sim_size. Add SD argument.
+
+ * interp.c (simulator): Delete global variable.
+ (callback): Delete global variable.
+ (mips_option_handler, sim_open, sim_write, sim_read,
+ sim_store_register, sim_fetch_register, sim_info, sim_do_command,
+ sim_size,sim_monitor): Use sim_io_* not callback->*.
+ (sim_open): ZALLOC simulator struct.
+ (PROFILE): Do not define.
+
+Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
+ support.h with corresponding code.
+
+ * sim-main.h (word64, uword64), support.h: Move definition to
+ sim-main.h.
+ (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
+
+ * support.h: Delete
+ * Makefile.in: Update dependencies
+ * interp.c: Do not include.
+
+Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (address_translation, load_memory, store_memory,
+ cache_op): Rename to from AddressTranslation et.al., make global,
+ add SD argument
+
+ * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
+ CacheOp): Define.
+
+ * interp.c (SignalException): Rename to signal_exception, make
+ global.
+
+ * interp.c (Interrupt, ...): Move definitions to sim-main.h.
+
+ * sim-main.h (SignalException, SignalExceptionInterrupt,
+ SignalExceptionInstructionFetch, SignalExceptionAddressStore,
+ SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
+ SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
+ Define.
+
+ * interp.c, support.h: Use.
+
+Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
+ to value_fpr / store_fpr. Add SD argument.
+ (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
+ Multiply, Divide, Recip, SquareRoot, Convert): Make global.
+
+ * sim-main.h (ValueFPR, StoreFPR): Define.
+
+Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_engine_run): Check consistency between configure
+ WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
+ and HASFPU.
+
+ * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
+ (mips_fpu): Configure WITH_FLOATING_POINT.
+ (mips_endian): Configure WITH_TARGET_ENDIAN.
+ * configure: Update.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+start-sanitize-r5900
+Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (MAX_REG): Allow up-to 128 registers.
+ (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
+ (REGISTER_SA): Ditto.
+ (sim_open): Initialize register_widths for r5900 specific
+ registers.
+ (sim_fetch_register, sim_store_register): Check for request of
+ r5900 specific SA register. Check for request for hi 64 bits of
+ r5900 specific registers.
+
+end-sanitize-r5900
+Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
+
+ * configure: Regenerated.
+
+Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
+
+ * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
+
+Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (print_igen_insn_models): Assume certain architectures
+ include all mips* instructions.
+ (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
+ instruction.
+
+ * Makefile.in (tmp.igen): Add target. Generate igen input from
+ gencode file.
+
+ * gencode.c (FEATURE_IGEN): Define.
+ (main): Add --igen option. Generate output in igen format.
+ (process_instructions): Format output according to igen option.
+ (print_igen_insn_format): New function.
+ (print_igen_insn_models): New function.
+ (process_instructions): Only issue warnings and ignore
+ instructions when no FEATURE_IGEN.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
+ MIPS targets.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
+ SIM_RESERVED_BITS): Delete, moved to common.
+ (SIM_EXTRA_CFLAGS): Update.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in: Configure non-strict memory alignment.
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (SDBBP,DERET): Added (3900) insns.
+ (RFE): Turn on for 3900.
+ * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
+ (dsstate): Made global.
+ (SUBTARGET_R3900): Added.
+ (CANCELDELAYSLOT): New.
+ (SignalException): Ignore SystemCall rather than ignore and
+ terminate. Add DebugBreakPoint handling.
+ (decode_coproc): New insns RFE, DERET; and new registers Debug
+ and DEPC protected by SUBTARGET_R3900.
+ (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
+ bits explicitly.
+ * Makefile.in,configure.in: Add mips subtarget option.
+ * configure: Update.
+
+Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c: Add r3900 (tx39).
+
+start-sanitize-tx19
+ * gencode.c: Fix some configuration problems by improving
+ the relationship between tx19 and tx39.
+end-sanitize-tx19
+
+Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (build_instruction): Don't need to subtract 4 for
+ JALR, just 2.
+
+Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
+
+ * interp.c: Correct some HASFPU problems.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (mips_options): Fix samples option short form, should
+ be `x'.
+
+Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_info): Enable info code. Was just returning.
+
+Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
+ MFC0.
+
+Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): Use SIGNED64 for 64 bit
+ constants.
+ (build_instruction): Ditto for LL.
+
+start-sanitize-tx19
+Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
+
+ * mips/configure.in, mips/gencode: Add tx19/r1900.
+
+end-sanitize-tx19
+Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+start-sanitize-r5900
+Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For "pabsw" and "pabsh", check
+ for overflow due to ABS of MININT, set result to MAXINT.
+ (build_instruction): For "psrlvw", signextend bit 31.
+
+end-sanitize-r5900
+Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Add call to sim_analyze_program, update
+ call to sim_config.
+
+Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_kill): Delete.
+ (sim_create_inferior): Add ABFD argument. Set PC from same.
+ (sim_load): Move code initializing trap handlers from here.
+ (sim_open): To here.
+ (sim_load): Delete, use sim-hload.c.
+
+ * Makefile.in (SIM_OBJS): Add sim-hload.o module.
+
+Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Add ABFD argument.
+ (sim_load): Move call to sim_config from here.
+ (sim_open): To here. Check return status.
+
+start-sanitize-r5900
+ * gencode.c (build_instruction): Do not define x8000000000000000,
+ x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
+
+end-sanitize-r5900
+start-sanitize-r5900
+Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For "pdivw", "pdivbw" and
+ "pdivuw" check for overflow due to signed divide by -1.
+
+end-sanitize-r5900
+Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (build_instruction): Two arg MADD should
+ not assign result to $0.
+
+start-sanitize-r5900
+Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
+
+ * gencode.c (build_instruction): For "ppac5" use unsigned
+ arrithmetic so that the sign bit doesn't smear when right shifted.
+ (build_instruction): For "pdiv" perform sign extension when
+ storing results in HI and LO.
+ (build_instructions): For "pdiv" and "pdivbw" check for
+ divide-by-zero.
+ (build_instruction): For "pmfhl.slw" update hi part of dest
+ register as well as low part.
+ (build_instruction): For "pmfhl" portably handle long long values.
+ (build_instruction): For "pmfhl.sh" correctly negative values.
+ Store half words 2 and three in the correct place.
+ (build_instruction): For "psllvw", sign extend value after shift.
+
+end-sanitize-r5900
+Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
+
+ * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
+ * sim/mips/configure.in: Regenerate.
+
+Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
+
+ * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
+ signed8, unsigned8 et.al. types.
+
+start-sanitize-r5900
+ * gencode.c (build_instruction): For PMULTU* do not sign extend
+ registers. Make generated code easier to debug.
+
+end-sanitize-r5900
+ * interp.c (SUB_REG_FETCH): Handle both little and big endian
+ hosts when selecting subreg.
+
+start-sanitize-r5900
+Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
+
+ * gencode.c (type_for_data_len): For 32bit operations concerned
+ with overflow, perform op using 64bits.
+ (build_instruction): For PADD, always compute operation using type
+ returned by type_for_data_len.
+ (build_instruction): For PSUBU, when overflow, saturate to zero as
+ actually underflow.
+
+end-sanitize-r5900
+Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
+
+start-sanitize-r5900
+ * gencode.c (build_instruction): Handle "pext5" according to
+ version 1.95 of the r5900 ISA.
+
+ * gencode.c (build_instruction): Handle "ppac5" according to
+ version 1.95 of the r5900 ISA.
+
+end-sanitize-r5900
+ * interp.c (sim_engine_run): Reset the ZERO register to zero
+ regardless of FEATURE_WARN_ZERO.
+ * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
+
+Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
+ (SignalException): For BreakPoints ignore any mode bits and just
+ save the PC.
+ (SignalException): Always set the CAUSE register.
+
+Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (SignalException): Clear the simDELAYSLOT flag when an
+ exception has been taken.
+
+ * interp.c: Implement the ERET and mt/f sr instructions.
+
+start-sanitize-r5900
+Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (build_instruction): For paddu, extract unsigned
+ sub-fields.
+
+ * gencode.c (build_instruction): Saturate padds instead of padd
+ instructions.
+
+end-sanitize-r5900
+Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (SignalException): Don't bother restarting an
+ interrupt.
+
+Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (SignalException): Really take an interrupt.
+ (interrupt_event): Only deliver interrupts when enabled.
+
+Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_info): Only print info when verbose.
+ (sim_info) Use sim_io_printf for output.
+
+Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
+ mips architectures.
+
+Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_do_command): Check for common commands if a
+ simulator specific command fails.
+
+Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
+
+ * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
+ and simBE when DEBUG is defined.
+
+Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (interrupt_event): New function. Pass exception event
+ onto exception handler.
+
+ * configure.in: Check for stdlib.h.
+ * configure: Regenerate.
+
+ * gencode.c (build_instruction): Add UNUSED attribute to tempS
+ variable declaration.
+ (build_instruction): Initialize memval1.
+ (build_instruction): Add UNUSED attribute to byte, bigend,
+ reverse.
+ (build_operands): Ditto.
+
+ * interp.c: Fix GCC warnings.
+ (sim_get_quit_code): Delete.
+
+ * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
+ * Makefile.in: Ditto.
+ * configure: Re-generate.
+
+ * Makefile.in (SIM_OBJS): Add sim-watch.o module.
+
+Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (mips_option_handler): New function parse argumes using
+ sim-options.
+ (myname): Replace with STATE_MY_NAME.
+ (sim_open): Delete check for host endianness - performed by
+ sim_config.
+ (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
+ (sim_open): Move much of the initialization from here.
+ (sim_load): To here. After the image has been loaded and
+ endianness set.
+ (sim_open): Move ColdReset from here.
+ (sim_create_inferior): To here.
+ (sim_open): Make FP check less dependant on host endianness.
+
+ * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
+ run.
+ * interp.c (sim_set_callbacks): Delete.
+
+ * interp.c (membank, membank_base, membank_size): Replace with
+ STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
+ (sim_open): Remove call to callback->init. gdb/run do this.
+
+ * interp.c: Update
+
+ * sim-main.h (SIM_HAVE_FLATMEM): Define.
+
+ * interp.c (big_endian_p): Delete, replaced by
+ current_target_byte_order.
+
+Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (host_read_long, host_read_word, host_swap_word,
+ host_swap_long): Delete. Using common sim-endian.
+ (sim_fetch_register, sim_store_register): Use H2T.
+ (pipeline_ticks): Delete. Handled by sim-events.
+ (sim_info): Update.
+ (sim_engine_run): Update.
+
+Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_stop_reason): Move code determining simEXCEPTION
+ reason from here.
+ (SignalException): To here. Signal using sim_engine_halt.
+ (sim_stop_reason): Delete, moved to common.
+
+Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
+
+ * interp.c (sim_open): Add callback argument.
+ (sim_set_callbacks): Delete SIM_DESC argument.
+ (sim_size): Ditto.
+
+Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add common modules.
+
+ * interp.c (sim_set_callbacks): Also set SD callback.
+ (set_endianness, xfer_*, swap_*): Delete.
+ (host_read_word, host_read_long, host_swap_word, host_swap_long):
+ Change to functions using sim-endian macros.
+ (control_c, sim_stop): Delete, use common version.
+ (simulate): Convert into.
+ (sim_engine_run): This function.
+ (sim_resume): Delete.
+
+ * interp.c (simulation): New variable - the simulator object.
+ (sim_kind): Delete global - merged into simulation.
+ (sim_load): Cleanup. Move PC assignment from here.
+ (sim_create_inferior): To here.
+
+ * sim-main.h: New file.
+ * interp.c (sim-main.h): Include.
+
+Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * tconfig.in (SIM_HAVE_BIENDIAN): Define.
+
+Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
+
+ * gencode.c (build_instruction): DIV instructions: check
+ for division by zero and integer overflow before using
+ host's division operation.
+
+Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Add sim-load.o.
+ * interp.c: #include bfd.h.
+ (target_byte_order): Delete.
+ (sim_kind, myname, big_endian_p): New static locals.
+ (sim_open): Set sim_kind, myname. Move call to set_endianness to
+ after argument parsing. Recognize -E arg, set endianness accordingly.
+ (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
+ load file into simulator. Set PC from bfd.
+ (sim_create_inferior): Return SIM_RC. Delete arg start_address.
+ (set_endianness): Use big_endian_p instead of target_byte_order.
+
+Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_size): Delete prototype - conflicts with
+ definition in remote-sim.h. Correct definition.
+
+Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
* interp.c (sim_open): New arg `kind'.
Change values to avoid overloading DOUBLEWORD which is tested
for all insns.
* gencode.c: reinstate "offending code".
-end-sanitize-r5900
+end-sanitize-r5900
Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
* interp.c: Fix printing of addresses for non-64-bit targets.
projects / thirdparty / binutils-gdb.git / blobdiff