THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
- $Revision$
- $Date$
-
NOTEs:
The IDT monitor (found on the VR4300 board), seems to lie about
*/
-/* The TRACE manifests enable the provision of extra features. If they
- are not defined then a simpler (quicker) simulator is constructed
- without the required run-time checks, etc. */
-#if 1 /* 0 to allow user build selection, 1 to force inclusion */
-#define TRACE (1)
-#endif
-
+#include "config.h"
#include "bfd.h"
#include "sim-main.h"
#include "sim-utils.h"
#include "sim-options.h"
#include "sim-assert.h"
+#include "sim-hw.h"
+
+#include "itable.h"
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#include "sky-vu.h"
-#include "sky-vpe.h"
-#include "sky-libvpe.h"
-#include "sky-pke.h"
-#include "idecode.h"
-#endif
-/* end-sanitize-sky */
#include "config.h"
#include <ctype.h>
#include <limits.h>
#include <math.h>
-#ifdef HAVE_STDLIB_H
#include <stdlib.h>
-#endif
-#ifdef HAVE_STRING_H
#include <string.h>
-#else
-#ifdef HAVE_STRINGS_H
-#include <strings.h>
-#endif
-#endif
#include "getopt.h"
#include "libiberty.h"
#include "bfd.h"
-#include "callback.h" /* GDB simulator callback interface */
-#include "remote-sim.h" /* GDB simulator interface */
-
-#include "sysdep.h"
-
-#ifndef PARAMS
-#define PARAMS(x)
-#endif
-
-char* pr_addr PARAMS ((SIM_ADDR addr));
-char* pr_uword64 PARAMS ((uword64 addr));
+#include "elf-bfd.h"
+#include "gdb/callback.h" /* GDB simulator callback interface */
+#include "gdb/remote-sim.h" /* GDB simulator interface */
+#include "sim-syscall.h" /* Simulator system call support */
+char* pr_addr (SIM_ADDR addr);
+char* pr_uword64 (uword64 addr);
-/* Get the simulator engine description, without including the code: */
-#if !(WITH_IGEN)
-#define SIM_MANIFESTS
-#include "oengine.c"
-#undef SIM_MANIFESTS
-#endif
/* Within interp.c we refer to the sim_state and sim_cpu directly. */
-#define SD sd
#define CPU cpu
+#define SD sd
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
-#define RSVD_INSTRUCTION (0x00000005)
+
+#define RSVD_INSTRUCTION (0x00000039)
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
#define RSVD_INSTRUCTION_ARG_SHIFT 6
#define Debug_DM 0x40000000 /* Debug Mode */
#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
-
-
-
-
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
-static void ColdReset PARAMS((SIM_DESC sd));
+static void ColdReset (SIM_DESC sd);
/*---------------------------------------------------------------------------*/
#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
+/* Note that the monitor code essentially assumes this layout of memory.
+ If you change these, change the monitor code, too. */
+/* FIXME Currently addresses are truncated to 32-bits, see
+ mips/sim-main.c:address_translation(). If that changes, then these
+ values will need to be extended, and tested for more carefully. */
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
-#define MONITOR_BASE (0xBFC00000)
-#define MONITOR_SIZE (1 << 11)
-#define MEM_SIZE (2 << 20)
-
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#undef MEM_SIZE
-#define MEM_SIZE (16 << 20) /* 16 MB */
-#endif
-/* end-sanitize-sky */
-#if defined(TRACE)
+/* Simple run-time monitor support.
+
+ We emulate the monitor by placing magic reserved instructions at
+ the monitor's entry points; when we hit these instructions, instead
+ of raising an exception (as we would normally), we look at the
+ instruction and perform the appropriate monitory operation.
+
+ `*_monitor_base' are the physical addresses at which the corresponding
+ monitor vectors are located. `0' means none. By default,
+ install all three.
+ The RSVD_INSTRUCTION... macros specify the magic instructions we
+ use at the monitor entry points. */
+static int firmware_option_p = 0;
+static SIM_ADDR idt_monitor_base = 0xBFC00000;
+static SIM_ADDR pmon_monitor_base = 0xBFC00500;
+static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
+
+static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
+
+#define MEM_SIZE (8 << 20) /* 8 MBytes */
+
+
+#if WITH_TRACE_ANY_P
static char *tracefile = "trace.din"; /* default filename for trace log */
FILE *tracefh = NULL;
-static void open_trace PARAMS((SIM_DESC sd));
-#endif /* TRACE */
+static void open_trace (SIM_DESC sd);
+#else
+#define open_trace(sd)
+#endif
+
+static const char * get_insn_name (sim_cpu *, int);
+
+/* simulation target board. NULL=canonical */
+static char* board = NULL;
+
static DECLARE_OPTION_HANDLER (mips_option_handler);
enum {
- OPTION_DINERO_TRACE = OPTION_START,
- OPTION_DINERO_FILE
-/* start-sanitize-sky */
- ,OPTION_FLOAT_TYPE
-/* end-sanitize-sky */
+ OPTION_DINERO_TRACE = OPTION_START,
+ OPTION_DINERO_FILE,
+ OPTION_FIRMWARE,
+ OPTION_INFO_MEMORY,
+ OPTION_BOARD
};
+static int display_mem_info = 0;
+
static SIM_RC
-mips_option_handler (sd, cpu, opt, arg, is_command)
- SIM_DESC sd;
- sim_cpu *cpu;
- int opt;
- char *arg;
- int is_command;
+mips_option_handler (SIM_DESC sd, sim_cpu *cpu, int opt, char *arg,
+ int is_command)
{
int cpu_nr;
switch (opt)
{
case OPTION_DINERO_TRACE: /* ??? */
-#if defined(TRACE)
+#if WITH_TRACE_ANY_P
/* Eventually the simTRACE flag could be treated as a toggle, to
allow external control of the program points being traced
(i.e. only from main onwards, excluding the run-time setup,
}
}
return SIM_RC_OK;
-#else /* !TRACE */
+#else /* !WITH_TRACE_ANY_P */
fprintf(stderr,"\
Simulator constructed without dinero tracing support (for performance).\n\
-Re-compile simulator with \"-DTRACE\" to enable this option.\n");
+Re-compile simulator with \"-DWITH_TRACE_ANY_P\" to enable this option.\n");
return SIM_RC_FAIL;
-#endif /* !TRACE */
+#endif /* !WITH_TRACE_ANY_P */
case OPTION_DINERO_FILE:
-#if defined(TRACE)
+#if WITH_TRACE_ANY_P
if (optarg != NULL) {
char *tmp;
tmp = (char *)malloc(strlen(optarg) + 1);
sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
}
}
-#endif /* TRACE */
+#endif /* WITH_TRACE_ANY_P */
return SIM_RC_OK;
-/* start-sanitize-sky */
- case OPTION_FLOAT_TYPE:
- /* Use host (fast) or target (accurate) floating point implementation. */
- if (arg && strcmp (arg, "host") == 0)
- STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_TARGET;
- else if (arg && strcmp (arg, "target") == 0)
- STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_TARGET;
- else
- {
- fprintf (stderr, "Unrecognized float-type option `%s'\n", arg);
- return SIM_RC_FAIL;
- }
- return SIM_RC_OK;
-/* end-sanitize-sky */
- }
+ case OPTION_FIRMWARE:
+ return sim_firmware_command (sd, arg);
+
+ case OPTION_BOARD:
+ {
+ if (arg)
+ {
+ board = zalloc(strlen(arg) + 1);
+ strcpy(board, arg);
+ }
+ return SIM_RC_OK;
+ }
+ case OPTION_INFO_MEMORY:
+ display_mem_info = 1;
+ break;
+ }
+
return SIM_RC_OK;
}
+
static const OPTION mips_options[] =
{
{ {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
{ {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
'\0', "FILE", "Write dinero trace to FILE",
mips_option_handler },
-/* start-sanitize-sky */
- { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE},
- '\0', "host|target", "Use host (fast) or target (accurate) floating point",
- mips_option_handler },
-/* end-sanitize-sky */
+ { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
+ '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
+ mips_option_handler },
+ { {"board", required_argument, NULL, OPTION_BOARD},
+ '\0', "none" /* rely on compile-time string concatenation for other options */
+
+#define BOARD_JMR3904 "jmr3904"
+ "|" BOARD_JMR3904
+#define BOARD_JMR3904_PAL "jmr3904pal"
+ "|" BOARD_JMR3904_PAL
+#define BOARD_JMR3904_DEBUG "jmr3904debug"
+ "|" BOARD_JMR3904_DEBUG
+#define BOARD_BSP "bsp"
+ "|" BOARD_BSP
+
+ , "Customize simulation for a particular board.", mips_option_handler },
+
+ /* These next two options have the same names as ones found in the
+ memory_options[] array in common/sim-memopt.c. This is because
+ the intention is to provide an alternative handler for those two
+ options. We need an alternative handler because the memory
+ regions are not set up until after the command line arguments
+ have been parsed, and so we cannot display the memory info whilst
+ processing the command line. There is a hack in sim_open to
+ remove these handlers when we want the real --memory-info option
+ to work. */
+ { { "info-memory", no_argument, NULL, OPTION_INFO_MEMORY },
+ '\0', NULL, "List configured memory regions", mips_option_handler },
+ { { "memory-info", no_argument, NULL, OPTION_INFO_MEMORY },
+ '\0', NULL, NULL, mips_option_handler },
+
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
int interrupt_pending;
-static void
+void
interrupt_event (SIM_DESC sd, void *data)
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
+ address_word cia = CPU_PC_GET (cpu);
if (SR & status_IE)
{
interrupt_pending = 0;
- SignalExceptionInterrupt ();
+ SignalExceptionInterrupt (1); /* interrupt "1" */
}
else if (!interrupt_pending)
sim_events_schedule (sd, 1, interrupt_event, data);
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
+static sim_cia
+mips_pc_get (sim_cpu *cpu)
+{
+ return PC;
+}
+
+static void
+mips_pc_set (sim_cpu *cpu, sim_cia pc)
+{
+ PC = pc;
+}
+
+static int mips_reg_fetch (SIM_CPU *, int, unsigned char *, int);
+static int mips_reg_store (SIM_CPU *, int, unsigned char *, int);
+
SIM_DESC
-sim_open (kind, cb, abfd, argv)
- SIM_OPEN_KIND kind;
- host_callback *cb;
- struct _bfd *abfd;
- char **argv;
+sim_open (SIM_OPEN_KIND kind, host_callback *cb,
+ struct bfd *abfd, char * const *argv)
{
+ int i;
SIM_DESC sd = sim_state_alloc (kind, cb);
- sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
+ sim_cpu *cpu;
SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
+ /* The cpu data is kept in a separately allocated chunk of memory. */
+ if (sim_cpu_alloc_all (sd, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK)
+ return 0;
+
+ cpu = STATE_CPU (sd, 0); /* FIXME */
+
/* FIXME: watchpoints code shouldn't need this */
- STATE_WATCHPOINTS (sd)->pc = &(PC);
- STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
+ /* Initialize the mechanism for doing insn profiling. */
+ CPU_INSN_NAME (cpu) = get_insn_name;
+ CPU_MAX_INSNS (cpu) = nr_itable_entries;
+
STATE = 0;
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, mips_options);
- /* Allocate core managed memory */
-
- /* the monitor */
- sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
- /* For compatibility with the old code - under this (at level one)
- are the kernel spaces K0 & K1. Both of these map to a single
- smaller sub region */
- sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
-/* start-sanitize-sky */
-#ifndef TARGET_SKY
-/* end-sanitize-sky */
- sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
- K1BASE, K0SIZE,
- MEM_SIZE, /* actual size */
- K0BASE);
-/* start-sanitize-sky */
-#else
- sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
- K1BASE, K0SIZE,
- MEM_SIZE, /* actual size */
- K0BASE,
- 0); /* add alias at 0x0000 */
-#endif
-/* end-sanitize-sky */
-
- device_init(sd);
- /* getopt will print the error message so we just have to exit if this fails.
- FIXME: Hmmm... in the case of gdb we need getopt to call
- print_filtered. */
+ /* The parser will print an error message for us, so we silently return. */
if (sim_parse_args (sd, argv) != SIM_RC_OK)
{
/* Uninstall the modules to avoid memory leaks,
return 0;
}
+ /* handle board-specific memory maps */
+ if (board == NULL)
+ {
+ /* Allocate core managed memory */
+ sim_memopt *entry, *match = NULL;
+ address_word mem_size = 0;
+ int mapped = 0;
+
+ /* For compatibility with the old code - under this (at level one)
+ are the kernel spaces K0 & K1. Both of these map to a single
+ smaller sub region */
+ sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
+
+ /* Look for largest memory region defined on command-line at
+ phys address 0. */
+ for (entry = STATE_MEMOPT (sd); entry != NULL; entry = entry->next)
+ {
+ /* If we find an entry at address 0, then we will end up
+ allocating a new buffer in the "memory alias" command
+ below. The region at address 0 will be deleted. */
+ address_word size = (entry->modulo != 0
+ ? entry->modulo : entry->nr_bytes);
+ if (entry->addr == 0
+ && (!match || entry->level < match->level))
+ match = entry;
+ else if (entry->addr == K0BASE || entry->addr == K1BASE)
+ mapped = 1;
+ else
+ {
+ sim_memopt *alias;
+ for (alias = entry->alias; alias != NULL; alias = alias->next)
+ {
+ if (alias->addr == 0
+ && (!match || entry->level < match->level))
+ match = entry;
+ else if (alias->addr == K0BASE || alias->addr == K1BASE)
+ mapped = 1;
+ }
+ }
+ }
+
+ if (!mapped)
+ {
+ if (match)
+ {
+ /* Get existing memory region size. */
+ mem_size = (match->modulo != 0
+ ? match->modulo : match->nr_bytes);
+ /* Delete old region. */
+ sim_do_commandf (sd, "memory delete %d:0x%lx@%d",
+ match->space, match->addr, match->level);
+ }
+ else if (mem_size == 0)
+ mem_size = MEM_SIZE;
+ /* Limit to KSEG1 size (512MB) */
+ if (mem_size > K1SIZE)
+ mem_size = K1SIZE;
+ /* memory alias K1BASE@1,K1SIZE%MEMSIZE,K0BASE */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
+ K1BASE, K1SIZE, (long)mem_size, K0BASE);
+ }
+
+ device_init(sd);
+ }
+ else if (board != NULL
+ && (strcmp(board, BOARD_BSP) == 0))
+ {
+ int i;
+
+ STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
+
+ /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x9FC00000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xBFC00000);
+
+ /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x80000000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xA0000000);
+
+ /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
+ for (i=0; i<8; i++) /* 32 MB total */
+ {
+ unsigned size = 4 * 1024 * 1024; /* 4 MB */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x88000000 + (i * size),
+ size,
+ 0xA8000000 + (i * size));
+ }
+ }
+#if (WITH_HW)
+ else if (board != NULL
+ && (strcmp(board, BOARD_JMR3904) == 0 ||
+ strcmp(board, BOARD_JMR3904_PAL) == 0 ||
+ strcmp(board, BOARD_JMR3904_DEBUG) == 0))
+ {
+ /* match VIRTUAL memory layout of JMR-TX3904 board */
+ int i;
+
+ /* --- disable monitor unless forced on by user --- */
+
+ if (! firmware_option_p)
+ {
+ idt_monitor_base = 0;
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = 0;
+ }
+
+ /* --- environment --- */
+
+ STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
+
+ /* --- memory --- */
+
+ /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x9FC00000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xBFC00000);
+
+ /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x80000000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xA0000000);
+
+ /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
+ for (i=0; i<8; i++) /* 32 MB total */
+ {
+ unsigned size = 4 * 1024 * 1024; /* 4 MB */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x88000000 + (i * size),
+ size,
+ 0xA8000000 + (i * size));
+ }
+
+ /* Dummy memory regions for unsimulated devices - sorted by address */
+
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2500000, 0x004); /* LED/switch */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x900); /* DRAMC */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
+
+
+ /* --- simulated devices --- */
+ sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
+ sim_hw_parse (sd, "/tx3904cpu");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
+ {
+ /* FIXME: poking at dv-sockser internals, use tcp backend if
+ --sockser_addr option was given.*/
+ extern char* sockser_addr;
+ if(sockser_addr == NULL)
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
+ else
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
+ }
+ sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
+
+ /* -- device connections --- */
+ sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
+
+ /* add PAL timer & I/O module */
+ if(! strcmp(board, BOARD_JMR3904_PAL))
+ {
+ /* the device */
+ sim_hw_parse (sd, "/pal@0xffff0000");
+ sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
+
+ /* wire up interrupt ports to irc */
+ sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
+ sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
+ sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
+ }
+
+ if(! strcmp(board, BOARD_JMR3904_DEBUG))
+ {
+ /* -- DEBUG: glue interrupt generators --- */
+ sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
+ }
+
+ device_init(sd);
+ }
+#endif
+
+ if (display_mem_info)
+ {
+ struct option_list * ol;
+ struct option_list * prev;
+
+ /* This is a hack. We want to execute the real --memory-info command
+ line switch which is handled in common/sim-memopts.c, not the
+ override we have defined in this file. So we remove the
+ mips_options array from the state options list. This is safe
+ because we have now processed all of the command line. */
+ for (ol = STATE_OPTIONS (sd), prev = NULL;
+ ol != NULL;
+ prev = ol, ol = ol->next)
+ if (ol->options == mips_options)
+ break;
+
+ SIM_ASSERT (ol != NULL);
+
+ if (prev == NULL)
+ STATE_OPTIONS (sd) = ol->next;
+ else
+ prev->next = ol->next;
+
+ sim_do_commandf (sd, "memory-info");
+ }
+
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
{
if (rn < 32)
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
- else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
+ else if ((rn >= FGR_BASE) && (rn < (FGR_BASE + NR_FGR)))
cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
else if ((rn >= 33) && (rn <= 37))
cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
else
cpu->register_widths[rn] = 0;
}
- /* start-sanitize-r5900 */
-
- /* set the 5900 "upper" registers to 64 bits */
- for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
- cpu->register_widths[rn] = 64;
- /* end-sanitize-r5900 */
-
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- /* Now the VU registers */
- for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
- cpu->register_widths[rn + NUM_R5900_REGS] = 16;
- cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
- }
- for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
- cpu->register_widths[rn + NUM_R5900_REGS] = 32;
- cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
- }
- /* Finally the VIF registers */
- for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
- cpu->register_widths[rn + NUM_R5900_REGS] = 32;
-#endif
- /* end-sanitize-sky */
}
-#if defined(TRACE)
if (STATE & simTRACE)
open_trace(sd);
-#endif /* TRACE */
+
+ /*
+ sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
+ idt_monitor_base,
+ pmon_monitor_base,
+ lsipmon_monitor_base);
+ */
/* Write the monitor trap address handlers into the monitor (eeprom)
address space. This can only be done once the target endianness
has been determined. */
- {
- unsigned loop;
- /* Entry into the IDT monitor is via fixed address vectors, and
- not using machine instructions. To avoid clashing with use of
- the MIPS TRAP system, we place our own (simulator specific)
- "undefined" instructions into the relevant vector slots. */
- for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
- {
- address_word vaddr = (MONITOR_BASE + loop);
- unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
- H2T (insn);
- sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
- }
+ if (idt_monitor_base != 0)
+ {
+ unsigned loop;
+ unsigned idt_monitor_size = 1 << 11;
+
+ /* the default monitor region */
+ sim_do_commandf (sd, "memory region 0x%x,0x%x",
+ idt_monitor_base, idt_monitor_size);
+
+ /* Entry into the IDT monitor is via fixed address vectors, and
+ not using machine instructions. To avoid clashing with use of
+ the MIPS TRAP system, we place our own (simulator specific)
+ "undefined" instructions into the relevant vector slots. */
+ for (loop = 0; (loop < idt_monitor_size); loop += 4)
+ {
+ address_word vaddr = (idt_monitor_base + loop);
+ unsigned32 insn = (RSVD_INSTRUCTION |
+ (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
+ << RSVD_INSTRUCTION_ARG_SHIFT));
+ H2T (insn);
+ sim_write (sd, vaddr, (unsigned char *)&insn, sizeof (insn));
+ }
+ }
+
+ if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
+ {
/* The PMON monitor uses the same address space, but rather than
branching into it the address of a routine is loaded. We can
cheat for the moment, and direct the PMON routine to IDT style
instructions within the monitor space. This relies on the IDT
monitor not using the locations from 0xBFC00500 onwards as its
entry points.*/
- for (loop = 0; (loop < 24); loop++)
- {
- address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
- unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
- switch (loop)
- {
+ unsigned loop;
+ for (loop = 0; (loop < 24); loop++)
+ {
+ unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
+ switch (loop)
+ {
case 0: /* read */
value = 7;
break;
value = 28;
break;
}
- /* FIXME - should monitor_base be SIM_ADDR?? */
- value = ((unsigned int)MONITOR_BASE + (value * 8));
+
+ SIM_ASSERT (idt_monitor_base != 0);
+ value = ((unsigned int) idt_monitor_base + (value * 8));
H2T (value);
- sim_write (sd, vaddr, (char *)&value, sizeof (value));
- /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
- vaddr -= 0x300;
- sim_write (sd, vaddr, (char *)&value, sizeof (value));
+ if (pmon_monitor_base != 0)
+ {
+ address_word vaddr = (pmon_monitor_base + (loop * 4));
+ sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
+ }
+
+ if (lsipmon_monitor_base != 0)
+ {
+ address_word vaddr = (lsipmon_monitor_base + (loop * 4));
+ sim_write (sd, vaddr, (unsigned char *)&value, sizeof (value));
+ }
}
+
+ /* Write an abort sequence into the TRAP (common) exception vector
+ addresses. This is to catch code executing a TRAP (et.al.)
+ instruction without installing a trap handler. */
+ if ((idt_monitor_base != 0) ||
+ (pmon_monitor_base != 0) ||
+ (lsipmon_monitor_base != 0))
+ {
+ unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
+ HALT_INSTRUCTION /* BREAK */ };
+ H2T (halt[0]);
+ H2T (halt[1]);
+ sim_write (sd, 0x80000000, (unsigned char *) halt, sizeof (halt));
+ sim_write (sd, 0x80000180, (unsigned char *) halt, sizeof (halt));
+ sim_write (sd, 0x80000200, (unsigned char *) halt, sizeof (halt));
+ /* XXX: Write here unconditionally? */
+ sim_write (sd, 0xBFC00200, (unsigned char *) halt, sizeof (halt));
+ sim_write (sd, 0xBFC00380, (unsigned char *) halt, sizeof (halt));
+ sim_write (sd, 0xBFC00400, (unsigned char *) halt, sizeof (halt));
+ }
}
+ /* CPU specific initialization. */
+ for (i = 0; i < MAX_NR_PROCESSORS; ++i)
+ {
+ SIM_CPU *cpu = STATE_CPU (sd, i);
+
+ CPU_REG_FETCH (cpu) = mips_reg_fetch;
+ CPU_REG_STORE (cpu) = mips_reg_store;
+ CPU_PC_FETCH (cpu) = mips_pc_get;
+ CPU_PC_STORE (cpu) = mips_pc_set;
+ }
+
return sd;
}
-#if defined(TRACE)
+#if WITH_TRACE_ANY_P
static void
-open_trace(sd)
- SIM_DESC sd;
+open_trace (SIM_DESC sd)
{
tracefh = fopen(tracefile,"wb+");
if (tracefh == NULL)
tracefh = stderr;
}
}
-#endif /* TRACE */
-
-void
-sim_close (sd, quitting)
- SIM_DESC sd;
- int quitting;
-{
-#ifdef DEBUG
- printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
#endif
- /* "quitting" is non-zero if we cannot hang on errors */
-
- /* Ensure that any resources allocated through the callback
- mechanism are released: */
- sim_io_shutdown (sd);
+/* Return name of an insn, used by insn profiling. */
+static const char *
+get_insn_name (sim_cpu *cpu, int i)
+{
+ return itable[i].name;
+}
-#if defined(TRACE)
+void
+mips_sim_close (SIM_DESC sd, int quitting)
+{
+#if WITH_TRACE_ANY_P
if (tracefh != NULL && tracefh != stderr)
fclose(tracefh);
tracefh = NULL;
-#endif /* TRACE */
-
- /* FIXME - free SD */
-
- return;
-}
-
-
-int
-sim_write (sd,addr,buffer,size)
- SIM_DESC sd;
- SIM_ADDR addr;
- unsigned char *buffer;
- int size;
-{
- int index;
- sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
- /* Return the number of bytes written, or zero if error. */
-#ifdef DEBUG
- sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
#endif
-
- /* We use raw read and write routines, since we do not want to count
- the GDB memory accesses in our statistics gathering. */
-
- for (index = 0; index < size; index++)
- {
- address_word vaddr = (address_word)addr + index;
- address_word paddr;
- int cca;
- if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
- break;
- if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
- break;
- }
-
- return(index);
-}
-
-int
-sim_read (sd,addr,buffer,size)
- SIM_DESC sd;
- SIM_ADDR addr;
- unsigned char *buffer;
- int size;
-{
- int index;
- sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
-
- /* Return the number of bytes read, or zero if error. */
-#ifdef DEBUG
- sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
-#endif /* DEBUG */
-
- for (index = 0; (index < size); index++)
- {
- address_word vaddr = (address_word)addr + index;
- address_word paddr;
- int cca;
- if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
- break;
- if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
- break;
- }
-
- return(index);
}
-int
-sim_store_register (sd,rn,memory,length)
- SIM_DESC sd;
- int rn;
- unsigned char *memory;
- int length;
+static int
+mips_reg_store (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
-#ifdef DEBUG
- sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
-#endif /* DEBUG */
/* Unfortunately this suffers from the same problem as the register
numbering one. We need to know what the width of each logical
if (cpu->register_widths[rn] == 0)
{
- sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
+ sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register store ignored)\n", rn);
return 0;
}
- /* start-sanitize-r5900 */
- if (rn >= 90 && rn < 90 + 32)
- {
- GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
- return 8;
- }
- switch (rn)
- {
- case REGISTER_SA:
- SA = T2H_8(*(unsigned64*)memory);
- return 8;
- case 122: /* FIXME */
- LO1 = T2H_8(*(unsigned64*)memory);
- return 8;
- case 123: /* FIXME */
- HI1 = T2H_8(*(unsigned64*)memory);
- return 8;
- }
- /* end-sanitize-r5900 */
-
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- if (rn >= NUM_R5900_REGS)
+ if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
- rn = rn - NUM_R5900_REGS;
-
- if( rn < NUM_VU_REGS )
+ cpu->fpr_state[rn - FGR_BASE] = fmt_uninterpreted;
+ if (cpu->register_widths[rn] == 32)
{
- if (rn < NUM_VU_INTEGER_REGS)
- return write_vu_int_reg (&(vu0_device.regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
+ if (length == 8)
{
- rn -= FIRST_VEC_REG;
- return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
- memory);
+ cpu->fgr[rn - FGR_BASE] =
+ (unsigned32) T2H_8 (*(unsigned64*)memory);
+ return 8;
}
- else switch (rn - NUM_VU_INTEGER_REGS)
+ else
{
- case 0:
- return write_vu_special_reg (&vu0_device, VU_REG_CIA,
- memory);
- case 1:
- return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
- memory);
- case 2: /* VU0 has no P register */
+ cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
return 4;
- case 3:
- return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
- memory);
- case 4:
- return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
- memory);
- default:
- return write_vu_acc_reg (&(vu0_device.regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
- }
- }
-
- rn = rn - NUM_VU_REGS;
-
- if (rn < NUM_VU_REGS)
- {
- if (rn < NUM_VU_INTEGER_REGS)
- return write_vu_int_reg (&(vu1_device.regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
- {
- rn -= FIRST_VEC_REG;
- return write_vu_vec_reg (&(vu1_device.regs),
- rn >> 2, rn & 3, memory);
- }
- else switch (rn - NUM_VU_INTEGER_REGS)
- {
- case 0:
- return write_vu_special_reg (&vu1_device, VU_REG_CIA,
- memory);
- case 1:
- return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
- memory);
- case 2:
- return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
- memory);
- case 3:
- return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
- memory);
- case 4:
- return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
- memory);
- default:
- return write_vu_acc_reg (&(vu1_device.regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
}
}
-
- rn -= NUM_VU_REGS; /* VIF0 registers are next */
-
- if (rn < NUM_VIF_REGS)
+ else
{
- if (rn < NUM_VIF_REGS-1)
- return write_pke_reg (&pke0_device, rn, memory);
- else
+ if (length == 8)
{
- sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
- return 0;
+ cpu->fgr[rn - FGR_BASE] = T2H_8 (*(unsigned64*)memory);
+ return 8;
}
- }
-
- rn -= NUM_VIF_REGS; /* VIF1 registers are last */
-
- if (rn < NUM_VIF_REGS)
- {
- if (rn < NUM_VIF_REGS-1)
- return write_pke_reg (&pke1_device, rn, memory);
else
{
- sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
- return 0;
+ cpu->fgr[rn - FGR_BASE] = T2H_4 (*(unsigned32*)memory);
+ return 4;
}
}
-
- sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
- return 0;
}
-#endif
- /* end-sanitize-sky */
- if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ if (cpu->register_widths[rn] == 32)
{
- if (cpu->register_widths[rn] == 32)
+ if (length == 8)
{
- cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
- return 4;
+ cpu->registers[rn] =
+ (unsigned32) T2H_8 (*(unsigned64*)memory);
+ return 8;
}
else
{
- cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
- return 8;
+ cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
+ return 4;
}
}
-
- if (cpu->register_widths[rn] == 32)
- {
- cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
- return 4;
- }
else
{
- cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
- return 8;
+ if (length == 8)
+ {
+ cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
+ return 8;
+ }
+ else
+ {
+ cpu->registers[rn] = (signed32) T2H_4(*(unsigned32*)memory);
+ return 4;
+ }
}
return 0;
}
-int
-sim_fetch_register (sd,rn,memory,length)
- SIM_DESC sd;
- int rn;
- unsigned char *memory;
- int length;
+static int
+mips_reg_fetch (SIM_CPU *cpu, int rn, unsigned char *memory, int length)
{
- sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
-#ifdef DEBUG
- sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
-#endif /* DEBUG */
if (cpu->register_widths[rn] == 0)
{
- sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
+ sim_io_eprintf (CPU_STATE (cpu), "Invalid register width for %d (register fetch ignored)\n", rn);
return 0;
}
- /* start-sanitize-r5900 */
- if (rn >= 90 && rn < 90 + 32)
- {
- *(unsigned64*)memory = GPR1[rn - 90];
- return 8;
- }
- switch (rn)
- {
- case REGISTER_SA:
- *((unsigned64*)memory) = H2T_8(SA);
- return 8;
- case 122: /* FIXME */
- *((unsigned64*)memory) = H2T_8(LO1);
- return 8;
- case 123: /* FIXME */
- *((unsigned64*)memory) = H2T_8(HI1);
- return 8;
- }
- /* end-sanitize-r5900 */
-
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- if (rn >= NUM_R5900_REGS)
+ /* Any floating point register */
+ if (rn >= FGR_BASE && rn < FGR_BASE + NR_FGR)
{
- rn = rn - NUM_R5900_REGS;
-
- if (rn < NUM_VU_REGS)
+ if (cpu->register_widths[rn] == 32)
{
- if (rn < NUM_VU_INTEGER_REGS)
- return read_vu_int_reg (&(vu0_device.regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
+ if (length == 8)
{
- rn -= FIRST_VEC_REG;
- return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
- memory);
+ *(unsigned64*)memory =
+ H2T_8 ((unsigned32) (cpu->fgr[rn - FGR_BASE]));
+ return 8;
}
- else switch (rn - NUM_VU_INTEGER_REGS)
+ else
{
- case 0:
- return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
- case 1:
- return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
- memory);
- case 2: /* VU0 has no P register */
- *((int *) memory) = 0;
+ *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGR_BASE]);
return 4;
- case 3:
- return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
- memory);
- case 4:
- return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
- memory);
- default:
- return read_vu_acc_reg (&(vu0_device.regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
}
}
-
- rn -= NUM_VU_REGS; /* VU1 registers are next */
-
- if (rn < NUM_VU_REGS)
+ else
{
- if (rn < NUM_VU_INTEGER_REGS)
- return read_vu_int_reg (&(vu1_device.regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
+ if (length == 8)
{
- rn -= FIRST_VEC_REG;
- return read_vu_vec_reg (&(vu1_device.regs),
- rn >> 2, rn & 3, memory);
+ *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGR_BASE]);
+ return 8;
}
- else switch (rn - NUM_VU_INTEGER_REGS)
+ else
{
- case 0:
- return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
- case 1:
- return read_vu_misc_reg (&(vu1_device.regs),
- VU_REG_MR, memory);
- case 2:
- return read_vu_misc_reg (&(vu1_device.regs),
- VU_REG_MP, memory);
- case 3:
- return read_vu_misc_reg (&(vu1_device.regs),
- VU_REG_MI, memory);
- case 4:
- return read_vu_misc_reg (&(vu1_device.regs),
- VU_REG_MQ, memory);
- default:
- return read_vu_acc_reg (&(vu1_device.regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->fgr[rn - FGR_BASE]));
+ return 4;
}
}
+ }
- rn -= NUM_VU_REGS; /* VIF0 registers are next */
-
- if (rn < NUM_VIF_REGS)
+ if (cpu->register_widths[rn] == 32)
+ {
+ if (length == 8)
{
- if (rn < NUM_VIF_REGS-1)
- return read_pke_reg (&pke0_device, rn, memory);
- else
- return read_pke_pc (&pke0_device, memory);
+ *(unsigned64*)memory =
+ H2T_8 ((unsigned32) (cpu->registers[rn]));
+ return 8;
}
-
- rn -= NUM_VIF_REGS; /* VIF1 registers are last */
-
- if (rn < NUM_VIF_REGS)
+ else
{
- if (rn < NUM_VIF_REGS-1)
- return read_pke_reg (&pke1_device, rn, memory);
- else
- return read_pke_pc (&pke1_device, memory);
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ return 4;
}
-
- sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
}
-#endif
- /* end-sanitize-sky */
-
- /* Any floating point register */
- if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ else
{
- if (cpu->register_widths[rn] == 32)
+ if (length == 8)
{
- *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
- return 4;
+ *(unsigned64*)memory =
+ H2T_8 ((unsigned64) (cpu->registers[rn]));
+ return 8;
}
else
{
- *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
- return 8;
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ return 4;
}
}
- if (cpu->register_widths[rn] == 32)
- {
- *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
- return 4;
- }
- else
- {
- *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
- return 8;
- }
-
return 0;
}
-
SIM_RC
-sim_create_inferior (sd, abfd, argv,env)
- SIM_DESC sd;
- struct _bfd *abfd;
- char **argv;
- char **env;
+sim_create_inferior (SIM_DESC sd, struct bfd *abfd,
+ char * const *argv, char * const *env)
{
#ifdef DEBUG
+#if 0 /* FIXME: doesn't compile */
printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
pr_addr(PC));
+#endif
#endif /* DEBUG */
ColdReset(sd);
for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
- CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
+ sim_cia pc = bfd_get_start_address (abfd);
+
+ /* We need to undo brain-dead bfd behavior where it sign-extends
+ addresses that are supposed to be unsigned. See the mips bfd
+ sign_extend_vma setting. We have to check the ELF data itself
+ in order to handle o32 & n32 ABIs. */
+ if (abfd->tdata.elf_obj_data->elf_header->e_ident[EI_CLASS] ==
+ ELFCLASS32)
+ pc = (unsigned32) pc;
+
+ CPU_PC_SET (cpu, pc);
}
}
return SIM_RC_OK;
}
-void
-sim_do_command (sd,cmd)
- SIM_DESC sd;
- char *cmd;
-{
- if (sim_args_command (sd, cmd) != SIM_RC_OK)
- sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
- cmd);
-}
-
/*---------------------------------------------------------------------------*/
/*-- Private simulator support interface ------------------------------------*/
/*---------------------------------------------------------------------------*/
/* Read a null terminated string from memory, return in a buffer */
static char *
-fetch_str (sd, addr)
- SIM_DESC sd;
- address_word addr;
+fetch_str (SIM_DESC sd,
+ address_word addr)
{
char *buf;
int nr = 0;
- char null;
+ unsigned char null;
while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
nr++;
buf = NZALLOC (char, nr + 1);
- sim_read (sd, addr, buf, nr);
+ sim_read (sd, addr, (unsigned char *)buf, nr);
return buf;
}
+
+/* Implements the "sim firmware" command:
+ sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
+ NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
+ defaults to the normal address for that monitor.
+ sim firmware none --- don't emulate any ROM monitor. Useful
+ if you need a clean address space. */
+static SIM_RC
+sim_firmware_command (SIM_DESC sd, char *arg)
+{
+ int address_present = 0;
+ SIM_ADDR address;
+
+ /* Signal occurrence of this option. */
+ firmware_option_p = 1;
+
+ /* Parse out the address, if present. */
+ {
+ char *p = strchr (arg, '@');
+ if (p)
+ {
+ char *q;
+ address_present = 1;
+ p ++; /* skip over @ */
+
+ address = strtoul (p, &q, 0);
+ if (*q != '\0')
+ {
+ sim_io_printf (sd, "Invalid address given to the"
+ "`sim firmware NAME@ADDRESS' command: %s\n",
+ p);
+ return SIM_RC_FAIL;
+ }
+ }
+ else
+ {
+ address_present = 0;
+ address = -1; /* Dummy value. */
+ }
+ }
+
+ if (! strncmp (arg, "idt", 3))
+ {
+ idt_monitor_base = address_present ? address : 0xBFC00000;
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = 0;
+ }
+ else if (! strncmp (arg, "pmon", 4))
+ {
+ /* pmon uses indirect calls. Hook into implied idt. */
+ pmon_monitor_base = address_present ? address : 0xBFC00500;
+ idt_monitor_base = pmon_monitor_base - 0x500;
+ lsipmon_monitor_base = 0;
+ }
+ else if (! strncmp (arg, "lsipmon", 7))
+ {
+ /* lsipmon uses indirect calls. Hook into implied idt. */
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = address_present ? address : 0xBFC00200;
+ idt_monitor_base = lsipmon_monitor_base - 0x200;
+ }
+ else if (! strncmp (arg, "none", 4))
+ {
+ if (address_present)
+ {
+ sim_io_printf (sd,
+ "The `sim firmware none' command does "
+ "not take an `ADDRESS' argument.\n");
+ return SIM_RC_FAIL;
+ }
+ idt_monitor_base = 0;
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = 0;
+ }
+ else
+ {
+ sim_io_printf (sd, "\
+Unrecognized name given to the `sim firmware NAME' command: %s\n\
+Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
+ arg);
+ return SIM_RC_FAIL;
+ }
+
+ return SIM_RC_OK;
+}
+
+/* stat structures from MIPS32/64. */
+static const char stat32_map[] =
+"st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
+":st_rdev,2:st_size,4:st_atime,4:st_spare1,4:st_mtime,4:st_spare2,4"
+":st_ctime,4:st_spare3,4:st_blksize,4:st_blocks,4:st_spare4,8";
+
+static const char stat64_map[] =
+"st_dev,2:st_ino,2:st_mode,4:st_nlink,2:st_uid,2:st_gid,2"
+":st_rdev,2:st_size,8:st_atime,8:st_spare1,8:st_mtime,8:st_spare2,8"
+":st_ctime,8:st_spare3,8:st_blksize,8:st_blocks,8:st_spare4,16";
+
+/* Map for calls using the host struct stat. */
+static const CB_TARGET_DEFS_MAP CB_stat_map[] =
+{
+ { "stat", CB_SYS_stat, 15 },
+ { 0, -1, -1 }
+};
+
+
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
-static void
+int
sim_monitor (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
/* The following callback functions are available, however the
monitor we are simulating does not make use of them: get_errno,
- isatty, lseek, rename, system, time and unlink */
+ isatty, rename, system and time. */
switch (reason)
{
{
char *path = fetch_str (sd, A0);
V0 = sim_io_open (sd, path, (int)A1);
- zfree (path);
+ free (path);
break;
}
int nr = A2;
char *buf = zalloc (nr);
V0 = sim_io_read (sd, fd, buf, nr);
- sim_write (sd, A1, buf, nr);
- zfree (buf);
+ sim_write (sd, A1, (unsigned char *)buf, nr);
+ free (buf);
}
break;
int fd = A0;
int nr = A2;
char *buf = zalloc (nr);
- sim_read (sd, A1, buf, nr);
+ sim_read (sd, A1, (unsigned char *)buf, nr);
V0 = sim_io_write (sd, fd, buf, nr);
- zfree (buf);
+ if (fd == 1)
+ sim_io_flush_stdout (sd);
+ else if (fd == 2)
+ sim_io_flush_stderr (sd);
+ free (buf);
break;
}
case 11: /* char inbyte(void) */
{
char tmp;
+ /* ensure that all output has gone... */
+ sim_io_flush_stdout (sd);
if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
{
sim_io_error(sd,"Invalid return from character read");
break;
}
+ case 13: /* int unlink(const char *path) */
+ {
+ char *path = fetch_str (sd, A0);
+ V0 = sim_io_unlink (sd, path);
+ free (path);
+ break;
+ }
+
+ case 14: /* int lseek(int fd, int offset, int whence) */
+ {
+ V0 = sim_io_lseek (sd, A0, A1, A2);
+ break;
+ }
+
+ case 15: /* int stat(const char *path, struct stat *buf); */
+ {
+ /* As long as the infrastructure doesn't cache anything
+ related to the stat mapping, this trick gets us a dual
+ "struct stat"-type mapping in the least error-prone way. */
+ host_callback *cb = STATE_CALLBACK (sd);
+ const char *saved_map = cb->stat_map;
+ CB_TARGET_DEFS_MAP *saved_syscall_map = cb->syscall_map;
+ bfd *prog_bfd = STATE_PROG_BFD (sd);
+ int is_elf32bit = (elf_elfheader(prog_bfd)->e_ident[EI_CLASS] ==
+ ELFCLASS32);
+ static CB_SYSCALL s;
+ CB_SYSCALL_INIT (&s);
+ s.func = 15;
+ /* Mask out the sign extension part for 64-bit targets because the
+ MIPS simulator's memory model is still 32-bit. */
+ s.arg1 = A0 & 0xFFFFFFFF;
+ s.arg2 = A1 & 0xFFFFFFFF;
+ s.p1 = (PTR) sd;
+ s.p2 = (PTR) cpu;
+ s.read_mem = sim_syscall_read_mem;
+ s.write_mem = sim_syscall_write_mem;
+
+ cb->syscall_map = (CB_TARGET_DEFS_MAP *) CB_stat_map;
+ cb->stat_map = is_elf32bit ? stat32_map : stat64_map;
+
+ if (cb_syscall (cb, &s) != CB_RC_OK)
+ sim_engine_halt (sd, cpu, NULL, mips_pc_get (cpu),
+ sim_stopped, SIM_SIGILL);
+
+ V0 = s.result;
+ cb->stat_map = saved_map;
+ cb->syscall_map = saved_syscall_map;
+ break;
+ }
+
case 17: /* void _exit() */
{
sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
break;
}
- case 28 : /* PMON flush_cache */
+ case 28: /* PMON flush_cache */
break;
case 55: /* void get_mem_info(unsigned int *ptr) */
/* [A0 + 4] = instruction cache size */
/* [A0 + 8] = data cache size */
{
- unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
+ unsigned_4 value;
unsigned_4 zero = 0;
+ address_word mem_size;
+ sim_memopt *entry, *match = NULL;
+
+ /* Search for memory region mapped to KSEG0 or KSEG1. */
+ for (entry = STATE_MEMOPT (sd);
+ entry != NULL;
+ entry = entry->next)
+ {
+ if ((entry->addr == K0BASE || entry->addr == K1BASE)
+ && (!match || entry->level < match->level))
+ match = entry;
+ else
+ {
+ sim_memopt *alias;
+ for (alias = entry->alias;
+ alias != NULL;
+ alias = alias->next)
+ if ((alias->addr == K0BASE || alias->addr == K1BASE)
+ && (!match || entry->level < match->level))
+ match = entry;
+ }
+ }
+
+ /* Get region size, limit to KSEG1 size (512MB). */
+ SIM_ASSERT (match != NULL);
+ mem_size = (match->modulo != 0
+ ? match->modulo : match->nr_bytes);
+ if (mem_size > K1SIZE)
+ mem_size = K1SIZE;
+
+ value = mem_size;
H2T (value);
- sim_write (sd, A0 + 0, (char *)&value, 4);
- sim_write (sd, A0 + 4, (char *)&zero, 4);
- sim_write (sd, A0 + 8, (char *)&zero, 4);
- /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
+ sim_write (sd, A0 + 0, (unsigned char *)&value, 4);
+ sim_write (sd, A0 + 4, (unsigned char *)&zero, 4);
+ sim_write (sd, A0 + 8, (unsigned char *)&zero, 4);
+ /* sim_io_eprintf (sd, "sim: get_mem_info() deprecated\n"); */
break;
}
- case 158 : /* PMON printf */
+ case 158: /* PMON printf */
/* in: A0 = pointer to format string */
/* A1 = optional argument 1 */
/* A2 = optional argument 2 */
/* The following is based on the PMON printf source */
{
address_word s = A0;
- char c;
+ unsigned char c;
signed_word *ap = &A1; /* 1st argument */
/* This isn't the quickest way, since we call the host print
routine for every character almost. But it does avoid
int width = 0, trunc = 0, haddot = 0, longlong = 0;
while (sim_read (sd, s++, &c, 1) && c != '\0')
{
- if (strchr ("dobxXulscefg%", s))
+ if (strchr ("dobxXulscefg%", c))
break;
else if (c == '-')
fmt = FMT_LJUST;
if ((int)*ap != 0)
{
address_word p = *ap++;
- char ch;
+ unsigned char ch;
while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
sim_io_printf(sd, "%c", ch);
}
}
default:
- sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
- reason, pr_addr(cia));
- break;
+ /* Unknown reason. */
+ return 0;
}
- return;
+ return 1;
}
/* Store a word into memory. */
uword64 vaddr,
signed_word val)
{
- address_word paddr;
- int uncached;
+ address_word paddr = vaddr;
if ((vaddr & 3) != 0)
SignalExceptionAddressStore ();
else
{
- if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
- isTARGET, isREAL))
- {
- const uword64 mask = 7;
- uword64 memval;
- unsigned int byte;
-
- paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
- byte = (vaddr & mask) ^ (BigEndianCPU << 2);
- memval = ((uword64) val) << (8 * byte);
- StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
- isREAL);
- }
+ const uword64 mask = 7;
+ uword64 memval;
+ unsigned int byte;
+
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
+ byte = (vaddr & mask) ^ (BigEndianCPU << 2);
+ memval = ((uword64) val) << (8 * byte);
+ StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr,
+ isREAL);
}
}
uword64 vaddr)
{
if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad ();
+ {
+ SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
else
{
- address_word paddr;
- int uncached;
+ address_word paddr = vaddr;
+ const uword64 mask = 0x7;
+ const unsigned int reverse = ReverseEndian ? 1 : 0;
+ const unsigned int bigend = BigEndianCPU ? 1 : 0;
+ uword64 memval;
+ unsigned int byte;
- if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
- isTARGET, isREAL))
- {
- const uword64 mask = 0x7;
- const unsigned int reverse = ReverseEndian ? 1 : 0;
- const unsigned int bigend = BigEndianCPU ? 1 : 0;
- uword64 memval;
- unsigned int byte;
-
- paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
- LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
- isDATA, isREAL);
- byte = (vaddr & mask) ^ (bigend << 2);
- return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
- }
+ paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
+ LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA,
+ isREAL);
+ byte = (vaddr & mask) ^ (bigend << 2);
+ return EXTEND32 (memval >> (8 * byte));
}
return 0;
/*-- trace support ----------------------------------------------------------*/
-/* The TRACE support is provided (if required) in the memory accessing
+/* The trace support is provided (if required) in the memory accessing
routines. Since we are also providing the architecture specific
features, the architecture simulation code can also deal with
- notifying the TRACE world of cache flushes, etc. Similarly we do
+ notifying the trace world of cache flushes, etc. Similarly we do
not need to provide profiling support in the simulator engine,
since we can sample in the instruction fetch control loop. By
- defining the TRACE manifest, we add tracing as a run-time
+ defining the trace manifest, we add tracing as a run-time
option. */
-#if defined(TRACE)
+#if WITH_TRACE_ANY_P
/* Tracing by default produces "din" format (as required by
dineroIII). Each line of such a trace file *MUST* have a din label
and address field. The rest of the line is ignored, so comments can
return;
}
-#endif /* TRACE */
+#endif /* WITH_TRACE_ANY_P */
/*---------------------------------------------------------------------------*/
/*-- simulator engine -------------------------------------------------------*/
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
/* RESET: Fixed PC address: */
- PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
+ PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
/* The reset vector address is in the unmapped, uncached memory space. */
SR &= ~(status_SR | status_TS | status_RP);
FPR_STATE[rn] = fmt_uninterpreted;
}
+ /* Initialise the Config0 register. */
+ C0_CONFIG = 0x80000000 /* Config1 present */
+ | 2; /* KSEG0 uncached */
+ if (WITH_TARGET_WORD_BITSIZE == 64)
+ {
+ /* FIXME Currently mips/sim-main.c:address_translation()
+ truncates all addresses to 32-bits. */
+ if (0 && WITH_TARGET_ADDRESS_BITSIZE == 64)
+ C0_CONFIG |= (2 << 13); /* MIPS64, 64-bit addresses */
+ else
+ C0_CONFIG |= (1 << 13); /* MIPS64, 32-bit addresses */
+ }
+ if (BigEndianMem)
+ C0_CONFIG |= 0x00008000; /* Big Endian */
}
}
-unsigned16
-ifetch16 (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- address_word vaddr)
-{
- /* Copy the action of the LW instruction */
- address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- unsigned64 value;
- address_word paddr;
- unsigned16 instruction;
- unsigned byte;
- int cca;
- AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
- return instruction;
-}
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
address_word cia,
int exception,...)
{
- int vector;
+ /* int vector; */
#ifdef DEBUG
sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
- switch (exception) {
- /* TODO: For testing purposes I have been ignoring TRAPs. In
- reality we should either simulate them, or allow the user to
- ignore them at run-time.
- Same for SYSCALL */
- case Trap :
- sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
- break;
-
- case SystemCall :
- {
- va_list ap;
- unsigned int instruction;
- unsigned int code;
-
- va_start(ap,exception);
- instruction = va_arg(ap,unsigned int);
- va_end(ap);
+ /* Save registers before interrupt dispatching */
+#ifdef SIM_CPU_EXCEPTION_TRIGGER
+ SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
+#endif
- code = (instruction >> 6) & 0xFFFFF;
-
- sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
- code, pr_addr(cia));
- }
- break;
+ switch (exception) {
- case DebugBreakPoint :
+ case DebugBreakPoint:
if (! (Debug & Debug_DM))
{
if (INDELAYSLOT())
}
break;
- case ReservedInstruction :
+ case ReservedInstruction:
{
va_list ap;
unsigned int instruction;
perform this magic. */
if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
{
- sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
+ int reason = (instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK;
+ if (!sim_monitor (SD, CPU, cia, reason))
+ sim_io_error (sd, "sim_monitor: unhandled reason = %d, pc = 0x%s\n", reason, pr_addr (cia));
+
/* NOTE: This assumes that a branch-and-link style
instruction was used to enter the vector (which is the
case with the current IDT monitor). */
sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
/* else fall through to normal exception processing */
- sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
+ sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
}
- case BreakPoint:
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
-#endif /* DEBUG */
- /* Keep a copy of the current A0 in-case this is the program exit
- breakpoint: */
- {
- va_list ap;
- unsigned int instruction;
- va_start(ap,exception);
- instruction = va_arg(ap,unsigned int);
- va_end(ap);
- /* Check for our special terminating BREAK: */
- if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
- sim_engine_halt (SD, CPU, NULL, cia,
- sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
- }
- }
- if (STATE & simDELAYSLOT)
- PC = cia - 4; /* reference the branch instruction */
- else
- PC = cia;
- sim_engine_halt (SD, CPU, NULL, cia,
- sim_stopped, SIM_SIGTRAP);
-
default:
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
+#ifdef SUBTARGET_R3900
+ /* update interrupt-related registers */
+
+ /* insert exception code in bits 6:2 */
+ CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
+ /* shift IE/KU history bits left */
+ SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
+
+ if (STATE & simDELAYSLOT)
+ {
+ STATE &= ~simDELAYSLOT;
+ CAUSE |= cause_BD;
+ EPC = (cia - 4); /* reference the branch instruction */
+ }
+ else
+ EPC = cia;
+
+ if (SR & status_BEV)
+ PC = (signed)0xBFC00000 + 0x180;
+ else
+ PC = (signed)0x80000000 + 0x080;
+#else
/* See figure 5-17 for an outline of the code below */
if (! (SR & status_EXL))
{
else
EPC = cia;
/* FIXME: TLB et.al. */
- vector = 0x180;
+ /* vector = 0x180; */
}
else
{
CAUSE = (exception << 2);
- vector = 0x180;
+ /* vector = 0x180; */
}
SR |= status_EXL;
/* Store exception code into current exception id variable (used
by exit code): */
+
if (SR & status_BEV)
PC = (signed)0xBFC00200 + 0x180;
else
PC = (signed)0x80000000 + 0x180;
+#endif
switch ((CAUSE >> 2) & 0x1F)
{
/* Interrupts arrive during event processing, no need to
restart */
return;
-
+
+ case NMIReset:
+ /* Ditto */
+#ifdef SUBTARGET_3900
+ /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
+ PC = (signed)0xBFC00000;
+#endif /* SUBTARGET_3900 */
+ return;
+
case TLBModification:
case TLBLoad:
case TLBStore:
case InstructionFetch:
case DataReference:
/* The following is so that the simulator will continue from the
- exception address on breakpoint operations. */
- PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ exception handler address. */
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGBUS);
case ReservedInstruction:
case CoProcessorUnusable:
PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGILL);
case IntegerOverflow:
case FPE:
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGFPE);
+
+ case BreakPoint:
+ sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
+ break;
+ case SystemCall:
case Trap:
+ sim_engine_restart (SD, CPU, NULL, PC);
+ break;
+
case Watch:
- case SystemCall:
PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGTRAP);
- case BreakPoint:
- PC = EPC;
- sim_engine_abort (SD, CPU, NULL_CIA,
- "FATAL: Should not encounter a breakpoint\n");
-
- default : /* Unknown internal exception */
+ default: /* Unknown internal exception */
PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGABRT);
}
return;
}
-#if defined(WARN_RESULT)
-/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
-/* This function indicates that the result of the operation is
- undefined. However, this should not affect the instruction
- stream. All that is meant to happen is that the destination
- register is set to an undefined result. To keep the simulator
- simple, we just don't bother updating the destination register, so
- the overall result will be undefined. If desired we can stop the
- simulator by raising a pseudo-exception. */
-#define UndefinedResult() undefined_result (sd,cia)
-static void
-undefined_result(sd,cia)
- SIM_DESC sd;
- address_word cia;
-{
- sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
-#if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
- state |= simSTOP;
-#endif
- return;
-}
-#endif /* WARN_RESULT */
-
-/*-- FPU support routines ---------------------------------------------------*/
-
-/* Numbers are held in normalized form. The SINGLE and DOUBLE binary
- formats conform to ANSI/IEEE Std 754-1985. */
-/* SINGLE precision floating:
- * seeeeeeeefffffffffffffffffffffff
- * s = 1bit = sign
- * e = 8bits = exponent
- * f = 23bits = fraction
- */
-/* SINGLE precision fixed:
- * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
- * s = 1bit = sign
- * i = 31bits = integer
- */
-/* DOUBLE precision floating:
- * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
- * s = 1bit = sign
- * e = 11bits = exponent
- * f = 52bits = fraction
- */
-/* DOUBLE precision fixed:
- * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
- * s = 1bit = sign
- * i = 63bits = integer
- */
-
-/* Extract sign-bit: */
-#define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
-#define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
-/* Extract biased exponent: */
-#define FP_S_be(v) (((v) >> 23) & 0xFF)
-#define FP_D_be(v) (((v) >> 52) & 0x7FF)
-/* Extract unbiased Exponent: */
-#define FP_S_e(v) (FP_S_be(v) - 0x7F)
-#define FP_D_e(v) (FP_D_be(v) - 0x3FF)
-/* Extract complete fraction field: */
-#define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
-#define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
-/* Extract numbered fraction bit: */
-#define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
-#define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
-
-/* Explicit QNaN values used when value required: */
-#define FPQNaN_SINGLE (0x7FBFFFFF)
-#define FPQNaN_WORD (0x7FFFFFFF)
-#define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
-#define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
-
-/* Explicit Infinity values used when required: */
-#define FPINF_SINGLE (0x7F800000)
-#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
-
-#if 1 /* def DEBUG */
-#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
-#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
-#endif /* DEBUG */
-
-uword64
-value_fpr (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int fpr,
- FP_formats fmt)
-{
- uword64 value = 0;
- int err = 0;
-
- /* Treat unused register values, as fixed-point 64bit values: */
- if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
-#if 1
- /* If request to read data as "uninterpreted", then use the current
- encoding: */
- fmt = FPR_STATE[fpr];
-#else
- fmt = fmt_long;
-#endif
- /* For values not yet accessed, set to the desired format: */
- if (FPR_STATE[fpr] == fmt_uninterpreted) {
- FPR_STATE[fpr] = fmt;
-#ifdef DEBUG
- printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
-#endif /* DEBUG */
- }
- if (fmt != FPR_STATE[fpr]) {
- sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
- FPR_STATE[fpr] = fmt_unknown;
- }
- if (FPR_STATE[fpr] == fmt_unknown) {
- /* Set QNaN value: */
- switch (fmt) {
- case fmt_single:
- value = FPQNaN_SINGLE;
- break;
+/* This function implements what the MIPS32 and MIPS64 ISAs define as
+ "UNPREDICTABLE" behaviour.
- case fmt_double:
- value = FPQNaN_DOUBLE;
- break;
+ About UNPREDICTABLE behaviour they say: "UNPREDICTABLE results
+ may vary from processor implementation to processor implementation,
+ instruction to instruction, or as a function of time on the same
+ implementation or instruction. Software can never depend on results
+ that are UNPREDICTABLE. ..." (MIPS64 Architecture for Programmers
+ Volume II, The MIPS64 Instruction Set. MIPS Document MD00087 revision
+ 0.95, page 2.)
+
+ For UNPREDICTABLE behaviour, we print a message, if possible print
+ the offending instructions mips.igen instruction name (provided by
+ the caller), and stop the simulator.
- case fmt_word:
- value = FPQNaN_WORD;
- break;
+ XXX FIXME: eventually, stopping the simulator should be made conditional
+ on a command-line option. */
+void
+unpredictable_action(sim_cpu *cpu, address_word cia)
+{
+ SIM_DESC sd = CPU_STATE(cpu);
- case fmt_long:
- value = FPQNaN_LONG;
- break;
+ sim_io_eprintf(sd, "UNPREDICTABLE: PC = 0x%s\n", pr_addr (cia));
+ sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGABRT);
+}
- default:
- err = -1;
- break;
- }
- } else if (SizeFGR() == 64) {
- switch (fmt) {
- case fmt_single:
- case fmt_word:
- value = (FGR[fpr] & 0xFFFFFFFF);
- break;
- case fmt_uninterpreted:
- case fmt_double:
- case fmt_long:
- value = FGR[fpr];
- break;
+/*-- co-processor support routines ------------------------------------------*/
- default :
- err = -1;
- break;
- }
- } else {
- switch (fmt) {
- case fmt_single:
- case fmt_word:
- value = (FGR[fpr] & 0xFFFFFFFF);
- break;
+static int UNUSED
+CoProcPresent(unsigned int coproc_number)
+{
+ /* Return TRUE if simulator provides a model for the given co-processor number */
+ return(0);
+}
- case fmt_uninterpreted:
- case fmt_double:
- case fmt_long:
- if ((fpr & 1) == 0) { /* even registers only */
- value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
- } else {
- SignalException(ReservedInstruction,0);
- }
- break;
+void
+cop_lw (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ unsigned int memword)
+{
+ switch (coproc_num)
+ {
+ case 1:
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+#ifdef DEBUG
+ printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
+#endif
+ StoreFPR(coproc_reg,fmt_uninterpreted_32,(uword64)memword);
+ break;
+ }
- default :
- err = -1;
+ default:
+#if 0 /* this should be controlled by a configuration option */
+ sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
+#endif
break;
}
- }
-
- if (err)
- SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
-
-#ifdef DEBUG
- printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
-#endif /* DEBUG */
- return(value);
+ return;
}
void
-store_fpr (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int fpr,
- FP_formats fmt,
- uword64 value)
+cop_ld (SIM_DESC sd,
+ sim_cpu *cpu,
+ address_word cia,
+ int coproc_num,
+ int coproc_reg,
+ uword64 memword)
{
- int err = 0;
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
-#endif /* DEBUG */
+ printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
+#endif
- if (SizeFGR() == 64) {
- switch (fmt) {
- case fmt_uninterpreted_32:
- fmt = fmt_uninterpreted;
- case fmt_single :
- case fmt_word :
- FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
- FPR_STATE[fpr] = fmt;
- break;
-
- case fmt_uninterpreted_64:
- fmt = fmt_uninterpreted;
- case fmt_uninterpreted:
- case fmt_double :
- case fmt_long :
- FGR[fpr] = value;
- FPR_STATE[fpr] = fmt;
- break;
-
- default :
- FPR_STATE[fpr] = fmt_unknown;
- err = -1;
- break;
- }
- } else {
- switch (fmt) {
- case fmt_uninterpreted_32:
- fmt = fmt_uninterpreted;
- case fmt_single :
- case fmt_word :
- FGR[fpr] = (value & 0xFFFFFFFF);
- FPR_STATE[fpr] = fmt;
- break;
-
- case fmt_uninterpreted_64:
- fmt = fmt_uninterpreted;
- case fmt_uninterpreted:
- case fmt_double :
- case fmt_long :
- if ((fpr & 1) == 0) { /* even register number only */
- FGR[fpr+1] = (value >> 32);
- FGR[fpr] = (value & 0xFFFFFFFF);
- FPR_STATE[fpr + 1] = fmt;
- FPR_STATE[fpr] = fmt;
- } else {
- FPR_STATE[fpr] = fmt_unknown;
- FPR_STATE[fpr + 1] = fmt_unknown;
- SignalException(ReservedInstruction,0);
- }
- break;
-
- default :
- FPR_STATE[fpr] = fmt_unknown;
- err = -1;
- break;
- }
- }
-#if defined(WARN_RESULT)
- else
- UndefinedResult();
-#endif /* WARN_RESULT */
-
- if (err)
- SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
-
-#ifdef DEBUG
- printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
-#endif /* DEBUG */
-
- return;
-}
-
-int
-NaN(op,fmt)
- uword64 op;
- FP_formats fmt;
-{
- int boolean = 0;
- switch (fmt) {
- case fmt_single:
- case fmt_word:
- {
- sim_fpu wop;
- sim_fpu_32to (&wop, op);
- boolean = sim_fpu_is_nan (&wop);
- break;
- }
- case fmt_double:
- case fmt_long:
- {
- sim_fpu wop;
- sim_fpu_64to (&wop, op);
- boolean = sim_fpu_is_nan (&wop);
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
-printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(boolean);
-}
-
-int
-Infinity(op,fmt)
- uword64 op;
- FP_formats fmt;
-{
- int boolean = 0;
-
-#ifdef DEBUG
- printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
-#endif /* DEBUG */
-
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop;
- sim_fpu_32to (&wop, op);
- boolean = sim_fpu_is_infinity (&wop);
- break;
- }
- case fmt_double:
- {
- sim_fpu wop;
- sim_fpu_64to (&wop, op);
- boolean = sim_fpu_is_infinity (&wop);
- break;
- }
- default:
- printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
- break;
- }
-
-#ifdef DEBUG
- printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(boolean);
-}
-
-int
-Less(op1,op2,fmt)
- uword64 op1;
- uword64 op2;
- FP_formats fmt;
-{
- int boolean = 0;
-
- /* Argument checking already performed by the FPCOMPARE code */
-
-#ifdef DEBUG
- printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- boolean = sim_fpu_is_lt (&wop1, &wop2);
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- boolean = sim_fpu_is_lt (&wop1, &wop2);
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
-#endif /* DEBUG */
-
- return(boolean);
-}
-
-int
-Equal(op1,op2,fmt)
- uword64 op1;
- uword64 op2;
- FP_formats fmt;
-{
- int boolean = 0;
-
- /* Argument checking already performed by the FPCOMPARE code */
-
-#ifdef DEBUG
- printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- boolean = sim_fpu_is_eq (&wop1, &wop2);
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- boolean = sim_fpu_is_eq (&wop1, &wop2);
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
-#endif /* DEBUG */
-
- return(boolean);
-}
-
-uword64
-AbsoluteValue(op,fmt)
- uword64 op;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
-#endif /* DEBUG */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop;
- unsigned32 ans;
- sim_fpu_32to (&wop, op);
- sim_fpu_abs (&wop, &wop);
- sim_fpu_to32 (&ans, &wop);
- result = ans;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop;
- unsigned64 ans;
- sim_fpu_64to (&wop, op);
- sim_fpu_abs (&wop, &wop);
- sim_fpu_to64 (&ans, &wop);
- result = ans;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
- return(result);
-}
-
-uword64
-Negate(op,fmt)
- uword64 op;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
-#endif /* DEBUG */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop;
- unsigned32 ans;
- sim_fpu_32to (&wop, op);
- sim_fpu_neg (&wop, &wop);
- sim_fpu_to32 (&ans, &wop);
- result = ans;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop;
- unsigned64 ans;
- sim_fpu_64to (&wop, op);
- sim_fpu_neg (&wop, &wop);
- sim_fpu_to64 (&ans, &wop);
- result = ans;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
- return(result);
-}
-
-uword64
-Add(op1,op2,fmt)
- uword64 op1;
- uword64 op2;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned32 res;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- sim_fpu_add (&ans, &wop1, &wop2);
- sim_fpu_to32 (&res, &ans);
- result = res;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned64 res;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- sim_fpu_add (&ans, &wop1, &wop2);
- sim_fpu_to64 (&res, &ans);
- result = res;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-
-uword64
-Sub(op1,op2,fmt)
- uword64 op1;
- uword64 op2;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned32 res;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- sim_fpu_sub (&ans, &wop1, &wop2);
- sim_fpu_to32 (&res, &ans);
- result = res;
- }
- break;
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned64 res;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- sim_fpu_sub (&ans, &wop1, &wop2);
- sim_fpu_to64 (&res, &ans);
- result = res;
- }
- break;
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-
-uword64
-Multiply(op1,op2,fmt)
- uword64 op1;
- uword64 op2;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned32 res;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- sim_fpu_mul (&ans, &wop1, &wop2);
- sim_fpu_to32 (&res, &ans);
- result = res;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned64 res;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- sim_fpu_mul (&ans, &wop1, &wop2);
- sim_fpu_to64 (&res, &ans);
- result = res;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-
-uword64
-Divide(op1,op2,fmt)
- uword64 op1;
- uword64 op2;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned32 res;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- sim_fpu_div (&ans, &wop1, &wop2);
- sim_fpu_to32 (&res, &ans);
- result = res;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu ans;
- unsigned64 res;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- sim_fpu_div (&ans, &wop1, &wop2);
- sim_fpu_to64 (&res, &ans);
- result = res;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-
-uword64 UNUSED
-Recip(op,fmt)
- uword64 op;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop;
- sim_fpu ans;
- unsigned32 res;
- sim_fpu_32to (&wop, op);
- sim_fpu_inv (&ans, &wop);
- sim_fpu_to32 (&res, &ans);
- result = res;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop;
- sim_fpu ans;
- unsigned64 res;
- sim_fpu_64to (&wop, op);
- sim_fpu_inv (&ans, &wop);
- sim_fpu_to64 (&res, &ans);
- result = res;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-
-uword64
-SquareRoot(op,fmt)
- uword64 op;
- FP_formats fmt;
-{
- uword64 result = 0;
-
-#ifdef DEBUG
- printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt) {
- case fmt_single:
- {
- sim_fpu wop;
- sim_fpu ans;
- unsigned32 res;
- sim_fpu_32to (&wop, op);
- sim_fpu_sqrt (&ans, &wop);
- sim_fpu_to32 (&res, &ans);
- result = res;
- break;
- }
- case fmt_double:
- {
- sim_fpu wop;
- sim_fpu ans;
- unsigned64 res;
- sim_fpu_64to (&wop, op);
- sim_fpu_sqrt (&ans, &wop);
- sim_fpu_to64 (&res, &ans);
- result = res;
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-
-#if 0
-uword64
-Max (uword64 op1,
- uword64 op2,
- FP_formats fmt)
-{
- int cmp;
- unsigned64 result;
-
-#ifdef DEBUG
- printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt)
- {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- cmp = sim_fpu_cmp (&wop1, &wop2);
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- cmp = sim_fpu_cmp (&wop1, &wop2);
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
- switch (cmp)
- {
- case SIM_FPU_IS_SNAN:
- case SIM_FPU_IS_QNAN:
- result = op1;
- case SIM_FPU_IS_NINF:
- case SIM_FPU_IS_NNUMBER:
- case SIM_FPU_IS_NDENORM:
- case SIM_FPU_IS_NZERO:
- result = op2; /* op1 - op2 < 0 */
- case SIM_FPU_IS_PINF:
- case SIM_FPU_IS_PNUMBER:
- case SIM_FPU_IS_PDENORM:
- case SIM_FPU_IS_PZERO:
- result = op1; /* op1 - op2 > 0 */
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-#endif
-
-#if 0
-uword64
-Min (uword64 op1,
- uword64 op2,
- FP_formats fmt)
-{
- int cmp;
- unsigned64 result;
-
-#ifdef DEBUG
- printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
-#endif /* DEBUG */
-
- /* The registers must specify FPRs valid for operands of type
- "fmt". If they are not valid, the result is undefined. */
-
- /* The format type should already have been checked: */
- switch (fmt)
- {
- case fmt_single:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_32to (&wop1, op1);
- sim_fpu_32to (&wop2, op2);
- cmp = sim_fpu_cmp (&wop1, &wop2);
- break;
- }
- case fmt_double:
- {
- sim_fpu wop1;
- sim_fpu wop2;
- sim_fpu_64to (&wop1, op1);
- sim_fpu_64to (&wop2, op2);
- cmp = sim_fpu_cmp (&wop1, &wop2);
- break;
- }
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
- switch (cmp)
- {
- case SIM_FPU_IS_SNAN:
- case SIM_FPU_IS_QNAN:
- result = op1;
- case SIM_FPU_IS_NINF:
- case SIM_FPU_IS_NNUMBER:
- case SIM_FPU_IS_NDENORM:
- case SIM_FPU_IS_NZERO:
- result = op1; /* op1 - op2 < 0 */
- case SIM_FPU_IS_PINF:
- case SIM_FPU_IS_PNUMBER:
- case SIM_FPU_IS_PDENORM:
- case SIM_FPU_IS_PZERO:
- result = op2; /* op1 - op2 > 0 */
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
-#endif /* DEBUG */
-
- return(result);
-}
-#endif
-
-uword64
-convert (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int rm,
- uword64 op,
- FP_formats from,
- FP_formats to)
-{
- sim_fpu wop;
- sim_fpu_round round;
- unsigned32 result32;
- unsigned64 result64;
-
-#ifdef DEBUG
- printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
-#endif /* DEBUG */
-
- switch (rm)
- {
- case FP_RM_NEAREST:
- /* Round result to nearest representable value. When two
- representable values are equally near, round to the value
- that has a least significant bit of zero (i.e. is even). */
- round = sim_fpu_round_near;
- break;
- case FP_RM_TOZERO:
- /* Round result to the value closest to, and not greater in
- magnitude than, the result. */
- round = sim_fpu_round_zero;
- break;
- case FP_RM_TOPINF:
- /* Round result to the value closest to, and not less than,
- the result. */
- round = sim_fpu_round_up;
- break;
-
- case FP_RM_TOMINF:
- /* Round result to the value closest to, and not greater than,
- the result. */
- round = sim_fpu_round_down;
- break;
- default:
- round = 0;
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
- /* Convert the input to sim_fpu internal format */
- switch (from)
- {
- case fmt_double:
- sim_fpu_64to (&wop, op);
- break;
- case fmt_single:
- sim_fpu_32to (&wop, op);
- break;
- case fmt_word:
- sim_fpu_i32to (&wop, op, round);
- break;
- case fmt_long:
- sim_fpu_i64to (&wop, op, round);
- break;
- default:
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
- /* Convert sim_fpu format into the output */
- /* The value WOP is converted to the destination format, rounding
- using mode RM. When the destination is a fixed-point format, then
- a source value of Infinity, NaN or one which would round to an
- integer outside the fixed point range then an IEEE Invalid
- Operation condition is raised. */
- switch (to)
- {
- case fmt_single:
- sim_fpu_round_32 (&wop, round, 0);
- sim_fpu_to32 (&result32, &wop);
- result64 = result32;
- break;
- case fmt_double:
- sim_fpu_round_64 (&wop, round, 0);
- sim_fpu_to64 (&result64, &wop);
- break;
- case fmt_word:
- sim_fpu_to32i (&result32, &wop, round);
- result64 = result32;
- break;
- case fmt_long:
- sim_fpu_to64i (&result64, &wop, round);
- break;
- default:
- result64 = 0;
- fprintf (stderr, "Bad switch\n");
- abort ();
- }
-
-#ifdef DEBUG
- printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
-#endif /* DEBUG */
-
- return(result64);
-}
-
-
-/*-- co-processor support routines ------------------------------------------*/
-
-static int UNUSED
-CoProcPresent(coproc_number)
- unsigned int coproc_number;
-{
- /* Return TRUE if simulator provides a model for the given co-processor number */
- return(0);
-}
-
-void
-cop_lw (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int coproc_num,
- int coproc_reg,
- unsigned int memword)
-{
- switch (coproc_num)
- {
- case 1:
- if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
- {
-#ifdef DEBUG
- printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
-#endif
- StoreFPR(coproc_reg,fmt_word,(uword64)memword);
- FPR_STATE[coproc_reg] = fmt_uninterpreted;
- break;
- }
-
- default:
-#if 0 /* this should be controlled by a configuration option */
- sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
-#endif
- break;
- }
-
- return;
-}
-
-void
-cop_ld (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int coproc_num,
- int coproc_reg,
- uword64 memword)
-{
- switch (coproc_num) {
- case 1:
- if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
- {
- StoreFPR(coproc_reg,fmt_uninterpreted,memword);
- break;
+ switch (coproc_num) {
+ case 1:
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ {
+ StoreFPR(coproc_reg,fmt_uninterpreted_64,memword);
+ break;
}
default:
}
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-void
-cop_lq (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int coproc_num,
- int coproc_reg,
- unsigned128 memword)
-{
- switch (coproc_num)
- {
- case 2:
- {
- unsigned_16 xyzw;
-
- while(vu0_busy())
- vu0_issue(sd);
-
- memcpy(& xyzw, & memword, sizeof(xyzw));
- xyzw = H2T_16(xyzw);
- /* one word at a time, argh! */
- write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 0, A4_16(& xyzw, 3));
- write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 1, A4_16(& xyzw, 2));
- write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 2, A4_16(& xyzw, 1));
- write_vu_vec_reg(&(vu0_device.regs), coproc_reg, 3, A4_16(& xyzw, 0));
- }
- break;
-
- default:
- sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
- coproc_num,coproc_reg,pr_addr(cia));
- break;
- }
-
- return;
-}
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
unsigned int
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
- FP_formats hold;
- hold = FPR_STATE[coproc_reg];
- FPR_STATE[coproc_reg] = fmt_word;
- value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
- FPR_STATE[coproc_reg] = hold;
+ value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted_32);
break;
}
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
{
- value = ValueFPR(coproc_reg,fmt_uninterpreted);
+ value = ValueFPR(coproc_reg,fmt_uninterpreted_64);
break;
}
}
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-unsigned128
-cop_sq (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int coproc_num,
- int coproc_reg)
-{
- unsigned128 value = U16_8(0, 0);
- switch (coproc_num)
- {
- case 2:
- {
- unsigned_16 xyzw;
-
- while(vu0_busy())
- vu0_issue(sd);
-
- /* one word at a time, argh! */
- read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 0, A4_16(& xyzw, 3));
- read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 1, A4_16(& xyzw, 2));
- read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 2, A4_16(& xyzw, 1));
- read_vu_vec_reg(&(vu0_device.regs), coproc_reg, 3, A4_16(& xyzw, 0));
- xyzw = T2H_16(xyzw);
- return xyzw;
- }
- break;
-
- default:
- sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
- coproc_num,coproc_reg,pr_addr(cia));
- break;
- }
-
- return(value);
-}
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
void
decode_coproc (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
- unsigned int instruction)
+ unsigned int instruction,
+ int coprocnum,
+ CP0_operation op,
+ int rt,
+ int rd,
+ int sel)
{
- int coprocnum = ((instruction >> 26) & 3);
-
switch (coprocnum)
{
case 0: /* standard CPU control and cache registers */
{
- int code = ((instruction >> 21) & 0x1F);
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
+ CODE><-RT><RD-><--TAIL--->
DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
- if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
+ if (((op == cp0_mfc0) || (op == cp0_mtc0) /* MFC0 / MTC0 */
+ || (op == cp0_dmfc0) || (op == cp0_dmtc0)) /* DMFC0 / DMTC0 */
+ && sel == 0)
{
- int rt = ((instruction >> 16) & 0x1F);
- int rd = ((instruction >> 11) & 0x1F);
-
switch (rd) /* NOTEs: Standard CP0 registers */
{
/* 0 = Index R4000 VR4100 VR4300 */
/* 10 = EntryHi R4000 VR4100 VR4300 */
/* 11 = Compare R4000 VR4100 VR4300 */
/* 12 = SR R4000 VR4100 VR4300 */
+#ifdef SUBTARGET_R3900
+ case 3:
+ /* 3 = Config R3900 */
+ case 7:
+ /* 7 = Cache R3900 */
+ case 15:
+ /* 15 = PRID R3900 */
+
+ /* ignore */
+ break;
+
+ case 8:
+ /* 8 = BadVAddr R4000 VR4100 VR4300 */
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
+ GPR[rt] = (signed_word) (signed_address) COP0_BADVADDR;
+ else
+ COP0_BADVADDR = GPR[rt];
+ break;
+
+#endif /* SUBTARGET_R3900 */
case 12:
- if (code == 0x00)
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = SR;
else
SR = GPR[rt];
break;
/* 13 = Cause R4000 VR4100 VR4300 */
case 13:
- if (code == 0x00)
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = CAUSE;
else
CAUSE = GPR[rt];
break;
/* 14 = EPC R4000 VR4100 VR4300 */
+ case 14:
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
+ GPR[rt] = (signed_word) (signed_address) EPC;
+ else
+ EPC = GPR[rt];
+ break;
/* 15 = PRId R4000 VR4100 VR4300 */
#ifdef SUBTARGET_R3900
/* 16 = Debug */
case 16:
- if (code == 0x00)
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = Debug;
else
Debug = GPR[rt];
#else
/* 16 = Config R4000 VR4100 VR4300 */
case 16:
- if (code == 0x00)
- GPR[rt] = C0_CONFIG;
- else
- C0_CONFIG = GPR[rt];
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
+ GPR[rt] = C0_CONFIG;
+ else
+ /* only bottom three bits are writable */
+ C0_CONFIG = (C0_CONFIG & ~0x7) | (GPR[rt] & 0x7);
break;
#endif
#ifdef SUBTARGET_R3900
/* 17 = Debug */
case 17:
- if (code == 0x00)
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
GPR[rt] = DEPC;
else
DEPC = GPR[rt];
/* 28 = TagLo R4000 VR4100 VR4300 */
/* 29 = TagHi R4000 VR4100 VR4300 */
/* 30 = ErrorEPC R4000 VR4100 VR4300 */
+ if (STATE_VERBOSE_P(SD))
+ sim_io_eprintf (SD,
+ "Warning: PC 0x%lx:interp.c decode_coproc DEADC0DE\n",
+ (unsigned long)cia);
GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
/* CPR[0,rd] = GPR[rt]; */
default:
+ if (op == cp0_mfc0 || op == cp0_dmfc0)
+ GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
+ else
+ COP0_GPR[rd] = GPR[rt];
+#if 0
if (code == 0x00)
- sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
else
- sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
+#endif
+ }
+ }
+ else if ((op == cp0_mfc0 || op == cp0_dmfc0)
+ && rd == 16)
+ {
+ /* [D]MFC0 RT,C0_CONFIG,SEL */
+ signed32 cfg = 0;
+ switch (sel)
+ {
+ case 0:
+ cfg = C0_CONFIG;
+ break;
+ case 1:
+ /* MIPS32 r/o Config1:
+ Config2 present */
+ cfg = 0x80000000;
+ /* MIPS16 implemented.
+ XXX How to check configuration? */
+ cfg |= 0x0000004;
+ if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
+ /* MDMX & FPU implemented */
+ cfg |= 0x00000021;
+ break;
+ case 2:
+ /* MIPS32 r/o Config2:
+ Config3 present. */
+ cfg = 0x80000000;
+ break;
+ case 3:
+ /* MIPS32 r/o Config3:
+ SmartMIPS implemented. */
+ cfg = 0x00000002;
+ break;
}
+ GPR[rt] = cfg;
}
- else if (code == 0x10 && (instruction & 0x3f) == 0x18)
+ else if (op == cp0_eret && sel == 0x18)
{
/* ERET */
if (SR & status_ERL)
SR &= ~status_EXL;
}
}
- else if (code == 0x10 && (instruction & 0x3f) == 0x10)
+ else if (op == cp0_rfe && sel == 0x10)
{
/* RFE */
+#ifdef SUBTARGET_R3900
+ /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
+
+ /* shift IE/KU history bits right */
+ SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
+
+ /* TODO: CACHE register */
+#endif /* SUBTARGET_R3900 */
}
- else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
+ else if (op == cp0_deret && sel == 0x1F)
{
/* DERET */
Debug &= ~Debug_DM;
{
int handle = 0;
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- /* On the R5900, this refers to a "VU" vector co-processor. */
-
- int i_25_21 = (instruction >> 21) & 0x1f;
- int i_20_16 = (instruction >> 16) & 0x1f;
- int i_20_6 = (instruction >> 6) & 0x7fff;
- int i_15_11 = (instruction >> 11) & 0x1f;
- int i_15_0 = instruction & 0xffff;
- int i_10_1 = (instruction >> 1) & 0x3ff;
- int i_10_0 = instruction & 0x7ff;
- int i_10_6 = (instruction >> 6) & 0x1f;
- int i_5_0 = instruction & 0x03f;
- int interlock = instruction & 0x01;
- /* setup for semantic.c-like actions below */
- typedef unsigned_4 instruction_word;
- int CIA = cia;
- int NIA = cia + 4;
- sim_cpu* CPU_ = cpu;
-
- handle = 1;
-
- /* test COP2 usability */
- if(! (SR & status_CU2))
- {
- SignalException(CoProcessorUnusable,instruction);
- /* NOTREACHED */
- }
-
- /* classify & execute basic COP2 instructions */
- if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- }
- else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- else NULLIFY_NEXT_INSTRUCTION();
- }
- else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- }
- else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- else NULLIFY_NEXT_INSTRUCTION();
- }
- else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
- (i_25_21 == 0x01)) /* QMFC2 */
- {
- int rt = i_20_16;
- int id = i_15_11;
-
- /* interlock checking */
- /* POLICY: never busy in macro mode */
- while(vu0_busy() && interlock)
- vu0_issue(sd);
-
- /* perform VU register address */
- if(i_25_21 == 0x01) /* QMFC2 */
- {
- unsigned_16 xyzw;
- /* one word at a time, argh! */
- read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
- read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
- read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
- read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
- xyzw = T2H_16(xyzw);
- memcpy(& GPR[rt], & xyzw, sizeof(xyzw));
- }
- else /* CFC2 */
- {
- unsigned_4 data;
- /* enum + int calculation, argh! */
- id = VU_REG_MST + 16 * id;
- read_vu_misc_reg(&(vu0_device.regs), id, & data);
- GPR[rt] = EXTEND32(T2H_4(data));
- }
- }
- else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
- (i_25_21 == 0x05)) /* QMTC2 */
- {
- int rt = i_20_16;
- int id = i_15_11;
-
- /* interlock checking */
- /* POLICY: never busy in macro mode */
- if(vu0_busy() && interlock)
- {
- while(! vu0_micro_interlock_released())
- vu0_issue(sd);
- }
-
- /* perform VU register address */
- if(i_25_21 == 0x05) /* QMTC2 */
- {
- unsigned_16 xyzw;
- memcpy(& xyzw, & GPR[rt], sizeof(xyzw));
- xyzw = H2T_16(xyzw);
- /* one word at a time, argh! */
- write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
- write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
- write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
- write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
- }
- else /* CTC2 */
- {
- unsigned_4 data = H2T_4(GPR[rt]);
- /* enum + int calculation, argh! */
- id = VU_REG_MST + 16 * id;
- write_vu_misc_reg(&(vu0_device.regs), id, & data);
- }
- }
- else if(i_10_0 == 0x3bf) /* VWAITQ */
- {
- while(vu0_q_busy())
- vu0_issue(sd);
- }
- else if(i_5_0 == 0x38) /* VCALLMS */
- {
- unsigned_4 data = H2T_2(i_20_6);
-
- while(vu0_busy())
- vu0_issue(sd);
-
- /* write to reserved CIA register to get VU0 moving */
- write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
-
- ASSERT(vu0_busy());
- }
- else if(i_5_0 == 0x39) /* VCALLMSR */
- {
- unsigned_4 data;
-
- while(vu0_busy())
- vu0_issue(sd);
-
- read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
- /* write to reserved CIA register to get VU0 moving */
- write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
-
- ASSERT(vu0_busy());
- }
- /* handle all remaining UPPER VU instructions in one block */
- else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
- (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
- {
- unsigned_4 vu_upper, vu_lower;
- vu_upper =
- 0x00000000 | /* bits 31 .. 25 */
- (instruction & 0x01ffffff); /* bits 24 .. 0 */
- vu_lower = 0x8000033c; /* NOP */
-
- /* POLICY: never busy in macro mode */
- while(vu0_busy())
- vu0_issue(sd);
-
- vu0_macro_issue(vu_upper, vu_lower);
-
- /* POLICY: wait for completion of macro-instruction */
- while(vu0_busy())
- vu0_issue(sd);
- }
- /* handle all remaining LOWER VU instructions in one block */
- else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
- (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
- { /* N.B.: VWAITQ already covered by prior case */
- unsigned_4 vu_upper, vu_lower;
- vu_upper = 0x000002ff; /* NOP/NOP */
- vu_lower =
- 0x10000000 | /* bits 31 .. 25 */
- (instruction & 0x01ffffff); /* bits 24 .. 0 */
-
- /* POLICY: never busy in macro mode */
- while(vu0_busy())
- vu0_issue(sd);
-
- vu0_macro_issue(vu_upper, vu_lower);
-
- /* POLICY: wait for completion of macro-instruction */
- while(vu0_busy())
- vu0_issue(sd);
- }
- /* ... no other COP2 instructions ... */
- else
- {
- SignalException(ReservedInstruction, instruction);
- /* NOTREACHED */
- }
-
- /* cleanup for semantic.c-like actions above */
- PC = NIA;
-
-#endif /* TARGET_SKY */
- /* end-sanitize-sky */
if(! handle)
{
}
-/*-- instruction simulation -------------------------------------------------*/
-
-/* When the IGEN simulator is being built, the function below is be
- replaced by a generated version. However, WITH_IGEN == 2 indicates
- that the fubction below should be compiled but under a different
- name (to allow backward compatibility) */
-
-#if (WITH_IGEN != 1)
-#if (WITH_IGEN > 1)
-void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
-void
-old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
-#else
-void
-sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
-#endif
- SIM_DESC sd;
- int next_cpu_nr; /* ignore */
- int nr_cpus; /* ignore */
- int siggnal; /* ignore */
-{
- sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
-#if !defined(FASTSIM)
- unsigned int pipeline_count = 1;
-#endif
-
-#ifdef DEBUG
- if (STATE_MEMORY (sd) == NULL) {
- printf("DBG: simulate() entered with no memory\n");
- exit(1);
- }
-#endif /* DEBUG */
-
-#if 0 /* Disabled to check that everything works OK */
- /* The VR4300 seems to sign-extend the PC on its first
- access. However, this may just be because it is currently
- configured in 32bit mode. However... */
- PC = SIGNEXTEND(PC,32);
-#endif
-
- /* main controlling loop */
- while (1) {
- /* vaddr is slowly being replaced with cia - current instruction
- address */
- address_word cia = (uword64)PC;
- address_word vaddr = cia;
- address_word paddr;
- int cca;
- unsigned int instruction; /* uword64? what's this used for? FIXME! */
-
-#ifdef DEBUG
- {
- printf("DBG: state = 0x%08X :",state);
- if (state & simHALTEX) printf(" simHALTEX");
- if (state & simHALTIN) printf(" simHALTIN");
- printf("\n");
- }
-#endif /* DEBUG */
-
- DSSTATE = (STATE & simDELAYSLOT);
-#ifdef DEBUG
- if (dsstate)
- sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
-#endif /* DEBUG */
-
- /* Fetch the next instruction from the simulator memory: */
- if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
- if ((vaddr & 1) == 0) {
- /* Copy the action of the LW instruction */
- unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- uword64 value;
- unsigned int byte;
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
- } else {
- /* Copy the action of the LH instruction */
- unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
- unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
- uword64 value;
- unsigned int byte;
- paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
- | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
- LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
- paddr & ~ (uword64) 1,
- vaddr, isINSTRUCTION, isREAL);
- byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
- instruction = ((value >> (8 * byte)) & 0xFFFF);
- }
- } else {
- fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
- exit(1);
- }
-
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
-#endif /* DEBUG */
-
- /* This is required by exception processing, to ensure that we can
- cope with exceptions in the delay slots of branches that may
- already have changed the PC. */
- if ((vaddr & 1) == 0)
- PC += 4; /* increment ready for the next fetch */
- else
- PC += 2;
- /* NOTE: If we perform a delay slot change to the PC, this
- increment is not requuired. However, it would make the
- simulator more complicated to try and avoid this small hit. */
-
- /* Currently this code provides a simple model. For more
- complicated models we could perform exception status checks at
- this point, and set the simSTOP state as required. This could
- also include processing any hardware interrupts raised by any
- I/O model attached to the simulator context.
-
- Support for "asynchronous" I/O events within the simulated world
- could be providing by managing a counter, and calling a I/O
- specific handler when a particular threshold is reached. On most
- architectures a decrement and check for zero operation is
- usually quicker than an increment and compare. However, the
- process of managing a known value decrement to zero, is higher
- than the cost of using an explicit value UINT_MAX into the
- future. Which system is used will depend on how complicated the
- I/O model is, and how much it is likely to affect the simulator
- bandwidth.
-
- If events need to be scheduled further in the future than
- UINT_MAX event ticks, then the I/O model should just provide its
- own counter, triggered from the event system. */
-
- /* MIPS pipeline ticks. To allow for future support where the
- pipeline hit of individual instructions is known, this control
- loop manages a "pipeline_count" variable. It is initialised to
- 1 (one), and will only be changed by the simulator engine when
- executing an instruction. If the engine does not have access to
- pipeline cycle count information then all instructions will be
- treated as using a single cycle. NOTE: A standard system is not
- provided by the default simulator because different MIPS
- architectures have different cycle counts for the same
- instructions.
-
- [NOTE: pipeline_count has been replaced the event queue] */
-
- /* shuffle the floating point status pipeline state */
- ENGINE_ISSUE_PREFIX_HOOK();
-
-/* NOTE: For multi-context simulation environments the "instruction"
- variable should be local to this routine. */
-
-/* Shorthand accesses for engine. Note: If we wanted to use global
- variables (and a single-threaded simulator engine), then we can
- create the actual variables with these names. */
-
- if (!(STATE & simSKIPNEXT)) {
- /* Include the simulator engine */
-#include "oengine.c"
-#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
-#error "Mismatch between run-time simulator code and simulation engine"
-#endif
-#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
-#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
-#endif
-#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
-#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
-#endif
-
-#if defined(WARN_LOHI)
- /* Decrement the HI/LO validity ticks */
- if (HIACCESS > 0)
- HIACCESS--;
- if (LOACCESS > 0)
- LOACCESS--;
- /* start-sanitize-r5900 */
- if (HI1ACCESS > 0)
- HI1ACCESS--;
- if (LO1ACCESS > 0)
- LO1ACCESS--;
- /* end-sanitize-r5900 */
-#endif /* WARN_LOHI */
-
- /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
- should check for it being changed. It is better doing it here,
- than within the simulator, since it will help keep the simulator
- small. */
- if (ZERO != 0) {
-#if defined(WARN_ZERO)
- sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
-#endif /* WARN_ZERO */
- ZERO = 0; /* reset back to zero before next instruction */
- }
- } else /* simSKIPNEXT check */
- STATE &= ~simSKIPNEXT;
-
- /* If the delay slot was active before the instruction is
- executed, then update the PC to its new value: */
- if (DSSTATE) {
-#ifdef DEBUG
- printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
-#endif /* DEBUG */
- PC = DSPC;
- CANCELDELAYSLOT();
- }
-
- if (MIPSISA < 4)
- PENDING_TICK();
-
-#if !defined(FASTSIM)
- if (sim_events_tickn (sd, pipeline_count))
- {
- /* cpu->cia = cia; */
- sim_events_process (sd);
- }
-#else
- if (sim_events_tick (sd))
- {
- /* cpu->cia = cia; */
- sim_events_process (sd);
- }
-#endif /* FASTSIM */
- }
-}
-#endif
-
-
/* This code copied from gdb's utils.c. Would like to share this code,
but don't know of a common place where both could get to it. */
#define NUMCELLS 16
#define CELLSIZE 32
static char*
-get_cell()
+get_cell (void)
{
static char buf[NUMCELLS][CELLSIZE];
static int cell=0;
static int thirty_two = 32;
char*
-pr_addr(addr)
- SIM_ADDR addr;
+pr_addr (SIM_ADDR addr)
{
char *paddr_str=get_cell();
switch (sizeof(addr))
}
char*
-pr_uword64(addr)
- uword64 addr;
+pr_uword64 (uword64 addr)
{
char *paddr_str=get_cell();
sprintf(paddr_str,"%08lx%08lx",
}
+void
+mips_core_signal (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_cia cia,
+ unsigned map,
+ int nr_bytes,
+ address_word addr,
+ transfer_type transfer,
+ sim_core_signals sig)
+{
+ const char *copy = (transfer == read_transfer ? "read" : "write");
+ address_word ip = CIA_ADDR (cia);
+
+ switch (sig)
+ {
+ case sim_core_unmapped_signal:
+ sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
+ nr_bytes, copy,
+ (unsigned long) addr, (unsigned long) ip);
+ COP0_BADVADDR = addr;
+ SignalExceptionDataReference();
+ break;
+
+ case sim_core_unaligned_signal:
+ sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
+ nr_bytes, copy,
+ (unsigned long) addr, (unsigned long) ip);
+ COP0_BADVADDR = addr;
+ if(transfer == read_transfer)
+ SignalExceptionAddressLoad();
+ else
+ SignalExceptionAddressStore();
+ break;
+
+ default:
+ sim_engine_abort (sd, cpu, cia,
+ "mips_core_signal - internal error - bad switch");
+ }
+}
+
+
+void
+mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
+{
+ ASSERT(cpu != NULL);
+
+ if(cpu->exc_suspended > 0)
+ sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
+
+ PC = cia;
+ memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
+ cpu->exc_suspended = 0;
+}
+
+void
+mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
+{
+ ASSERT(cpu != NULL);
+
+ if(cpu->exc_suspended > 0)
+ sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
+ cpu->exc_suspended, exception);
+
+ memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
+ memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
+ cpu->exc_suspended = exception;
+}
+
+void
+mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
+{
+ ASSERT(cpu != NULL);
+
+ if(exception == 0 && cpu->exc_suspended > 0)
+ {
+ /* warn not for breakpoints */
+ if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
+ sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
+ cpu->exc_suspended);
+ }
+ else if(exception != 0 && cpu->exc_suspended > 0)
+ {
+ if(exception != cpu->exc_suspended)
+ sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
+ cpu->exc_suspended, exception);
+
+ memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
+ }
+ else if(exception != 0 && cpu->exc_suspended == 0)
+ {
+ sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
+ }
+ cpu->exc_suspended = 0;
+}
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
projects / thirdparty / binutils-gdb.git / blobdiff