#include "sim-utils.h"
#include "sim-options.h"
#include "sim-assert.h"
+#include "sim-hw.h"
+
+#include "itable.h"
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#include "sky-vu.h"
-#include "sky-vpe.h"
-#include "sky-libvpe.h"
-#include "sky-pke.h"
-#endif
-/* end-sanitize-sky */
#include "config.h"
char* pr_uword64 PARAMS ((uword64 addr));
-/* Get the simulator engine description, without including the code: */
-#if !(WITH_IGEN)
-#define SIM_MANIFESTS
-#include "oengine.c"
-#undef SIM_MANIFESTS
-#endif
-
/* Within interp.c we refer to the sim_state and sim_cpu directly. */
-#define SD sd
#define CPU cpu
+#define SD sd
/* The following reserved instruction value is used when a simulator
trap is required. NOTE: Care must be taken, since this value may be
used in later revisions of the MIPS ISA. */
+
#define RSVD_INSTRUCTION (0x00000005)
#define RSVD_INSTRUCTION_MASK (0xFC00003F)
#define Debug_DM 0x40000000 /* Debug Mode */
#define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
-
-
-
-
/*---------------------------------------------------------------------------*/
/*-- GDB simulator interface ------------------------------------------------*/
/*---------------------------------------------------------------------------*/
#define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
#define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
+/* Note that the monitor code essentially assumes this layout of memory.
+ If you change these, change the monitor code, too. */
#define K0BASE (0x80000000)
#define K0SIZE (0x20000000)
#define K1BASE (0xA0000000)
#define K1SIZE (0x20000000)
-#define MONITOR_BASE (0xBFC00000)
-#define MONITOR_SIZE (1 << 11)
+
+/* Simple run-time monitor support.
+
+ We emulate the monitor by placing magic reserved instructions at
+ the monitor's entry points; when we hit these instructions, instead
+ of raising an exception (as we would normally), we look at the
+ instruction and perform the appropriate monitory operation.
+
+ `*_monitor_base' are the physical addresses at which the corresponding
+ monitor vectors are located. `0' means none. By default,
+ install all three.
+ The RSVD_INSTRUCTION... macros specify the magic instructions we
+ use at the monitor entry points. */
+static int firmware_option_p = 0;
+static SIM_ADDR idt_monitor_base = 0xBFC00000;
+static SIM_ADDR pmon_monitor_base = 0xBFC00500;
+static SIM_ADDR lsipmon_monitor_base = 0xBFC00200;
+
+static SIM_RC sim_firmware_command (SIM_DESC sd, char* arg);
+
+
#define MEM_SIZE (2 << 20)
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-#undef MEM_SIZE
-#define MEM_SIZE (16 << 20) /* 16 MB */
-#endif
-/* end-sanitize-sky */
#if defined(TRACE)
static char *tracefile = "trace.din"; /* default filename for trace log */
static void open_trace PARAMS((SIM_DESC sd));
#endif /* TRACE */
+static const char * get_insn_name (sim_cpu *, int);
+
+/* simulation target board. NULL=canonical */
+static char* board = NULL;
+
+
static DECLARE_OPTION_HANDLER (mips_option_handler);
enum {
- OPTION_DINERO_TRACE = OPTION_START,
- OPTION_DINERO_FILE
-/* start-sanitize-sky */
- ,OPTION_FLOAT_TYPE
-/* end-sanitize-sky */
+ OPTION_DINERO_TRACE = OPTION_START,
+ OPTION_DINERO_FILE,
+ OPTION_FIRMWARE,
+ OPTION_BOARD
};
+
static SIM_RC
mips_option_handler (sd, cpu, opt, arg, is_command)
SIM_DESC sd;
#endif /* TRACE */
return SIM_RC_OK;
-/* start-sanitize-sky */
- case OPTION_FLOAT_TYPE:
- /* Use host (fast) or target (accurate) floating point implementation. */
- if (arg && strcmp (arg, "host") == 0)
- STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_TARGET;
- else if (arg && strcmp (arg, "target") == 0)
- STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_TARGET;
- else
- {
- fprintf (stderr, "Unrecognized float-type option `%s'\n", arg);
- return SIM_RC_FAIL;
- }
- return SIM_RC_OK;
-/* end-sanitize-sky */
- }
+ case OPTION_FIRMWARE:
+ return sim_firmware_command (sd, arg);
+ case OPTION_BOARD:
+ {
+ if (arg)
+ {
+ board = zalloc(strlen(arg) + 1);
+ strcpy(board, arg);
+ }
+ return SIM_RC_OK;
+ }
+ }
+
return SIM_RC_OK;
}
+
static const OPTION mips_options[] =
{
{ {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
{ {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
'\0', "FILE", "Write dinero trace to FILE",
mips_option_handler },
-/* start-sanitize-sky */
- { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE},
- '\0', "host|target", "Use host (fast) or target (accurate) floating point",
- mips_option_handler },
-/* end-sanitize-sky */
+ { {"firmware", required_argument, NULL, OPTION_FIRMWARE},
+ '\0', "[idt|pmon|lsipmon|none][@ADDRESS]", "Emulate ROM monitor",
+ mips_option_handler },
+ { {"board", required_argument, NULL, OPTION_BOARD},
+ '\0', "none" /* rely on compile-time string concatenation for other options */
+
+#define BOARD_JMR3904 "jmr3904"
+ "|" BOARD_JMR3904
+#define BOARD_JMR3904_PAL "jmr3904pal"
+ "|" BOARD_JMR3904_PAL
+#define BOARD_JMR3904_DEBUG "jmr3904debug"
+ "|" BOARD_JMR3904_DEBUG
+#define BOARD_BSP "bsp"
+ "|" BOARD_BSP
+
+ , "Customize simulation for a particular board.", mips_option_handler },
+
{ {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
};
int interrupt_pending;
-static void
+void
interrupt_event (SIM_DESC sd, void *data)
{
sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
+ address_word cia = CIA_GET (cpu);
if (SR & status_IE)
{
interrupt_pending = 0;
- SignalExceptionInterrupt ();
+ SignalExceptionInterrupt (1); /* interrupt "1" */
}
else if (!interrupt_pending)
sim_events_schedule (sd, 1, interrupt_event, data);
STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
+ /* Initialize the mechanism for doing insn profiling. */
+ CPU_INSN_NAME (cpu) = get_insn_name;
+ CPU_MAX_INSNS (cpu) = nr_itable_entries;
+
STATE = 0;
if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
return 0;
sim_add_option_table (sd, NULL, mips_options);
- /* Allocate core managed memory */
-
- /* the monitor */
- sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
- /* For compatibility with the old code - under this (at level one)
- are the kernel spaces K0 & K1. Both of these map to a single
- smaller sub region */
- sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
-/* start-sanitize-sky */
-#ifndef TARGET_SKY
-/* end-sanitize-sky */
- sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
- K1BASE, K0SIZE,
- MEM_SIZE, /* actual size */
- K0BASE);
-/* start-sanitize-sky */
-#else
- sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
- K1BASE, K0SIZE,
- MEM_SIZE, /* actual size */
- K0BASE,
- 0); /* add alias at 0x0000 */
-#endif
-/* end-sanitize-sky */
-
- device_init(sd);
/* getopt will print the error message so we just have to exit if this fails.
FIXME: Hmmm... in the case of gdb we need getopt to call
return 0;
}
+ /* handle board-specific memory maps */
+ if (board == NULL)
+ {
+ /* Allocate core managed memory */
+
+
+ /* For compatibility with the old code - under this (at level one)
+ are the kernel spaces K0 & K1. Both of these map to a single
+ smaller sub region */
+ sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
+ K1BASE, K0SIZE,
+ MEM_SIZE, /* actual size */
+ K0BASE);
+
+ device_init(sd);
+ }
+ else if (board != NULL
+ && (strcmp(board, BOARD_BSP) == 0))
+ {
+ int i;
+
+ STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
+
+ /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x9FC00000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xBFC00000);
+
+ /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x80000000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xA0000000);
+
+ /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
+ for (i=0; i<8; i++) /* 32 MB total */
+ {
+ unsigned size = 4 * 1024 * 1024; /* 4 MB */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x88000000 + (i * size),
+ size,
+ 0xA8000000 + (i * size));
+ }
+ }
+#if (WITH_HW)
+ else if (board != NULL
+ && (strcmp(board, BOARD_JMR3904) == 0 ||
+ strcmp(board, BOARD_JMR3904_PAL) == 0 ||
+ strcmp(board, BOARD_JMR3904_DEBUG) == 0))
+ {
+ /* match VIRTUAL memory layout of JMR-TX3904 board */
+ int i;
+
+ /* --- disable monitor unless forced on by user --- */
+
+ if (! firmware_option_p)
+ {
+ idt_monitor_base = 0;
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = 0;
+ }
+
+ /* --- environment --- */
+
+ STATE_ENVIRONMENT (sd) = OPERATING_ENVIRONMENT;
+
+ /* --- memory --- */
+
+ /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x9FC00000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xBFC00000);
+
+ /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x80000000,
+ 4 * 1024 * 1024, /* 4 MB */
+ 0xA0000000);
+
+ /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
+ for (i=0; i<8; i++) /* 32 MB total */
+ {
+ unsigned size = 4 * 1024 * 1024; /* 4 MB */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
+ 0x88000000 + (i * size),
+ size,
+ 0xA8000000 + (i * size));
+ }
+
+ /* Dummy memory regions for unsimulated devices */
+
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFE000, 0x01c); /* EBIF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF9000, 0x200); /* EBIF */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFFF500, 0x300); /* PIO */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xFFFF8000, 0x804); /* DRAMC */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2100000, 0x004); /* ISA ctl */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB1000000, 0x400); /* ISA I/O */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB2700000, 0x004); /* RTC */
+ sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx", 0xB3C00000, 0x004); /* RTC */
+
+ /* --- simulated devices --- */
+ sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
+ sim_hw_parse (sd, "/tx3904cpu");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300/reg 0xfffff300 0x100");
+ {
+ /* FIXME: poking at dv-sockser internals, use tcp backend if
+ --sockser_addr option was given.*/
+ extern char* sockser_addr;
+ if(sockser_addr == NULL)
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend stdio");
+ else
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300/backend tcp");
+ }
+ sim_hw_parse (sd, "/tx3904sio@0xfffff400/reg 0xfffff400 0x100");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff400/backend stdio");
+
+ /* -- device connections --- */
+ sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff300 > int sio0 /tx3904irc");
+ sim_hw_parse (sd, "/tx3904sio@0xfffff400 > int sio1 /tx3904irc");
+
+ /* add PAL timer & I/O module */
+ if(! strcmp(board, BOARD_JMR3904_PAL))
+ {
+ /* the device */
+ sim_hw_parse (sd, "/pal@0xffff0000");
+ sim_hw_parse (sd, "/pal@0xffff0000/reg 0xffff0000 64");
+
+ /* wire up interrupt ports to irc */
+ sim_hw_parse (sd, "/pal@0x31000000 > countdown tmr0 /tx3904irc");
+ sim_hw_parse (sd, "/pal@0x31000000 > timer tmr1 /tx3904irc");
+ sim_hw_parse (sd, "/pal@0x31000000 > int int0 /tx3904irc");
+ }
+
+ if(! strcmp(board, BOARD_JMR3904_DEBUG))
+ {
+ /* -- DEBUG: glue interrupt generators --- */
+ sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
+ sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
+ }
+
+ device_init(sd);
+ }
+#endif
+
+
/* check for/establish the a reference program image */
if (sim_analyze_program (sd,
(STATE_PROG_ARGV (sd) != NULL
else
cpu->register_widths[rn] = 0;
}
- /* start-sanitize-r5900 */
-
- /* set the 5900 "upper" registers to 64 bits */
- for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
- cpu->register_widths[rn] = 64;
- /* end-sanitize-r5900 */
-
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- /* Now the VU registers */
- for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
- cpu->register_widths[rn + NUM_R5900_REGS] = 16;
- cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
- }
- for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
- cpu->register_widths[rn + NUM_R5900_REGS] = 32;
- cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
- }
- /* Finally the VIF registers */
- for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
- cpu->register_widths[rn + NUM_R5900_REGS] = 32;
-#endif
- /* end-sanitize-sky */
}
#if defined(TRACE)
open_trace(sd);
#endif /* TRACE */
+ /*
+ sim_io_eprintf (sd, "idt@%x pmon@%x lsipmon@%x\n",
+ idt_monitor_base,
+ pmon_monitor_base,
+ lsipmon_monitor_base);
+ */
+
/* Write the monitor trap address handlers into the monitor (eeprom)
address space. This can only be done once the target endianness
has been determined. */
- {
- unsigned loop;
- /* Entry into the IDT monitor is via fixed address vectors, and
- not using machine instructions. To avoid clashing with use of
- the MIPS TRAP system, we place our own (simulator specific)
- "undefined" instructions into the relevant vector slots. */
- for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
- {
- address_word vaddr = (MONITOR_BASE + loop);
- unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
- H2T (insn);
- sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
- }
+ if (idt_monitor_base != 0)
+ {
+ unsigned loop;
+ unsigned idt_monitor_size = 1 << 11;
+
+ /* the default monitor region */
+ sim_do_commandf (sd, "memory region 0x%x,0x%x",
+ idt_monitor_base, idt_monitor_size);
+
+ /* Entry into the IDT monitor is via fixed address vectors, and
+ not using machine instructions. To avoid clashing with use of
+ the MIPS TRAP system, we place our own (simulator specific)
+ "undefined" instructions into the relevant vector slots. */
+ for (loop = 0; (loop < idt_monitor_size); loop += 4)
+ {
+ address_word vaddr = (idt_monitor_base + loop);
+ unsigned32 insn = (RSVD_INSTRUCTION |
+ (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK)
+ << RSVD_INSTRUCTION_ARG_SHIFT));
+ H2T (insn);
+ sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
+ }
+ }
+
+ if ((pmon_monitor_base != 0) || (lsipmon_monitor_base != 0))
+ {
/* The PMON monitor uses the same address space, but rather than
branching into it the address of a routine is loaded. We can
cheat for the moment, and direct the PMON routine to IDT style
instructions within the monitor space. This relies on the IDT
monitor not using the locations from 0xBFC00500 onwards as its
entry points.*/
- for (loop = 0; (loop < 24); loop++)
- {
- address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
- unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
- switch (loop)
- {
+ unsigned loop;
+ for (loop = 0; (loop < 24); loop++)
+ {
+ unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
+ switch (loop)
+ {
case 0: /* read */
value = 7;
break;
value = 28;
break;
}
- /* FIXME - should monitor_base be SIM_ADDR?? */
- value = ((unsigned int)MONITOR_BASE + (value * 8));
+
+ SIM_ASSERT (idt_monitor_base != 0);
+ value = ((unsigned int) idt_monitor_base + (value * 8));
H2T (value);
- sim_write (sd, vaddr, (char *)&value, sizeof (value));
- /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
- vaddr -= 0x300;
- sim_write (sd, vaddr, (char *)&value, sizeof (value));
+ if (pmon_monitor_base != 0)
+ {
+ address_word vaddr = (pmon_monitor_base + (loop * 4));
+ sim_write (sd, vaddr, (char *)&value, sizeof (value));
+ }
+
+ if (lsipmon_monitor_base != 0)
+ {
+ address_word vaddr = (lsipmon_monitor_base + (loop * 4));
+ sim_write (sd, vaddr, (char *)&value, sizeof (value));
+ }
}
+
+ /* Write an abort sequence into the TRAP (common) exception vector
+ addresses. This is to catch code executing a TRAP (et.al.)
+ instruction without installing a trap handler. */
+ if ((idt_monitor_base != 0) ||
+ (pmon_monitor_base != 0) ||
+ (lsipmon_monitor_base != 0))
+ {
+ unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
+ HALT_INSTRUCTION /* BREAK */ };
+ H2T (halt[0]);
+ H2T (halt[1]);
+ sim_write (sd, 0x80000000, (char *) halt, sizeof (halt));
+ sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
+ sim_write (sd, 0x80000200, (char *) halt, sizeof (halt));
+ /* XXX: Write here unconditionally? */
+ sim_write (sd, 0xBFC00200, (char *) halt, sizeof (halt));
+ sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
+ sim_write (sd, 0xBFC00400, (char *) halt, sizeof (halt));
+ }
}
+
+
return sd;
}
}
#endif /* TRACE */
+/* Return name of an insn, used by insn profiling. */
+static const char *
+get_insn_name (sim_cpu *cpu, int i)
+{
+ return itable[i].name;
+}
+
void
sim_close (sd, quitting)
SIM_DESC sd;
printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
#endif
+
/* "quitting" is non-zero if we cannot hang on errors */
+ /* shut down modules */
+ sim_module_uninstall (sd);
+
/* Ensure that any resources allocated through the callback
mechanism are released: */
sim_io_shutdown (sd);
return 0;
}
- /* start-sanitize-r5900 */
- if (rn >= 90 && rn < 90 + 32)
- {
- GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
- return 8;
- }
- switch (rn)
- {
- case REGISTER_SA:
- SA = T2H_8(*(unsigned64*)memory);
- return 8;
- case 122: /* FIXME */
- LO1 = T2H_8(*(unsigned64*)memory);
- return 8;
- case 123: /* FIXME */
- HI1 = T2H_8(*(unsigned64*)memory);
- return 8;
- }
- /* end-sanitize-r5900 */
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- if (rn >= NUM_R5900_REGS)
- {
- rn = rn - NUM_R5900_REGS;
- if( rn < NUM_VU_REGS )
- {
- if (rn < NUM_VU_INTEGER_REGS)
- return write_vu_int_reg (&(vu0_device.state->regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
- {
- rn -= FIRST_VEC_REG;
- return write_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn&3,
- memory);
- }
- else switch (rn - NUM_VU_INTEGER_REGS)
- {
- case 0:
- return write_vu_special_reg (vu0_device.state, VU_REG_CIA,
- memory);
- case 1:
- return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
- memory);
- case 2: /* VU0 has no P register */
- return 4;
- case 3:
- return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
- memory);
- case 4:
- return write_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
- memory);
- default:
- return write_vu_acc_reg (&(vu0_device.state->regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
- }
- }
-
- rn = rn - NUM_VU_REGS;
-
- if (rn < NUM_VU_REGS)
+ if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ cpu->fpr_state[rn - FGRIDX] = fmt_uninterpreted;
+ if (cpu->register_widths[rn] == 32)
{
- if (rn < NUM_VU_INTEGER_REGS)
- return write_vu_int_reg (&(vu1_device.state->regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
+ if (length == 8)
{
- rn -= FIRST_VEC_REG;
- return write_vu_vec_reg (&(vu1_device.state->regs),
- rn >> 2, rn & 3, memory);
+ cpu->fgr[rn - FGRIDX] =
+ (unsigned32) T2H_8 (*(unsigned64*)memory);
+ return 8;
}
- else switch (rn - NUM_VU_INTEGER_REGS)
- {
- case 0:
- return write_vu_special_reg (vu1_device.state, VU_REG_CIA,
- memory);
- case 1:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MR,
- memory);
- case 2:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MP,
- memory);
- case 3:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MI,
- memory);
- case 4:
- return write_vu_misc_reg (&(vu1_device.state->regs), VU_REG_MQ,
- memory);
- default:
- return write_vu_acc_reg (&(vu1_device.state->regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
- }
- }
-
- rn -= NUM_VU_REGS; /* VIF0 registers are next */
-
- if (rn < NUM_VIF_REGS)
- {
- if (rn < NUM_VIF_REGS-1)
- return write_pke_reg (&pke0_device, rn, memory);
else
{
- sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
- return 0;
+ cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
+ return 4;
}
}
-
- rn -= NUM_VIF_REGS; /* VIF1 registers are last */
-
- if (rn < NUM_VIF_REGS)
+ else
{
- if (rn < NUM_VIF_REGS-1)
- return write_pke_reg (&pke1_device, rn, memory);
- else
- {
- sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
- return 0;
- }
+ cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
+ return 8;
}
-
- sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
- return 0;
}
-#endif
- /* end-sanitize-sky */
- if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ if (cpu->register_widths[rn] == 32)
{
- if (cpu->register_widths[rn] == 32)
+ if (length == 8)
{
- cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
- return 4;
+ cpu->registers[rn] =
+ (unsigned32) T2H_8 (*(unsigned64*)memory);
+ return 8;
}
else
{
- cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
- return 8;
+ cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
+ return 4;
}
}
-
- if (cpu->register_widths[rn] == 32)
- {
- cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
- return 4;
- }
else
{
cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
/* NOTE: gdb (the client) stores registers in target byte order
while the simulator uses host byte order */
#ifdef DEBUG
+#if 0 /* FIXME: doesn't compile */
sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
+#endif
#endif /* DEBUG */
if (cpu->register_widths[rn] == 0)
return 0;
}
- /* start-sanitize-r5900 */
- if (rn >= 90 && rn < 90 + 32)
- {
- *(unsigned64*)memory = GPR1[rn - 90];
- return 8;
- }
- switch (rn)
- {
- case REGISTER_SA:
- *((unsigned64*)memory) = H2T_8(SA);
- return 8;
- case 122: /* FIXME */
- *((unsigned64*)memory) = H2T_8(LO1);
- return 8;
- case 123: /* FIXME */
- *((unsigned64*)memory) = H2T_8(HI1);
- return 8;
- }
- /* end-sanitize-r5900 */
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- if (rn >= NUM_R5900_REGS)
- {
- rn = rn - NUM_R5900_REGS;
- if (rn < NUM_VU_REGS)
+ /* Any floating point register */
+ if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ {
+ if (cpu->register_widths[rn] == 32)
{
- if (rn < NUM_VU_INTEGER_REGS)
- return read_vu_int_reg (&(vu0_device.state->regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
+ if (length == 8)
{
- rn -= FIRST_VEC_REG;
- return read_vu_vec_reg (&(vu0_device.state->regs), rn>>2, rn & 3,
- memory);
+ *(unsigned64*)memory =
+ H2T_8 ((unsigned32) (cpu->fgr[rn - FGRIDX]));
+ return 8;
}
- else switch (rn - NUM_VU_INTEGER_REGS)
+ else
{
- case 0:
- return read_vu_special_reg(vu0_device.state, VU_REG_CIA, memory);
- case 1:
- return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MR,
- memory);
- case 2: /* VU0 has no P register */
- *((int *) memory) = 0;
+ *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
return 4;
- case 3:
- return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MI,
- memory);
- case 4:
- return read_vu_misc_reg (&(vu0_device.state->regs), VU_REG_MQ,
- memory);
- default:
- return read_vu_acc_reg (&(vu0_device.state->regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
- }
- }
-
- rn -= NUM_VU_REGS; /* VU1 registers are next */
-
- if (rn < NUM_VU_REGS)
- {
- if (rn < NUM_VU_INTEGER_REGS)
- return read_vu_int_reg (&(vu1_device.state->regs), rn, memory);
- else if (rn >= FIRST_VEC_REG)
- {
- rn -= FIRST_VEC_REG;
- return read_vu_vec_reg (&(vu1_device.state->regs),
- rn >> 2, rn & 3, memory);
}
- else switch (rn - NUM_VU_INTEGER_REGS)
- {
- case 0:
- return read_vu_special_reg(vu1_device.state, VU_REG_CIA, memory);
- case 1:
- return read_vu_misc_reg (&(vu1_device.state->regs),
- VU_REG_MR, memory);
- case 2:
- return read_vu_misc_reg (&(vu1_device.state->regs),
- VU_REG_MP, memory);
- case 3:
- return read_vu_misc_reg (&(vu1_device.state->regs),
- VU_REG_MI, memory);
- case 4:
- return read_vu_misc_reg (&(vu1_device.state->regs),
- VU_REG_MQ, memory);
- default:
- return read_vu_acc_reg (&(vu1_device.state->regs),
- rn - (NUM_VU_INTEGER_REGS + 5),
- memory);
- }
- }
-
- rn -= NUM_VU_REGS; /* VIF0 registers are next */
-
- if (rn < NUM_VIF_REGS)
- {
- if (rn < NUM_VIF_REGS-1)
- return read_pke_reg (&pke0_device, rn, memory);
- else
- return read_pke_pc (&pke0_device, memory);
}
-
- rn -= NUM_VIF_REGS; /* VIF1 registers are last */
-
- if (rn < NUM_VIF_REGS)
+ else
{
- if (rn < NUM_VIF_REGS-1)
- return read_pke_reg (&pke1_device, rn, memory);
- else
- return read_pke_pc (&pke1_device, memory);
+ *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
+ return 8;
}
-
- sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
}
-#endif
- /* end-sanitize-sky */
- /* Any floating point register */
- if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
+ if (cpu->register_widths[rn] == 32)
{
- if (cpu->register_widths[rn] == 32)
+ if (length == 8)
{
- *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
- return 4;
+ *(unsigned64*)memory =
+ H2T_8 ((unsigned32) (cpu->registers[rn]));
+ return 8;
}
else
{
- *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
- return 8;
+ *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
+ return 4;
}
}
-
- if (cpu->register_widths[rn] == 32)
- {
- *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
- return 4;
- }
else
{
*(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
{
#ifdef DEBUG
+#if 0 /* FIXME: doesn't compile */
printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
pr_addr(PC));
+#endif
#endif /* DEBUG */
ColdReset(sd);
/* Read a null terminated string from memory, return in a buffer */
static char *
-fetch_str (sd, addr)
- SIM_DESC sd;
- address_word addr;
+fetch_str (SIM_DESC sd,
+ address_word addr)
{
char *buf;
int nr = 0;
return buf;
}
+
+/* Implements the "sim firmware" command:
+ sim firmware NAME[@ADDRESS] --- emulate ROM monitor named NAME.
+ NAME can be idt, pmon, or lsipmon. If omitted, ADDRESS
+ defaults to the normal address for that monitor.
+ sim firmware none --- don't emulate any ROM monitor. Useful
+ if you need a clean address space. */
+static SIM_RC
+sim_firmware_command (SIM_DESC sd, char *arg)
+{
+ int address_present = 0;
+ SIM_ADDR address;
+
+ /* Signal occurrence of this option. */
+ firmware_option_p = 1;
+
+ /* Parse out the address, if present. */
+ {
+ char *p = strchr (arg, '@');
+ if (p)
+ {
+ char *q;
+ address_present = 1;
+ p ++; /* skip over @ */
+
+ address = strtoul (p, &q, 0);
+ if (*q != '\0')
+ {
+ sim_io_printf (sd, "Invalid address given to the"
+ "`sim firmware NAME@ADDRESS' command: %s\n",
+ p);
+ return SIM_RC_FAIL;
+ }
+ }
+ else
+ address_present = 0;
+ }
+
+ if (! strncmp (arg, "idt", 3))
+ {
+ idt_monitor_base = address_present ? address : 0xBFC00000;
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = 0;
+ }
+ else if (! strncmp (arg, "pmon", 4))
+ {
+ /* pmon uses indirect calls. Hook into implied idt. */
+ pmon_monitor_base = address_present ? address : 0xBFC00500;
+ idt_monitor_base = pmon_monitor_base - 0x500;
+ lsipmon_monitor_base = 0;
+ }
+ else if (! strncmp (arg, "lsipmon", 7))
+ {
+ /* lsipmon uses indirect calls. Hook into implied idt. */
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = address_present ? address : 0xBFC00200;
+ idt_monitor_base = lsipmon_monitor_base - 0x200;
+ }
+ else if (! strncmp (arg, "none", 4))
+ {
+ if (address_present)
+ {
+ sim_io_printf (sd,
+ "The `sim firmware none' command does "
+ "not take an `ADDRESS' argument.\n");
+ return SIM_RC_FAIL;
+ }
+ idt_monitor_base = 0;
+ pmon_monitor_base = 0;
+ lsipmon_monitor_base = 0;
+ }
+ else
+ {
+ sim_io_printf (sd, "\
+Unrecognized name given to the `sim firmware NAME' command: %s\n\
+Recognized firmware names are: `idt', `pmon', `lsipmon', and `none'.\n",
+ arg);
+ return SIM_RC_FAIL;
+ }
+
+ return SIM_RC_OK;
+}
+
+
+
/* Simple monitor interface (currently setup for the IDT and PMON monitors) */
-static void
+void
sim_monitor (SIM_DESC sd,
sim_cpu *cpu,
address_word cia,
case 11: /* char inbyte(void) */
{
char tmp;
+ /* ensure that all output has gone... */
+ sim_io_flush_stdout (sd);
if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
{
sim_io_error(sd,"Invalid return from character read");
int width = 0, trunc = 0, haddot = 0, longlong = 0;
while (sim_read (sd, s++, &c, 1) && c != '\0')
{
- if (strchr ("dobxXulscefg%", s))
+ if (strchr ("dobxXulscefg%", c))
break;
else if (c == '-')
fmt = FMT_LJUST;
uword64 vaddr)
{
if ((vaddr & 3) != 0)
- SignalExceptionAddressLoad ();
+ {
+ SIM_CORE_SIGNAL (SD, cpu, cia, read_map, AccessLength_WORD+1, vaddr, read_transfer, sim_core_unaligned_signal);
+ }
else
{
address_word paddr;
{
sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
/* RESET: Fixed PC address: */
- PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
+ PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
/* The reset vector address is in the unmapped, uncached memory space. */
SR &= ~(status_SR | status_TS | status_RP);
}
}
-unsigned16
-ifetch16 (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- address_word vaddr)
-{
- /* Copy the action of the LW instruction */
- address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- unsigned64 value;
- address_word paddr;
- unsigned16 instruction;
- unsigned byte;
- int cca;
- AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
- return instruction;
-}
+
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
address_word cia,
int exception,...)
{
- int vector;
+ /* int vector; */
#ifdef DEBUG
sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
/* Ensure that any active atomic read/modify/write operation will fail: */
LLBIT = 0;
- switch (exception) {
- /* TODO: For testing purposes I have been ignoring TRAPs. In
- reality we should either simulate them, or allow the user to
- ignore them at run-time.
- Same for SYSCALL */
- case Trap :
- sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
- break;
-
- case SystemCall :
- {
- va_list ap;
- unsigned int instruction;
- unsigned int code;
-
- va_start(ap,exception);
- instruction = va_arg(ap,unsigned int);
- va_end(ap);
+ /* Save registers before interrupt dispatching */
+#ifdef SIM_CPU_EXCEPTION_TRIGGER
+ SIM_CPU_EXCEPTION_TRIGGER(sd, cpu, cia);
+#endif
- code = (instruction >> 6) & 0xFFFFF;
-
- sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
- code, pr_addr(cia));
- }
- break;
+ switch (exception) {
case DebugBreakPoint :
if (! (Debug & Debug_DM))
sim_engine_restart (sd, NULL, NULL, NULL_CIA);
}
/* else fall through to normal exception processing */
- sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
+ sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
}
- case BreakPoint:
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
-#endif /* DEBUG */
- /* Keep a copy of the current A0 in-case this is the program exit
- breakpoint: */
- {
- va_list ap;
- unsigned int instruction;
- va_start(ap,exception);
- instruction = va_arg(ap,unsigned int);
- va_end(ap);
- /* Check for our special terminating BREAK: */
- if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
- sim_engine_halt (SD, CPU, NULL, cia,
- sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
- }
- }
- if (STATE & simDELAYSLOT)
- PC = cia - 4; /* reference the branch instruction */
- else
- PC = cia;
- sim_engine_halt (SD, CPU, NULL, cia,
- sim_stopped, SIM_SIGTRAP);
-
default:
/* Store exception code into current exception id variable (used
by exit code): */
/* TODO: If not simulating exceptions then stop the simulator
execution. At the moment we always stop the simulation. */
+#ifdef SUBTARGET_R3900
+ /* update interrupt-related registers */
+
+ /* insert exception code in bits 6:2 */
+ CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
+ /* shift IE/KU history bits left */
+ SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
+
+ if (STATE & simDELAYSLOT)
+ {
+ STATE &= ~simDELAYSLOT;
+ CAUSE |= cause_BD;
+ EPC = (cia - 4); /* reference the branch instruction */
+ }
+ else
+ EPC = cia;
+
+ if (SR & status_BEV)
+ PC = (signed)0xBFC00000 + 0x180;
+ else
+ PC = (signed)0x80000000 + 0x080;
+#else
/* See figure 5-17 for an outline of the code below */
if (! (SR & status_EXL))
{
else
EPC = cia;
/* FIXME: TLB et.al. */
- vector = 0x180;
+ /* vector = 0x180; */
}
else
{
CAUSE = (exception << 2);
- vector = 0x180;
+ /* vector = 0x180; */
}
SR |= status_EXL;
/* Store exception code into current exception id variable (used
by exit code): */
+
if (SR & status_BEV)
PC = (signed)0xBFC00200 + 0x180;
else
PC = (signed)0x80000000 + 0x180;
+#endif
switch ((CAUSE >> 2) & 0x1F)
{
/* Interrupts arrive during event processing, no need to
restart */
return;
-
+
+ case NMIReset:
+ /* Ditto */
+#ifdef SUBTARGET_3900
+ /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
+ PC = (signed)0xBFC00000;
+#endif SUBTARGET_3900
+ return;
+
case TLBModification:
case TLBLoad:
case TLBStore:
case InstructionFetch:
case DataReference:
/* The following is so that the simulator will continue from the
- exception address on breakpoint operations. */
- PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ exception handler address. */
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGBUS);
case ReservedInstruction:
case CoProcessorUnusable:
PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGILL);
case IntegerOverflow:
case FPE:
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGFPE);
+
+ case BreakPoint:
+ sim_engine_halt (SD, CPU, NULL, PC, sim_stopped, SIM_SIGTRAP);
+ break;
+ case SystemCall:
case Trap:
+ sim_engine_restart (SD, CPU, NULL, PC);
+ break;
+
case Watch:
- case SystemCall:
PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGTRAP);
- case BreakPoint:
- PC = EPC;
- sim_engine_abort (SD, CPU, NULL_CIA,
- "FATAL: Should not encounter a breakpoint\n");
-
default : /* Unknown internal exception */
PC = EPC;
- sim_engine_halt (SD, CPU, NULL, NULL_CIA,
+ sim_engine_halt (SD, CPU, NULL, PC,
sim_stopped, SIM_SIGABRT);
}
return;
}
+
+
#if defined(WARN_RESULT)
/* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
/* This function indicates that the result of the operation is
#define FPINF_SINGLE (0x7F800000)
#define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
-#if 1 /* def DEBUG */
#define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
-#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
-#endif /* DEBUG */
+#define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : (((v) == fmt_uninterpreted_32) ? "<uninterpreted_32>" : (((v) == fmt_uninterpreted_64) ? "<uninterpreted_64>" : "<format error>"))))))))
uword64
value_fpr (SIM_DESC sd,
case fmt_double:
case fmt_long:
if ((fpr & 1) == 0) { /* even registers only */
+#ifdef DEBUG
+ printf("DBG: ValueFPR: FGR[%d] = %s, FGR[%d] = %s\n",
+ fpr+1, pr_uword64( (uword64) FGR[fpr+1] ),
+ fpr, pr_uword64( (uword64) FGR[fpr] ));
+#endif
value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
} else {
SignalException(ReservedInstruction,0);
SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
#ifdef DEBUG
- printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
+ printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
#endif /* DEBUG */
return(value);
int err = 0;
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
+ printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d,\n",fpr,DOFMT(fmt),pr_uword64(value),pr_addr(cia),SizeFGR());
#endif /* DEBUG */
if (SizeFGR() == 64) {
SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
#ifdef DEBUG
- printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
+ printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_uword64(FGR[fpr]),DOFMT(fmt));
#endif /* DEBUG */
return;
unsigned64 result64;
#ifdef DEBUG
+#if 0 /* FIXME: doesn't compile */
printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
+#endif
#endif /* DEBUG */
switch (rm)
/*-- co-processor support routines ------------------------------------------*/
static int UNUSED
-CoProcPresent(coproc_number)
- unsigned int coproc_number;
+CoProcPresent(unsigned int coproc_number)
{
/* Return TRUE if simulator provides a model for the given co-processor number */
return(0);
int coproc_reg,
uword64 memword)
{
+
+#ifdef DEBUG
+ printf("DBG: COP_LD: coproc_num = %d, coproc_reg = %d, value = 0x%s : PC = 0x%s\n", coproc_num, coproc_reg, pr_uword64(memword), pr_addr(cia) );
+#endif
+
switch (coproc_num) {
case 1:
if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
}
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-void
-cop_lq (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int coproc_num,
- int coproc_reg,
- unsigned128 memword)
-{
- switch (coproc_num)
- {
- case 2:
- /* XXX COP2 */
- break;
-
- default:
- sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
- coproc_num,coproc_reg,pr_addr(cia));
- break;
- }
-
- return;
-}
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
unsigned int
}
-/* start-sanitize-sky */
-#ifdef TARGET_SKY
-unsigned128
-cop_sq (SIM_DESC sd,
- sim_cpu *cpu,
- address_word cia,
- int coproc_num,
- int coproc_reg)
-{
- unsigned128 value = U16_8(0, 0);
- switch (coproc_num)
- {
- case 2:
- /* XXX COP2 */
- break;
-
- default:
- sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
- coproc_num,coproc_reg,pr_addr(cia));
- break;
- }
-
- return(value);
-}
-#endif /* TARGET_SKY */
-/* end-sanitize-sky */
void
case 0: /* standard CPU control and cache registers */
{
int code = ((instruction >> 21) & 0x1F);
+ int rt = ((instruction >> 16) & 0x1F);
+ int rd = ((instruction >> 11) & 0x1F);
+ int tail = instruction & 0x3ff;
/* R4000 Users Manual (second edition) lists the following CP0
instructions:
+ CODE><-RT><RD-><--TAIL--->
DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
ERET Exception return (VR4100 = 01000010000000000000000000011000)
*/
- if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
+ if (((code == 0x00) || (code == 0x04) /* MFC0 / MTC0 */
+ || (code == 0x01) || (code == 0x05)) /* DMFC0 / DMTC0 */
+ && tail == 0)
{
- int rt = ((instruction >> 16) & 0x1F);
- int rd = ((instruction >> 11) & 0x1F);
+ /* Clear double/single coprocessor move bit. */
+ code &= ~1;
+
+ /* M[TF]C0 (32 bits) | DM[TF]C0 (64 bits) */
switch (rd) /* NOTEs: Standard CP0 registers */
{
/* 10 = EntryHi R4000 VR4100 VR4300 */
/* 11 = Compare R4000 VR4100 VR4300 */
/* 12 = SR R4000 VR4100 VR4300 */
+#ifdef SUBTARGET_R3900
+ case 3:
+ /* 3 = Config R3900 */
+ case 7:
+ /* 7 = Cache R3900 */
+ case 15:
+ /* 15 = PRID R3900 */
+
+ /* ignore */
+ break;
+
+ case 8:
+ /* 8 = BadVAddr R4000 VR4100 VR4300 */
+ if (code == 0x00)
+ GPR[rt] = COP0_BADVADDR;
+ else
+ COP0_BADVADDR = GPR[rt];
+ break;
+
+#endif /* SUBTARGET_R3900 */
case 12:
if (code == 0x00)
GPR[rt] = SR;
CAUSE = GPR[rt];
break;
/* 14 = EPC R4000 VR4100 VR4300 */
+ case 14:
+ if (code == 0x00)
+ GPR[rt] = (signed_word) (signed_address) EPC;
+ else
+ EPC = GPR[rt];
+ break;
/* 15 = PRId R4000 VR4100 VR4300 */
#ifdef SUBTARGET_R3900
/* 16 = Debug */
/* CPR[0,rd] = GPR[rt]; */
default:
if (code == 0x00)
- sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ GPR[rt] = (signed_word) (signed32) COP0_GPR[rd];
+ else
+ COP0_GPR[rd] = GPR[rt];
+#if 0
+ if (code == 0x00)
+ sim_io_printf(sd,"Warning: MFC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
else
- sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
+ sim_io_printf(sd,"Warning: MTC0 %d,%d ignored, PC=%08x (architecture specific)\n",rt,rd, (unsigned)cia);
+#endif
}
}
- else if (code == 0x10 && (instruction & 0x3f) == 0x18)
+ else if (code == 0x10 && (tail & 0x3f) == 0x18)
{
/* ERET */
if (SR & status_ERL)
SR &= ~status_EXL;
}
}
- else if (code == 0x10 && (instruction & 0x3f) == 0x10)
+ else if (code == 0x10 && (tail & 0x3f) == 0x10)
{
/* RFE */
+#ifdef SUBTARGET_R3900
+ /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
+
+ /* shift IE/KU history bits right */
+ SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
+
+ /* TODO: CACHE register */
+#endif /* SUBTARGET_R3900 */
}
- else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
+ else if (code == 0x10 && (tail & 0x3f) == 0x1F)
{
/* DERET */
Debug &= ~Debug_DM;
}
break;
- case 2: /* undefined co-processor */
+ case 2: /* co-processor 2 */
{
int handle = 0;
- /* start-sanitize-sky */
-#ifdef TARGET_SKY
- /* On the R5900, this refers to a "VU" vector co-processor. */
-
- int i_25_21 = (instruction >> 21) & 0x1f;
- int i_20_16 = (instruction >> 16) & 0x1f;
- int i_15_11 = (instruction >> 11) & 0x1f;
- int i_15_0 = instruction & 0xffff;
- int i_10_1 = (instruction >> 1) & 0x3ff;
- int i_5_0 = instruction & 0x03f;
- int interlock = instruction & 0x01;
- int co = (instruction >> 25) & 0x01;
- /* setup for semantic.c-like actions below */
- typedef unsigned_4 instruction_word;
- int CIA = cia;
- int NIA = cia + 4;
- sim_cpu* CPU_ = cpu;
-
- handle = 1;
-
- /* test COP2 usability */
- if(! (SR & status_CU2))
- {
- SignalException(CoProcessorUnusable,instruction);
- /* NOTREACHED */
- }
-
- /* classify & execute basic COP2 instructions */
- if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- }
- else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- else NULLIFY_NEXT_INSTRUCTION();
- }
- else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- }
- else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
- {
- address_word offset = EXTEND16(i_15_0) << 2;
- if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
- else NULLIFY_NEXT_INSTRUCTION();
- }
- else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
- (i_25_21 == 0x01)) /* QMFC2 */
- {
- int rt = i_20_16;
- int id = i_15_11;
- address_word vu_cr_addr; /* VU control register address */
- unsigned_4 data;
-
- /* interlock checking */
- if(vu0_busy_in_macro_mode()) /* busy in macro mode */
- {
- /* interlock bit invalid here */
- if(interlock)
- ; /* XXX: warning */
-
- /* always check data hazard */
- while(vu0_macro_hazard_check(id))
- vu0_issue(sd);
- }
- else if(vu0_busy_in_micro_mode() && interlock)
- {
- while(vu0_busy_in_micro_mode())
- vu0_issue(sd);
- }
-
- /* compute VU register address */
- if(i_25_21 == 0x01) /* QMFC2 */
- vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
- else /* CFC2 */
- vu_cr_addr = VU0_MST + (id * 16);
-
- /* read or write word */
- data = sim_core_read_aligned_4(cpu, cia, read_map, vu_cr_addr);
- GPR[rt] = EXTEND64(data);
- }
- else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
- (i_25_21 == 0x05)) /* QMTC2 */
- {
- int rt = i_20_16;
- int id = i_15_11;
- address_word vu_cr_addr; /* VU control register address */
- unsigned_4 data;
-
- /* interlock checking */
- if(vu0_busy_in_macro_mode()) /* busy in macro mode */
- {
- /* interlock bit invalid here */
- if(interlock)
- ; /* XXX: warning */
-
- /* always check data hazard */
- while(vu0_macro_hazard_check(id))
- vu0_issue(sd);
- }
- else if(vu0_busy_in_micro_mode())
- {
- if(interlock)
- {
- while(! vu0_micro_interlock_released())
- vu0_issue(sd);
- }
- }
-
- /* compute VU register address */
- if(i_25_21 == 0x05) /* QMTC2 */
- vu_cr_addr = VU0_REGISTER_WINDOW_START + (id * 16);
- else /* CTC2 */
- vu_cr_addr = VU0_MST + (id * 16);
-
- data = GPR[rt];
- sim_core_write_aligned_4(cpu, cia, write_map, vu_cr_addr, data);
- }
- else if( 0 /* XXX: ... upper ... */)
- {
- unsigned_4 vu_upper, vu_lower;
- vu_upper =
- 0x00000000 | /* bits 31 .. 25 */
- instruction & 0x01ffffff; /* bits 24 .. 0 */
- vu_lower = 0x8000033c; /* NOP */
-
- while(vu0_busy_in_micro_mode())
- vu0_issue(sd);
-
- vu0_macro_issue(vu_upper, vu_lower);
- }
- else if( 0 /* XXX: ... lower ... */)
- {
- unsigned_4 vu_upper, vu_lower;
- vu_upper = 0x000002ff; /* NOP */
- vu_lower =
- 0x10000000 | /* bits 31 .. 25 */
- instruction & 0x01ffffff; /* bits 24 .. 0 */
-
- while(vu0_busy_in_micro_mode())
- vu0_issue(sd);
-
- vu0_macro_issue(vu_upper, vu_lower);
- }
- /* XXX */
- /* ... other COP2 instructions ... */
- else
- {
- SignalException(ReservedInstruction, instruction);
- /* NOTREACHED */
- }
-
- /* cleanup for semantic.c-like actions above */
- PC = NIA;
-
-#endif /* TARGET_SKY */
- /* end-sanitize-sky */
if(! handle)
{
- sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
+ sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
instruction,pr_addr(cia));
}
}
}
-/*-- instruction simulation -------------------------------------------------*/
-
-/* When the IGEN simulator is being built, the function below is be
- replaced by a generated version. However, WITH_IGEN == 2 indicates
- that the fubction below should be compiled but under a different
- name (to allow backward compatibility) */
-
-#if (WITH_IGEN != 1)
-#if (WITH_IGEN > 1)
-void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
-void
-old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
-#else
-void
-sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
-#endif
- SIM_DESC sd;
- int next_cpu_nr; /* ignore */
- int nr_cpus; /* ignore */
- int siggnal; /* ignore */
-{
- sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
-#if !defined(FASTSIM)
- unsigned int pipeline_count = 1;
-#endif
-
-#ifdef DEBUG
- if (STATE_MEMORY (sd) == NULL) {
- printf("DBG: simulate() entered with no memory\n");
- exit(1);
- }
-#endif /* DEBUG */
-
-#if 0 /* Disabled to check that everything works OK */
- /* The VR4300 seems to sign-extend the PC on its first
- access. However, this may just be because it is currently
- configured in 32bit mode. However... */
- PC = SIGNEXTEND(PC,32);
-#endif
-
- /* main controlling loop */
- while (1) {
- /* vaddr is slowly being replaced with cia - current instruction
- address */
- address_word cia = (uword64)PC;
- address_word vaddr = cia;
- address_word paddr;
- int cca;
- unsigned int instruction; /* uword64? what's this used for? FIXME! */
-
-#ifdef DEBUG
- {
- printf("DBG: state = 0x%08X :",state);
- if (state & simHALTEX) printf(" simHALTEX");
- if (state & simHALTIN) printf(" simHALTIN");
- printf("\n");
- }
-#endif /* DEBUG */
-
- DSSTATE = (STATE & simDELAYSLOT);
-#ifdef DEBUG
- if (dsstate)
- sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
-#endif /* DEBUG */
-
- /* Fetch the next instruction from the simulator memory: */
- if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
- if ((vaddr & 1) == 0) {
- /* Copy the action of the LW instruction */
- unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
- unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
- uword64 value;
- unsigned int byte;
- paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
- LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
- byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
- instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
- } else {
- /* Copy the action of the LH instruction */
- unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
- unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
- uword64 value;
- unsigned int byte;
- paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
- | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
- LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
- paddr & ~ (uword64) 1,
- vaddr, isINSTRUCTION, isREAL);
- byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
- instruction = ((value >> (8 * byte)) & 0xFFFF);
- }
- } else {
- fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
- exit(1);
- }
-
-#ifdef DEBUG
- sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
-#endif /* DEBUG */
-
- /* This is required by exception processing, to ensure that we can
- cope with exceptions in the delay slots of branches that may
- already have changed the PC. */
- if ((vaddr & 1) == 0)
- PC += 4; /* increment ready for the next fetch */
- else
- PC += 2;
- /* NOTE: If we perform a delay slot change to the PC, this
- increment is not requuired. However, it would make the
- simulator more complicated to try and avoid this small hit. */
-
- /* Currently this code provides a simple model. For more
- complicated models we could perform exception status checks at
- this point, and set the simSTOP state as required. This could
- also include processing any hardware interrupts raised by any
- I/O model attached to the simulator context.
-
- Support for "asynchronous" I/O events within the simulated world
- could be providing by managing a counter, and calling a I/O
- specific handler when a particular threshold is reached. On most
- architectures a decrement and check for zero operation is
- usually quicker than an increment and compare. However, the
- process of managing a known value decrement to zero, is higher
- than the cost of using an explicit value UINT_MAX into the
- future. Which system is used will depend on how complicated the
- I/O model is, and how much it is likely to affect the simulator
- bandwidth.
-
- If events need to be scheduled further in the future than
- UINT_MAX event ticks, then the I/O model should just provide its
- own counter, triggered from the event system. */
-
- /* MIPS pipeline ticks. To allow for future support where the
- pipeline hit of individual instructions is known, this control
- loop manages a "pipeline_count" variable. It is initialised to
- 1 (one), and will only be changed by the simulator engine when
- executing an instruction. If the engine does not have access to
- pipeline cycle count information then all instructions will be
- treated as using a single cycle. NOTE: A standard system is not
- provided by the default simulator because different MIPS
- architectures have different cycle counts for the same
- instructions.
-
- [NOTE: pipeline_count has been replaced the event queue] */
-
- /* shuffle the floating point status pipeline state */
- ENGINE_ISSUE_PREFIX_HOOK();
-
-/* NOTE: For multi-context simulation environments the "instruction"
- variable should be local to this routine. */
-
-/* Shorthand accesses for engine. Note: If we wanted to use global
- variables (and a single-threaded simulator engine), then we can
- create the actual variables with these names. */
-
- if (!(STATE & simSKIPNEXT)) {
- /* Include the simulator engine */
-#include "oengine.c"
-#if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
-#error "Mismatch between run-time simulator code and simulation engine"
-#endif
-#if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
-#error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
-#endif
-#if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
-#error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
-#endif
-
-#if defined(WARN_LOHI)
- /* Decrement the HI/LO validity ticks */
- if (HIACCESS > 0)
- HIACCESS--;
- if (LOACCESS > 0)
- LOACCESS--;
- /* start-sanitize-r5900 */
- if (HI1ACCESS > 0)
- HI1ACCESS--;
- if (LO1ACCESS > 0)
- LO1ACCESS--;
- /* end-sanitize-r5900 */
-#endif /* WARN_LOHI */
-
- /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
- should check for it being changed. It is better doing it here,
- than within the simulator, since it will help keep the simulator
- small. */
- if (ZERO != 0) {
-#if defined(WARN_ZERO)
- sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
-#endif /* WARN_ZERO */
- ZERO = 0; /* reset back to zero before next instruction */
- }
- } else /* simSKIPNEXT check */
- STATE &= ~simSKIPNEXT;
-
- /* If the delay slot was active before the instruction is
- executed, then update the PC to its new value: */
- if (DSSTATE) {
-#ifdef DEBUG
- printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
-#endif /* DEBUG */
- PC = DSPC;
- CANCELDELAYSLOT();
- }
-
- if (MIPSISA < 4)
- PENDING_TICK();
-
-#if !defined(FASTSIM)
- if (sim_events_tickn (sd, pipeline_count))
- {
- /* cpu->cia = cia; */
- sim_events_process (sd);
- }
-#else
- if (sim_events_tick (sd))
- {
- /* cpu->cia = cia; */
- sim_events_process (sd);
- }
-#endif /* FASTSIM */
- }
-}
-#endif
-
-
/* This code copied from gdb's utils.c. Would like to share this code,
but don't know of a common place where both could get to it. */
#define NUMCELLS 16
#define CELLSIZE 32
static char*
-get_cell()
+get_cell (void)
{
static char buf[NUMCELLS][CELLSIZE];
static int cell=0;
}
+void
+mips_core_signal (SIM_DESC sd,
+ sim_cpu *cpu,
+ sim_cia cia,
+ unsigned map,
+ int nr_bytes,
+ address_word addr,
+ transfer_type transfer,
+ sim_core_signals sig)
+{
+ const char *copy = (transfer == read_transfer ? "read" : "write");
+ address_word ip = CIA_ADDR (cia);
+
+ switch (sig)
+ {
+ case sim_core_unmapped_signal:
+ sim_io_eprintf (sd, "mips-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
+ nr_bytes, copy,
+ (unsigned long) addr, (unsigned long) ip);
+ COP0_BADVADDR = addr;
+ SignalExceptionDataReference();
+ break;
+
+ case sim_core_unaligned_signal:
+ sim_io_eprintf (sd, "mips-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
+ nr_bytes, copy,
+ (unsigned long) addr, (unsigned long) ip);
+ COP0_BADVADDR = addr;
+ if(transfer == read_transfer)
+ SignalExceptionAddressLoad();
+ else
+ SignalExceptionAddressStore();
+ break;
+
+ default:
+ sim_engine_abort (sd, cpu, cia,
+ "mips_core_signal - internal error - bad switch");
+ }
+}
+
+
+void
+mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word cia)
+{
+ ASSERT(cpu != NULL);
+
+ if(cpu->exc_suspended > 0)
+ sim_io_eprintf(sd, "Warning, nested exception triggered (%d)\n", cpu->exc_suspended);
+
+ PC = cia;
+ memcpy(cpu->exc_trigger_registers, cpu->registers, sizeof(cpu->exc_trigger_registers));
+ cpu->exc_suspended = 0;
+}
+
+void
+mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception)
+{
+ ASSERT(cpu != NULL);
+
+ if(cpu->exc_suspended > 0)
+ sim_io_eprintf(sd, "Warning, nested exception signal (%d then %d)\n",
+ cpu->exc_suspended, exception);
+
+ memcpy(cpu->exc_suspend_registers, cpu->registers, sizeof(cpu->exc_suspend_registers));
+ memcpy(cpu->registers, cpu->exc_trigger_registers, sizeof(cpu->registers));
+ cpu->exc_suspended = exception;
+}
+
+void
+mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception)
+{
+ ASSERT(cpu != NULL);
+
+ if(exception == 0 && cpu->exc_suspended > 0)
+ {
+ /* warn not for breakpoints */
+ if(cpu->exc_suspended != sim_signal_to_host(sd, SIM_SIGTRAP))
+ sim_io_eprintf(sd, "Warning, resuming but ignoring pending exception signal (%d)\n",
+ cpu->exc_suspended);
+ }
+ else if(exception != 0 && cpu->exc_suspended > 0)
+ {
+ if(exception != cpu->exc_suspended)
+ sim_io_eprintf(sd, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
+ cpu->exc_suspended, exception);
+
+ memcpy(cpu->registers, cpu->exc_suspend_registers, sizeof(cpu->registers));
+ }
+ else if(exception != 0 && cpu->exc_suspended == 0)
+ {
+ sim_io_eprintf(sd, "Warning, ignoring spontanous exception signal (%d)\n", exception);
+ }
+ cpu->exc_suspended = 0;
+}
+
/*---------------------------------------------------------------------------*/
/*> EOF interp.c <*/
projects / thirdparty / binutils-gdb.git / blobdiff