import gdb-1999-09-08 snapshot

[thirdparty/binutils-gdb.git] / sim / mips / mips.igen

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index 7b4102c7daac63354e9fdf10826bfb93e5896e77..17748febcfc40a0c266b05c60efa6faaa7ea49c2 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1,5 +1,9 @@
 // -*- C -*-
 //
+// In mips.igen, the semantics for many of the instructions were created
+// using code generated by gencode.  Those semantic segments could be
+// greatly simplified.
+//
 //    <insn> ::=
 //        <insn-word> { "+" <insn-word> }
 //        ":" <format-name>
@@ -36,20 +40,8 @@
 :model:::mipsIII:mips4000:
 :model:::mipsIV:mips8000:
 :model:::mips16:mips16:
-// start-sanitize-r5900
-:model:::r5900:mips5900:
-// end-sanitize-r5900
 :model:::r3900:mips3900:
-// start-sanitize-tx19
-:model:::tx19:tx19:
-// end-sanitize-tx19
-// start-sanitize-vr4320
-:model:::vr4320:mips4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-:model:::vr5400:mips5400:
-:model:::mdmx:mdmx:
-// end-sanitize-vr5400
+:model:::vr4100:mips4100:
 :model:::vr5000:mips5000:
 
 
@@ -84,6 +76,7 @@
   CIA = CIA + 4; /* NOTE not mips16 */
   STATE |= simDELAYSLOT;
   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
+  ENGINE_ISSUE_PREFIX_HOOK();
   idecode_issue (CPU_, delay_insn, (CIA));
   STATE &= ~simDELAYSLOT;
   return target;
@@ -96,6 +89,133 @@
   return CIA + 8;
 }
 
+// Helper:
+// 
+// Check that an access to a HI/LO register meets timing requirements
+//
+// The following requirements exist:
+//
+//   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
+//   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
+//   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
+//      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
+//
+
+:function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
+{
+  if (history->mf.timestamp + 3 > time)
+    {
+      sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
+                       itable[MY_INDEX].name,
+                       new, (long) CIA,
+                       (long) history->mf.cia);      
+      return 0;
+    }
+  return 1;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+{
+  signed64 time = sim_events_time (SD);
+  int ok = check_mf_cycles (SD_, history, time, "MT");
+  history->mt.timestamp = time;
+  history->mt.cia = CIA;
+  return ok;
+}
+
+:function:::int:check_mt_hilo:hilo_history *history
+*r3900:
+{
+  signed64 time = sim_events_time (SD);
+  history->mt.timestamp = time;
+  history->mt.cia = CIA;
+  return 1;
+}
+
+
+:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  signed64 time = sim_events_time (SD);
+  int ok = 1;
+  if (peer != NULL
+      && peer->mt.timestamp > history->op.timestamp
+      && history->mt.timestamp < history->op.timestamp
+      && ! (history->mf.timestamp > history->op.timestamp
+           && history->mf.timestamp < peer->mt.timestamp)
+      && ! (peer->mf.timestamp > history->op.timestamp
+           && peer->mf.timestamp < peer->mt.timestamp))
+    {
+      /* The peer has been written to since the last OP yet we have
+         not */
+      sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
+                       itable[MY_INDEX].name,
+                       (long) CIA,
+                       (long) history->op.cia,
+                       (long) peer->mt.cia);      
+      ok = 0;
+    }
+  history->mf.timestamp = time;
+  history->mf.cia = CIA;
+  return ok;
+}
+
+
+
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+{
+  signed64 time = sim_events_time (SD);
+  int ok = (check_mf_cycles (SD_, hi, time, "OP")
+           && check_mf_cycles (SD_, lo, time, "OP"));
+  hi->op.timestamp = time;
+  lo->op.timestamp = time;
+  hi->op.cia = CIA;
+  lo->op.cia = CIA;
+  return ok;
+}
+
+// The r3900 mult and multu insns _can_ be exectuted immediatly after
+// a mf{hi,lo}
+:function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
+*r3900:
+{
+  /* FIXME: could record the fact that a stall occured if we want */
+  signed64 time = sim_events_time (SD);
+  hi->op.timestamp = time;
+  lo->op.timestamp = time;
+  hi->op.cia = CIA;
+  lo->op.cia = CIA;
+  return 1;
+}
+
+
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+*r3900:
+{
+  signed64 time = sim_events_time (SD);
+  int ok = (check_mf_cycles (SD_, hi, time, "OP")
+           && check_mf_cycles (SD_, lo, time, "OP"));
+  hi->op.timestamp = time;
+  lo->op.timestamp = time;
+  hi->op.cia = CIA;
+  lo->op.cia = CIA;
+  return ok;
+}
+
+
+
 
 
 //
@@ -109,24 +229,17 @@
 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 "add r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  ALU32_BEGIN (GPR[RS]);
-  ALU32_ADD (GPR[RT]);
-  ALU32_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU32_BEGIN (GPR[RS]);
+    ALU32_ADD (GPR[RT]);
+    ALU32_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -134,24 +247,17 @@
 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 "addi r<RT>, r<RS>, IMMEDIATE"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  ALU32_BEGIN (GPR[RS]);
-  ALU32_ADD (EXTEND16 (IMMEDIATE));
-  ALU32_END (GPR[RT]);
+  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+  {
+    ALU32_BEGIN (GPR[RS]);
+    ALU32_ADD (EXTEND16 (IMMEDIATE));
+    ALU32_END (GPR[RT]);
+  }
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
@@ -166,20 +272,9 @@
 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_addiu (SD_, RS, RT, IMMEDIATE);
 }
@@ -196,20 +291,9 @@
 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 "addu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_addu (SD_, RS, RT, RD);
 }
@@ -226,20 +310,9 @@
 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 "and r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_and (SD_, RS, RT, RD);
 }
@@ -249,22 +322,13 @@
 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 "and r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
+  TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
   GPR[RT] = GPR[RS] & IMMEDIATE;
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
@@ -272,24 +336,17 @@
 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 "beq r<RS>, r<RT>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -299,24 +356,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -326,24 +376,17 @@
 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 "bgez r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -351,25 +394,18 @@
 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 "bgezal r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -379,27 +415,20 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -411,24 +440,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -438,24 +460,17 @@
 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 "bgtz r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] > 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -465,26 +480,19 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] > 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -494,26 +502,19 @@
 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 "blez r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] <= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -523,24 +524,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] <= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -550,24 +544,17 @@
 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 "bltz r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -575,27 +562,20 @@
 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 "bltzal r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -605,25 +585,18 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -635,26 +608,19 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -664,24 +630,17 @@
 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 "bne r<RS>, r<RT>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -691,24 +650,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -718,39 +670,38 @@
 000000,20.CODE,001101:SPECIAL:32::BREAK
 "break"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  SignalException(BreakPoint, instruction_0);
+  /* Check for some break instruction which are reserved for use by the simulator.  */
+  unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
+  if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
+      break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+    {
+      sim_engine_halt (SD, CPU, NULL, cia,
+                       sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+    }
+  else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
+           break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+    {
+      if (STATE & simDELAYSLOT)
+        PC = cia - 4; /* reference the branch instruction */
+      else
+        PC = cia;
+      SignalException(BreakPoint, instruction_0);
+    }
+
+  else
+    {
+      /* If we get this far, we're not an instruction reserved by the sim.  Raise 
+        the exception. */
+      SignalException(BreakPoint, instruction_0);
+    }
 }
 
 
 
-0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
-"cop<ZZ> <COP_FUN>"
-*mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  DecodeCoproc (instruction_0);
-}
 
 
 
@@ -758,24 +709,17 @@
 "dadd r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   /* this check's for overflow */
-  ALU64_BEGIN (GPR[RS]);
-  ALU64_ADD (GPR[RT]);
-  ALU64_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU64_BEGIN (GPR[RS]);
+    ALU64_ADD (GPR[RT]);
+    ALU64_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -784,28 +728,21 @@
 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  ALU64_BEGIN (GPR[RS]);
-  ALU64_ADD (EXTEND16 (IMMEDIATE));
-  ALU64_END (GPR[RT]);
+  TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
+  {
+    ALU64_BEGIN (GPR[RS]);
+    ALU64_ADD (EXTEND16 (IMMEDIATE));
+    ALU64_END (GPR[RT]);
+  }
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
 
-:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 {
   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
@@ -816,19 +753,8 @@
 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_daddiu (SD_, RS, RT, IMMEDIATE);
 }
@@ -846,47 +772,40 @@
 "daddu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_daddu (SD_, RS, RT, RD);
 }
 
 
 
-:function:64::void:do_ddiv:int rs, int rt
+:function:::void:do_ddiv:int rs, int rt
 {
+  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO ("Division");
   {
     signed64 n = GPR[rs];
     signed64 d = GPR[rt];
+    signed64 hi;
+    signed64 lo;
     if (d == 0)
       {
-       LO = SIGNED64 (0x8000000000000000);
-       HI = 0;
+       lo = SIGNED64 (0x8000000000000000);
+       hi = 0;
       }
     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
       {
-       LO = SIGNED64 (0x8000000000000000);
-       HI = 0;
+       lo = SIGNED64 (0x8000000000000000);
+       hi = 0;
       }
     else
       {
-       LO = (n / d);
-       HI = (n % d);
+       lo = (n / d);
+       hi = (n % d);
       }
+    HI = hi;
+    LO = lo;
   }
   TRACE_ALU_RESULT2 (HI, LO);
 }
@@ -895,42 +814,35 @@
 "ddiv r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_ddiv (SD_, RS, RT);
 }
 
 
 
-:function:64::void:do_ddivu:int rs, int rt
+:function:::void:do_ddivu:int rs, int rt
 {
+  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO ("Division");
   {
     unsigned64 n = GPR[rs];
     unsigned64 d = GPR[rt];
+    unsigned64 hi;
+    unsigned64 lo;
     if (d == 0)
       {
-       LO = SIGNED64 (0x8000000000000000);
-       HI = 0;
+       lo = SIGNED64 (0x8000000000000000);
+       hi = 0;
       }
     else
       {
-       LO = (n / d);
-       HI = (n % d);
+       lo = (n / d);
+       hi = (n % d);
       }
+    HI = hi;
+    LO = lo;
   }
   TRACE_ALU_RESULT2 (HI, LO);
 }
@@ -939,16 +851,8 @@
 "ddivu r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_ddivu (SD_, RS, RT);
 }
@@ -957,8 +861,8 @@
 
 :function:::void:do_div:int rs, int rt
 {
+  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO("Division");
   {
     signed32 n = GPR[rs];
     signed32 d = GPR[rt];
@@ -984,20 +888,9 @@
 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 "div r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_div (SD_, RS, RT);
 }
@@ -1006,8 +899,8 @@
 
 :function:::void:do_divu:int rs, int rt
 {
+  check_div_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO ("Division");
   {
     unsigned32 n = GPR[rs];
     unsigned32 d = GPR[rt];
@@ -1028,20 +921,9 @@
 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 "divu r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_divu (SD_, RS, RT);
 }
@@ -1060,8 +942,8 @@
   int sign;
   unsigned64 op1 = GPR[rs];
   unsigned64 op2 = GPR[rt];
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO ("Multiplication");
   /* make signed multiply unsigned */ 
   sign = 0;
   if (signed_p)
@@ -1116,12 +998,7 @@
 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 "dmult r<RS>, r<RT>"
 *mipsIII,mipsIV:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
+*vr4100:
 {
   do_dmult (SD_, RS, RT, 0);
 }
@@ -1130,9 +1007,6 @@
 "dmult r<RS>, r<RT>":RD == 0
 "dmult r<RD>, r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   do_dmult (SD_, RS, RT, RD);
 }
@@ -1147,12 +1021,7 @@
 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 "dmultu r<RS>, r<RT>"
 *mipsIII,mipsIV:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
+*vr4100:
 {
   do_dmultu (SD_, RS, RT, 0);
 }
@@ -1161,35 +1030,30 @@
 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
 "dmultu r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   do_dmultu (SD_, RS, RT, RD);
 }
 
+:function:::void:do_dsll:int rt, int rd, int shift
+{
+  GPR[rd] = GPR[rt] << shift;
+}
+
+:function:::void:do_dsllv:int rs, int rt, int rd
+{
+  int s = MASKED64 (GPR[rs], 5, 0);
+  GPR[rd] = GPR[rt] << s;
+}
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 "dsll r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  int s = SHIFT;
-  GPR[RD] = GPR[RT] << s;
+{
+  do_dsll (SD_, RT, RD, SHIFT);
 }
 
 
@@ -1197,70 +1061,37 @@
 "dsll32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   int s = 32 + SHIFT;
   GPR[RD] = GPR[RT] << s;
 }
 
-
-
 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 "dsllv r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  int s = MASKED64 (GPR[RS], 5, 0);
-  GPR[RD] = GPR[RT] << s;
+{
+  do_dsllv (SD_, RS, RT, RD);
 }
 
+:function:::void:do_dsra:int rt, int rd, int shift
+{
+  GPR[rd] = ((signed64) GPR[rt]) >> shift;
+}
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
 "dsra r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  int s = SHIFT;
-  GPR[RD] = ((signed64) GPR[RT]) >> s;
+{
+  do_dsra (SD_, RT, RD, SHIFT);
 }
 
 
@@ -1268,19 +1099,8 @@
 "dsra32 r<RT>, r<RD>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   int s = 32 + SHIFT;
   GPR[RD] = ((signed64) GPR[RT]) >> s;
@@ -1299,44 +1119,26 @@
 "dsra32 r<RT>, r<RD>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_dsrav (SD_, RS, RT, RD);
 }
 
+:function:::void:do_dsrl:int rt, int rd, int shift
+{
+  GPR[rd] = (unsigned64) GPR[rt] >> shift;
+}
+
 
 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
 "dsrl r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  int s = SHIFT;
-  GPR[RD] = (unsigned64) GPR[RT] >> s;
+{
+  do_dsrl (SD_, RT, RD, SHIFT);
 }
 
 
@@ -1344,45 +1146,30 @@
 "dsrl32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   int s = 32 + SHIFT;
   GPR[RD] = (unsigned64) GPR[RT] >> s;
 }
 
 
+:function:::void:do_dsrlv:int rs, int rt, int rd
+{
+  int s = MASKED64 (GPR[rs], 5, 0);
+  GPR[rd] = (unsigned64) GPR[rt] >> s;
+}
+
+
+
 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
 "dsrl32 r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  int s = MASKED64 (GPR[RS], 5, 0);
-  GPR[RD] = (unsigned64) GPR[RT] >> s;
+{
+  do_dsrlv (SD_, RS, RT, RD);
 }
 
 
@@ -1390,23 +1177,16 @@
 "dsub r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  ALU64_BEGIN (GPR[RS]);
-  ALU64_SUB (GPR[RT]);
-  ALU64_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU64_BEGIN (GPR[RS]);
+    ALU64_SUB (GPR[RT]);
+    ALU64_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -1421,19 +1201,8 @@
 "dsubu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_dsubu (SD_, RS, RT, RD);
 }
@@ -1442,20 +1211,9 @@
 000010,26.INSTR_INDEX:NORMAL:32::J
 "j <INSTR_INDEX>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   /* NOTE: The region used is that of the delay slot NIA and NOT the
      current instruction */
@@ -1467,20 +1225,9 @@
 000011,26.INSTR_INDEX:NORMAL:32::JAL
 "jal <INSTR_INDEX>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   /* NOTE: The region used is that of the delay slot and NOT the
      current instruction */
@@ -1489,25 +1236,13 @@
   DELAY_SLOT (region | (INSTR_INDEX << 2));
 }
 
-
 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
 "jalr r<RS>":RD == 31
 "jalr r<RD>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   address_word temp = GPR[RS];
   GPR[RD] = CIA + 8;
@@ -1518,20 +1253,9 @@
 000000,5.RS,000000000000000001000:SPECIAL:32::JR
 "jr r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   DELAY_SLOT (GPR[RS]);
 }
@@ -1550,7 +1274,9 @@
 
   vaddr = base + offset;
   if ((vaddr & access) != 0)
-    SignalExceptionAddressLoad ();
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
+    }
   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
@@ -1562,20 +1288,9 @@
 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
 "lb r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -1584,20 +1299,9 @@
 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
 "lbu r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
 }
@@ -1607,19 +1311,8 @@
 "ld r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -1630,17 +1323,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -1652,19 +1337,8 @@
 "ldl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -1674,19 +1348,8 @@
 "ldr r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -1695,20 +1358,9 @@
 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
 "lh r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -1717,20 +1369,9 @@
 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
 "lhu r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
 }
@@ -1741,19 +1382,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1764,7 +1394,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 3) != 0)
-      SignalExceptionAddressLoad();
+      {
+        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
@@ -1791,19 +1423,8 @@
 "lld r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -1814,7 +1435,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 7) != 0)
-      SignalExceptionAddressLoad();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
@@ -1833,42 +1456,22 @@
 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
 "lui r<RT>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
+  TRACE_ALU_INPUT1 (IMMEDIATE);
   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 
 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
 "lw r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -1877,20 +1480,9 @@
 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -1902,33 +1494,53 @@
   address_word reverseendian = (ReverseEndian ? -1 : 0);
   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
   unsigned int byte;
+  unsigned int word;
   address_word paddr;
   int uncached;
   unsigned64 memval;
   address_word vaddr;
+  int nr_lhs_bits;
+  int nr_rhs_bits;
+  unsigned_word lhs_mask;
+  unsigned_word temp;
 
   vaddr = base + offset;
   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem == 0)
     paddr = paddr & ~access;
-  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
-  LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
-  /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
-     (long) vaddr, byte, (long) paddr, (long) memval); */
-  if ((byte & ~access) == 0)
+
+  /* compute where within the word/mem we are */
+  byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+  word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+  nr_lhs_bits = 8 * byte + 8;
+  nr_rhs_bits = 8 * access - 8 * byte;
+  /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+
+  /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+          (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+          (long) ((unsigned64) paddr >> 32), (long) paddr,
+          word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+  LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+  if (word == 0)
     {
-      int bits = 8 * (access - byte);
-      unsigned_word screen = LSMASK (bits - 1, 0);
-      rt &= screen;
-      rt |= ((memval << bits) & ~screen);
+      /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
+      temp = (memval << nr_rhs_bits);
     }
   else
     {
-      unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
-      rt &= screen;
-      rt |= ((memval >> (8 * (mask - byte))) & ~screen);
+      /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
+      temp = (memval >> nr_lhs_bits);
     }
+  lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
+  rt = (rt & ~lhs_mask) | (temp & lhs_mask);
+
+  /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
+          (long) ((unsigned64) memval >> 32), (long) memval,
+          (long) ((unsigned64) temp >> 32), (long) temp,
+          (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+          (long) (rt >> 32), (long) rt); */
   return rt;
 }
 
@@ -1936,22 +1548,11 @@
 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
 "lwl r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
+  GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
 }
 
 
@@ -1989,20 +1590,9 @@
 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
 "lwr r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
 }
@@ -2012,19 +1602,8 @@
 "lwu r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
 }
@@ -2032,31 +1611,18 @@
 
 :function:::void:do_mfhi:int rd
 {
+  check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT1 (HI);
   GPR[rd] = HI;
   TRACE_ALU_RESULT (GPR[rd]);
-#if 0
-  HIACCESS = 3;
-#endif
 }
 
 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
 "mfhi r<RD>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_mfhi (SD_, RD);
 }
@@ -2065,31 +1631,18 @@
 
 :function:::void:do_mflo:int rd
 {
+  check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
   TRACE_ALU_INPUT1 (LO);
   GPR[rd] = LO;
   TRACE_ALU_RESULT (GPR[rd]);
-#if 0
-  LOACCESS = 3; /* 3rd instruction will be safe */
-#endif
 }
 
 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
 "mflo r<RD>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_mflo (SD_, RD);
 }
@@ -2100,15 +1653,6 @@
 "movn r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   if (GPR[RT] != 0)
     GPR[RD] = GPR[RS];
@@ -2120,15 +1664,6 @@
 "movz r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   if (GPR[RT] == 0)
     GPR[RD] = GPR[RS];
@@ -2139,29 +1674,12 @@
 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
 "mthi r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-#if 0
-  if (HIACCESS != 0)
-    sim_io_eprintf (sd, "MT (move-to) over-writing HI register value\n");
-#endif
+{
+  check_mt_hilo (SD_, HIHISTORY);
   HI = GPR[RS];
-#if 0
-  HIACCESS = 3; /* 3rd instruction will be safe */
-#endif
 }
 
 
@@ -2169,29 +1687,12 @@
 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
 "mtlo r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-#if 0
-  if (LOACCESS != 0)
-    sim_io_eprintf (sd, "MT (move-to) over-writing LO register value\n");
-#endif
+{
+  check_mt_hilo (SD_, LOHISTORY);
   LO = GPR[RS];
-#if 0
-  LOACCESS = 3; /* 3rd instruction will be safe */
-#endif
 }
 
 
@@ -2199,8 +1700,8 @@
 :function:::void:do_mult:int rs, int rt, int rd
 {
   signed64 prod;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO ("Multiplication");
   prod = (((signed64)(signed32) GPR[rs])
          * ((signed64)(signed32) GPR[rt]));
   LO = EXTEND32 (VL4_8 (prod));
@@ -2213,27 +1714,17 @@
 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
 "mult r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
+*vr4100:
 {
   do_mult (SD_, RS, RT, 0);
 }
 
 
 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
+"mult r<RS>, r<RT>":RD == 0
 "mult r<RD>, r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_mult (SD_, RS, RT, RD);
 }
@@ -2242,8 +1733,8 @@
 :function:::void:do_multu:int rs, int rt, int rd
 {
   unsigned64 prod;
+  check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
-  CHECKHILO ("Multiplication");
   prod = (((unsigned64)(unsigned32) GPR[rs])
          * ((unsigned64)(unsigned32) GPR[rt]));
   LO = EXTEND32 (VL4_8 (prod));
@@ -2256,26 +1747,16 @@
 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
 "multu r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
+*vr4100:
 {
-  do_multu (SD_, RS, RT, 0);
+  do_multu (SD_, RS, RT, RD);
 }
 
 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
+"multu r<RS>, r<RT>":RD == 0
 "multu r<RD>, r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_multu (SD_, RS, RT, 0);
 }
@@ -2291,20 +1772,9 @@
 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
 "nor r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_nor (SD_, RS, RT, RD);
 }
@@ -2320,20 +1790,9 @@
 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
 "or r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_or (SD_, RS, RT, RD);
 }
@@ -2350,20 +1809,9 @@
 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
 "ori r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_ori (SD_, RS, RT, IMMEDIATE);
 }
@@ -2372,15 +1820,6 @@
 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -2410,7 +1849,9 @@
 
   vaddr = base + offset;
   if ((vaddr & access) != 0)
-    SignalExceptionAddressStore ();
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
+    }
   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
   byte = ((vaddr & mask) ^ bigendiancpu);
@@ -2422,20 +1863,9 @@
 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
 "sb r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -2446,19 +1876,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -2469,7 +1888,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 3) != 0)
-      SignalExceptionAddressStore();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
@@ -2496,19 +1917,8 @@
 "scd r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -2519,7 +1929,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 7) != 0)
-      SignalExceptionAddressStore();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
@@ -2542,19 +1954,8 @@
 "sd r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -2565,19 +1966,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
 }
@@ -2587,19 +1977,8 @@
 "sdl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -2609,19 +1988,8 @@
 "sdr r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -2630,20 +1998,9 @@
 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
 "sh r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -2660,20 +2017,9 @@
 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
 "sll r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_sll (SD_, RT, RD, SHIFT);
 }
@@ -2691,20 +2037,9 @@
 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
 "sllv r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_sllv (SD_, RS, RT, RD);
 }
@@ -2720,20 +2055,9 @@
 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
 "slt r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_slt (SD_, RS, RT, RD);
 }
@@ -2749,20 +2073,9 @@
 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
 "slti r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_slti (SD_, RS, RT, IMMEDIATE);
 }
@@ -2778,20 +2091,9 @@
 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_sltiu (SD_, RS, RT, IMMEDIATE);
 }
@@ -2808,20 +2110,9 @@
 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
 "sltu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_sltu (SD_, RS, RT, RD);
 }
@@ -2838,20 +2129,9 @@
 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
 "sra r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_sra (SD_, RT, RD, SHIFT);
 }
@@ -2870,20 +2150,9 @@
 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
 "srav r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_srav (SD_, RS, RT, RD);
 }
@@ -2901,20 +2170,9 @@
 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
 "srl r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_srl (SD_, RT, RD, SHIFT);
 }
@@ -2932,20 +2190,9 @@
 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
 "srlv r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_srlv (SD_, RS, RT, RD);
 }
@@ -2954,24 +2201,17 @@
 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
 "sub r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
-  ALU32_BEGIN (GPR[RS]);
-  ALU32_SUB (GPR[RT]);
-  ALU32_END (GPR[RD]);
+  TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
+  {
+    ALU32_BEGIN (GPR[RS]);
+    ALU32_SUB (GPR[RT]);
+    ALU32_END (GPR[RD]);
+  }
+  TRACE_ALU_RESULT (GPR[RD]);
 }
 
 
@@ -2985,20 +2225,9 @@
 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
 "subu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_subu (SD_, RS, RT, RD);
 }
@@ -3007,20 +2236,9 @@
 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
 "sw r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
+*vr4100:
 *r3900:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
 *vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -3029,17 +2247,9 @@
 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
 }
@@ -3052,42 +2262,52 @@
   address_word reverseendian = (ReverseEndian ? -1 : 0);
   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
   unsigned int byte;
+  unsigned int word;
   address_word paddr;
   int uncached;
   unsigned64 memval;
   address_word vaddr;
+  int nr_lhs_bits;
+  int nr_rhs_bits;
 
   vaddr = base + offset;
   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem == 0)
     paddr = paddr & ~access;
-  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
-  if ((byte & ~access) == 0)
-    memval = (rt >> (8 * (access - byte)));
+
+  /* compute where within the word/mem we are */
+  byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+  word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+  nr_lhs_bits = 8 * byte + 8;
+  nr_rhs_bits = 8 * access - 8 * byte;
+  /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+  /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+          (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+          (long) ((unsigned64) paddr >> 32), (long) paddr,
+          word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+  if (word == 0)
+    {
+      memval = (rt >> nr_rhs_bits);
+    }
   else
-    memval = (rt << (8 * (mask - byte)));
-  StoreMemory (uncached, byte & access, memval, NULL, paddr, vaddr, isREAL);
+    {
+      memval = (rt << nr_lhs_bits);
+    }
+  /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
+          (long) ((unsigned64) rt >> 32), (long) rt,
+          (long) ((unsigned64) memval >> 32), (long) memval); */
+  StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
 }
 
 
 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
 "swl r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -3117,20 +2337,9 @@
 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
 "swr r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
 }
@@ -3142,20 +2351,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   SyncOperation (STYPE);
 }
@@ -3164,20 +2362,9 @@
 000000,20.CODE,001100:SPECIAL:32::SYSCALL
 "syscall <CODE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   SignalException(SystemCall, instruction_0);
 }
@@ -3188,19 +2375,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
@@ -3212,19 +2388,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
@@ -3236,19 +2401,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
@@ -3260,19 +2414,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
@@ -3284,19 +2427,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
@@ -3308,19 +2440,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
     SignalException(Trap, instruction_0);
@@ -3332,19 +2453,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
@@ -3356,19 +2466,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
@@ -3380,19 +2479,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
@@ -3404,19 +2492,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
     SignalException(Trap, instruction_0);
@@ -3428,19 +2505,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
     SignalException(Trap, instruction_0);
@@ -3452,19 +2518,8 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
     SignalException(Trap, instruction_0);
@@ -3481,20 +2536,9 @@
 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
 "xor r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_xor (SD_, RS, RT, RD);
 }
@@ -3510,20 +2554,9 @@
 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
 "xori r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_xori (SD_, RS, RT, IMMEDIATE);
 }
@@ -3602,17 +2635,9 @@
 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
 "abs.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3631,17 +2656,9 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3663,18 +2680,17 @@
 // BC1T
 // BC1TL
 
-010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
 "bc1%s<TF>%s<ND> <OFFSET>"
 *mipsI,mipsII,mipsIII:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
+  check_branch_bug ();
   TRACE_BRANCH_INPUT (PREVCOC1());
   if (PREVCOC1() == TF)
     {
       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
       TRACE_BRANCH_RESULT (dest);
+      mark_branch_bug (dest);
       DELAY_SLOT (dest);
     }
   else if (ND)
@@ -3688,25 +2704,20 @@
     }
 }
 
-010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
+#*vr4100:
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
+  check_branch_bug ();
   if (GETFCC(CC) == TF)
     {
-      DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
+      address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
+      mark_branch_bug (dest);
+      DELAY_SLOT (dest);
     }
   else if (ND)
     {
@@ -3716,6 +2727,9 @@
 
 
 
+
+
+
 // C.EQ.S
 // C.EQ.D
 // ...
@@ -3756,28 +2770,20 @@
     }
 }
 
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII:
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>":
 {
   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
 }
 
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
 }
@@ -3787,20 +2793,9 @@
 "ceil.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3819,20 +2814,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3849,7 +2833,7 @@
 
 // CFC1
 // CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
 "c%s<X>c1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
@@ -3873,23 +2857,12 @@
       /* else NOP */
     }
 }
-010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
 "c%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if (X)
     {
@@ -3936,17 +2909,9 @@
 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
 "cvt.d.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3965,17 +2930,9 @@
 "cvt.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -3996,17 +2953,9 @@
 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
 "cvt.s.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4024,17 +2973,9 @@
 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
 "cvt.w.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4052,17 +2993,9 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4080,7 +3013,7 @@
 
 // DMFC1
 // DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
 "dm%s<X>c1 r<RT>, f<FS>"
 *mipsIII:
 {
@@ -4104,23 +3037,12 @@
        PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
     }
 }
-010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
 "dm%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   if (X)
     {
@@ -4145,20 +3067,9 @@
 "floor.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4178,20 +3089,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4211,17 +3111,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -4231,12 +3123,6 @@
 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
 }
@@ -4246,20 +3132,9 @@
 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 
 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
 }
@@ -4269,12 +3144,6 @@
 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
 }
@@ -4288,12 +3157,6 @@
 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4310,12 +3173,6 @@
 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4330,7 +3187,7 @@
 
 // MFC1
 // MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
 "m%s<X>c1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
@@ -4346,21 +3203,14 @@
   else /*MFC1*/
     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
 }
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
 "m%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
+  int fs = FS;
   if (X)
     /*MTC1*/
     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
@@ -4372,17 +3222,9 @@
 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
 "mov.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4399,15 +3241,6 @@
 "mov%s<TF> r<RD>, r<RS>, <CC>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   if (GETFCC(CC) == TF)
     GPR[RD] = GPR[RS];
@@ -4419,15 +3252,6 @@
 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int format = ((instruction >> 21) & 0x00000007);
@@ -4443,15 +3267,6 @@
 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4474,15 +3289,6 @@
 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4499,15 +3305,6 @@
 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4525,15 +3322,6 @@
 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4552,17 +3340,9 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4581,17 +3361,9 @@
 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
 "neg.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4611,12 +3383,6 @@
 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4634,12 +3400,6 @@
 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4657,12 +3417,6 @@
 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4680,12 +3434,6 @@
 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4702,12 +3450,6 @@
 "prefx <HINT>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int fs = ((instruction >> 11) & 0x0000001F);
@@ -4726,12 +3468,6 @@
 *mipsIV:
 "recip.%s<FMT> f<FD>, f<FS>"
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4750,20 +3486,9 @@
 "round.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4783,20 +3508,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4815,12 +3529,6 @@
 *mipsIV:
 "rsqrt.%s<FMT> f<FD>, f<FS>"
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4840,17 +3548,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
 }
@@ -4860,12 +3560,6 @@
 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
 }
@@ -4876,17 +3570,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4904,17 +3590,9 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4934,20 +3612,9 @@
 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
 "swc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = EXTEND16 (OFFSET);
@@ -4958,21 +3625,23 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 3) != 0)
-      SignalExceptionAddressStore();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
          {
            uword64 memval = 0;
            uword64 memval1 = 0;
-           uword64 mask = 0x7;
+           uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+           address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
+           address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
            unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-           byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+           byte = ((vaddr & mask) ^ bigendiancpu);
            memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
-           {
-             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-           }
+           StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
          }
       }
   }
@@ -4983,12 +3652,6 @@
 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
 *mipsIV:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
 {
   unsigned32 instruction = instruction_0;
   int fs = ((instruction >> 11) & 0x0000001F);
@@ -4999,7 +3662,9 @@
    address_word paddr;
    int uncached;
    if ((vaddr & 3) != 0)
-    SignalExceptionAddressStore();
+     {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+     }
    else
    {
     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
@@ -5024,20 +3689,9 @@
 "trunc.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -5057,20 +3711,9 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -5095,74 +3738,44 @@
 010000,01000,00000,16.OFFSET:COP0:32::BC0F
 "bc0f <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+
+010000,01000,00000,16.OFFSET:COP0:32::BC0F
+"bc0f <OFFSET>"
+// stub needed for eCos as tx39 hardware bug workaround
+*r3900:
+{
+  /* do nothing */
+}
 
 
 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
 "bc0fl <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 
 010000,01000,00001,16.OFFSET:COP0:32::BC0T
 "bc0t <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-
+*vr4100:
 
 
 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
 "bc0tl <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 
 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 *r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 {
   unsigned32 instruction = instruction_0;
   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
@@ -5181,257 +3794,129 @@
 010000,10000,000000000000000,111001:COP0:32::DI
 "di"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+
+
+010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
+"dmfc0 r<RT>, r<RD>"
+*mipsIII,mipsIV:
+{
+  DecodeCoproc (instruction_0);
+}
+
+
+010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
+"dmtc0 r<RT>, r<RD>"
+*mipsIII,mipsIV:
+{
+  DecodeCoproc (instruction_0);
+}
 
 
 010000,10000,000000000000000,111000:COP0:32::EI
 "ei"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 
 010000,10000,000000000000000,011000:COP0:32::ERET
 "eret"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+{
+  if (SR & status_ERL)
+    {
+      /* Oops, not yet available */
+      sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
+      NIA = EPC;
+      SR &= ~status_ERL;
+    }
+  else
+    {
+      NIA = EPC;
+      SR &= ~status_EXL;
+    }
+}
 
 
 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
 "mfc0 r<RT>, r<RD> # <REGX>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*r3900:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
+  TRACE_ALU_INPUT0 ();
   DecodeCoproc (instruction_0);
+  TRACE_ALU_RESULT (GPR[RT]);
 }
 
 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
 "mtc0 r<RT>, r<RD> # <REGX>"
 *mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
 *r3900:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
+*vr4100:
 *vr5000:
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   DecodeCoproc (instruction_0);
 }
 
 
+010000,10000,000000000000000,010000:COP0:32::RFE
+"rfe"
+*mipsI,mipsII,mipsIII,mipsIV:
+*r3900:
+*vr4100:
+*vr5000:
+{
+  DecodeCoproc (instruction_0);
+}
+
+
+0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
+"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*r3900:
+{
+  DecodeCoproc (instruction_0);
+}
+
+
+
 010000,10000,000000000000000,001000:COP0:32::TLBP
 "tlbp"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 
 010000,10000,000000000000000,000001:COP0:32::TLBR
 "tlbr"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 
 010000,10000,000000000000000,000010:COP0:32::TLBWI
 "tlbwi"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 
 010000,10000,000000000000000,000110:COP0:32::TLBWR
 "tlbwr"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
-// start-sanitize-vr4320
-*vr4320:
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-*vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 
 \f
 :include:::m16.igen
-// start-sanitize-vr4320
-:include::vr4320:vr4320.igen
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-:include::vr5400:vr5400.igen
-:include:64,f::mdmx.igen
-// end-sanitize-vr5400
-// start-sanitize-r5900
-:include::r5900:r5900.igen
-// end-sanitize-r5900
 :include:::tx.igen
+:include:::vr.igen
 \f
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this instruction?
-// 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
-// *mipsI:
-// *mipsII:
-// *mipsIII:
-// *mipsIV:
-// // start-sanitize-r5900
-// *r5900:
-// // end-sanitize-r5900
-// *r3900:
-// // start-sanitize-tx19
-// *tx19:
-// // end-sanitize-tx19
-// {
-//   unsigned32 instruction = instruction_0;
-//   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
-//   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-//   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-//   {
-//     if (CoProcPresent(3))
-//       SignalException(CoProcessorUnusable);
-//     else
-//       SignalException(ReservedInstruction,instruction);
-//   }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this?
-// 11100,******,00001:RR:16::SDBBP
-// *mips16:
-// {
-//   unsigned32 instruction = instruction_0;
-//   if (have_extendval)
-//     SignalException (ReservedInstruction, instruction);
-//   {
-//     SignalException(DebugBreakPoint,instruction);
-//   }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME What is this?
-// 000000,********************,001110:SPECIAL:32::SDBBP
-// *r3900:
-// {
-//   unsigned32 instruction = instruction_0;
-//   {
-//     SignalException(DebugBreakPoint,instruction);
-//   }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
-// *vr4100:
-// {
-//   unsigned32 instruction = instruction_0;
-//   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-//   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-//   {
-//     CHECKHILO("Multiply-Add");
-//     {
-//       unsigned64 temp = (op1 * op2);
-//       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
-//       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
-//       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
-//     }
-//   }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
-// *vr4100:
-// {
-//   unsigned32 instruction = instruction_0;
-//   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-//   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-//   {
-//     CHECKHILO("Multiply-Add");
-//     {
-//       unsigned64 temp = (op1 * op2);
-//       LO = LO + temp;
-//     }
-//   }
-// }
-
-// end-sanitize-cygnus-never