* config/sh/tm-sh.h (BELIEVE_PCC_PROMOTION): Define, so that

[thirdparty/binutils-gdb.git] / sim / mips / mips.igen

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index df89140dd9b7f959232b8b116eb99dc4c537084d..c457c73dd5bf9710304c2de3b8c75d6eb6975bd6 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1,5 +1,9 @@
 // -*- C -*-
 //
+// In mips.igen, the semantics for many of the instructions were created
+// using code generated by gencode.  Those semantic segments could be
+// greatly simplified.
+//
 //    <insn> ::=
 //        <insn-word> { "+" <insn-word> }
 //        ":" <format-name>
@@ -43,13 +47,17 @@
 // start-sanitize-tx19
 :model:::tx19:tx19:
 // end-sanitize-tx19
+:model:::vr4100:mips4100:
+// start-sanitize-vr4xxx
+:model:::vr4121:mips4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 :model:::vr4320:mips4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 :model:::vr5400:mips5400:
 :model:::mdmx:mdmx:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 :model:::vr5000:mips5000:
 
 
@@ -96,8 +104,27 @@
   return CIA + 8;
 }
 
+// start-sanitize-branchbug4011
+:function:::void:check_4011_branch_bug:
+{
+  if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
+    sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
+                     itable[MY_INDEX].name,
+                     (long) CIA,
+                     (long) BRANCHBUG4011_LAST_CIA);
+}
 
+:function:::void:mark_4011_branch_bug:address_word target
+{
+  if (BRANCHBUG4011_OPTION)
+    {
+      BRANCHBUG4011_OPTION = 2;
+      BRANCHBUG4011_LAST_TARGET = target;
+      BRANCHBUG4011_LAST_CIA = CIA;
+    }
+}
 
+// end-sanitize-branchbug4011
 // Helper:
 // 
 // Check that an access to a HI/LO register meets timing requirements
@@ -125,16 +152,17 @@
 
 :function:::int:check_mt_hilo:hilo_history *history
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 {
   signed64 time = sim_events_time (SD);
   int ok = check_mf_cycles (SD_, history, time, "MT");
@@ -148,6 +176,9 @@
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
 {
   signed64 time = sim_events_time (SD);
   history->mt.timestamp = time;
@@ -155,13 +186,34 @@
   return 1;
 }
 
+
 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+*vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
+// start-sanitize-vr4320
+*vr4320:
+// end-sanitize-vr4320
+// start-sanitize-cygnus
+*vr5400:
+// end-sanitize-cygnus
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
 {
   signed64 time = sim_events_time (SD);
   int ok = 1;
   if (peer != NULL
       && peer->mt.timestamp > history->op.timestamp
-      && history->mf.timestamp < history->op.timestamp)
+      && history->mt.timestamp < history->op.timestamp
+      && ! (history->mf.timestamp > history->op.timestamp
+           && history->mf.timestamp < peer->mt.timestamp)
+      && ! (peer->mf.timestamp > history->op.timestamp
+           && peer->mf.timestamp < peer->mt.timestamp))
     {
       /* The peer has been written to since the last OP yet we have
          not */
@@ -177,18 +229,37 @@
   return ok;
 }
 
+// start-sanitize-r5900
+// The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
+:function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
+// end-sanitize-r5900
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+// start-sanitize-r5900
+{
+  /* FIXME: could record the fact that a stall occured if we want */
+  signed64 time = sim_events_time (SD);
+  history->mf.timestamp = time;
+  history->mf.cia = CIA;
+  return 1;
+}
+// end-sanitize-r5900
+
+
 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 {
   signed64 time = sim_events_time (SD);
   int ok = (check_mf_cycles (SD_, hi, time, "OP")
@@ -200,7 +271,6 @@
   return ok;
 }
 
-
 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 // a mf{hi,lo}
 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
@@ -208,7 +278,11 @@
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
 {
+  /* FIXME: could record the fact that a stall occured if we want */
   signed64 time = sim_events_time (SD);
   hi->op.timestamp = time;
   lo->op.timestamp = time;
@@ -217,22 +291,24 @@
   return 1;
 }
 
+
 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
 {
   signed64 time = sim_events_time (SD);
   int ok = (check_mf_cycles (SD_, hi, time, "OP")
@@ -245,6 +321,27 @@
 }
 
 
+// start-sanitize-r5900
+// The r5900 div et.al insns _can_ be exectuted immediatly after
+// a mf{hi,lo}
+:function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
+// end-sanitize-r5900
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+// start-sanitize-r5900
+{
+  /* FIXME: could record the fact that a stall occured if we want */
+  signed64 time = sim_events_time (SD);
+  hi->op.timestamp = time;
+  lo->op.timestamp = time;
+  hi->op.cia = CIA;
+  lo->op.cia = CIA;
+  return 1;
+}
+// end-sanitize-r5900
+
+
 
 //
 // Mips Architecture:
@@ -257,13 +354,17 @@
 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 "add r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -286,13 +387,17 @@
 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 "addi r<RT>, r<RS>, IMMEDIATE"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -322,13 +427,17 @@
 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -352,13 +461,17 @@
 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 "addu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -382,13 +495,17 @@
 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 "and r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -405,13 +522,17 @@
 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 "and r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -430,13 +551,17 @@
 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 "beq r<RS>, r<RT>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -446,8 +571,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -457,13 +586,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -473,8 +606,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -484,13 +621,17 @@
 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 "bgez r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -500,8 +641,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -509,13 +654,17 @@
 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 "bgezal r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -525,9 +674,13 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -537,13 +690,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -553,11 +710,15 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -569,13 +730,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -585,8 +750,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] >= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -596,13 +765,17 @@
 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 "bgtz r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -612,8 +785,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] > 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -623,13 +800,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -639,10 +820,14 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] > 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -652,13 +837,17 @@
 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 "blez r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -668,10 +857,14 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] <= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -681,13 +874,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -697,8 +894,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] <= 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -708,13 +909,17 @@
 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 "bltz r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -724,8 +929,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -733,13 +942,17 @@
 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 "bltzal r<RS>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -749,11 +962,15 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -763,13 +980,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -779,9 +1000,13 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   RA = (CIA + 8);
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -793,13 +1018,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -809,10 +1038,14 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   /* NOTE: The branch occurs AFTER the next instruction has been
      executed */
   if ((signed_word) GPR[RS] < 0)
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -822,13 +1055,17 @@
 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 "bne r<RS>, r<RT>, <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -838,8 +1075,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
 }
 
 
@@ -849,13 +1090,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -865,8 +1110,12 @@
 // end-sanitize-tx19
 {
   address_word offset = EXTEND16 (OFFSET) << 2;
+  check_branch_bug ();
   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
-    DELAY_SLOT (NIA + offset);
+    {
+      mark_branch_bug (NIA+offset);
+      DELAY_SLOT (NIA + offset);
+    }
   else
     NULLIFY_NEXT_INSTRUCTION ();
 }
@@ -876,13 +1125,17 @@
 000000,20.CODE,001101:SPECIAL:32::BREAK
 "break"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -891,24 +1144,80 @@
 *tx19:
 // end-sanitize-tx19
 {
-  SignalException(BreakPoint, instruction_0);
+  /* Check for some break instruction which are reserved for use by the simulator.  */
+  unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
+  if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
+      break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+    {
+      sim_engine_halt (SD, CPU, NULL, cia,
+                       sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
+    }
+  else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
+           break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
+    {
+      if (STATE & simDELAYSLOT)
+        PC = cia - 4; /* reference the branch instruction */
+      else
+        PC = cia;
+      sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
+    }
+// start-sanitize-sky
+#ifdef TARGET_SKY
+  else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
+    {
+      sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
+    }
+  else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
+    {
+      sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
+    }
+  else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
+    {
+      sim_monitor(SD, CPU, cia, 316);  /* Magic number for idt printf routine. */
+    }
+  else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
+    {
+      /* This is a multi-phase load instruction.  Load next configured
+        executable and return its starting PC in A0 ($4). */
+      
+      if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
+       {
+         sim_io_eprintf (SD, "Cannot load program %d.  Not enough load-next options.\n",
+                         STATE_MLOAD_COUNT (SD));
+         A0 = 0;
+       }
+      else
+       {
+         char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
+         SIM_RC rc;
+         
+         STATE_MLOAD_INDEX (SD) ++;
+         
+         /* call sim_load_file, preserving most previous state */
+         rc = sim_load (SD, next, NULL, 0);
+         if(rc != SIM_RC_OK)
+           {
+             sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
+                             STATE_MLOAD_INDEX (SD));
+             A0 = 0;
+           }
+         else
+           A0 = STATE_START_ADDR (SD);
+       }
+    }
+#endif TARGET_SKY
+// end-sanitize-sky
+
+  else
+    {
+      /* If we get this far, we're not an instruction reserved by the sim.  Raise 
+        the exception. */
+      SignalException(BreakPoint, instruction_0);
+    }
 }
 
 
 
-0100,ZZ!0!1!3,26.COP_FUN:NORMAL:32::COPz
-"cop<ZZ> <COP_FUN>"
-*mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-*r3900:
-// start-sanitize-tx19
-*tx19:
-// end-sanitize-tx19
-{
-  DecodeCoproc (instruction_0);
-}
 
 
 
@@ -916,13 +1225,17 @@
 "dadd r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -946,13 +1259,17 @@
 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -971,7 +1288,7 @@
 
 
 
-:function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
+:function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 {
   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
@@ -982,13 +1299,17 @@
 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1012,13 +1333,17 @@
 "daddu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1031,28 +1356,32 @@
 
 
 
-:function:64::void:do_ddiv:int rs, int rt
+:function:::void:do_ddiv:int rs, int rt
 {
   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   {
     signed64 n = GPR[rs];
     signed64 d = GPR[rt];
+    signed64 hi;
+    signed64 lo;
     if (d == 0)
       {
-       LO = SIGNED64 (0x8000000000000000);
-       HI = 0;
+       lo = SIGNED64 (0x8000000000000000);
+       hi = 0;
       }
     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
       {
-       LO = SIGNED64 (0x8000000000000000);
-       HI = 0;
+       lo = SIGNED64 (0x8000000000000000);
+       hi = 0;
       }
     else
       {
-       LO = (n / d);
-       HI = (n % d);
+       lo = (n / d);
+       hi = (n % d);
       }
+    HI = hi;
+    LO = lo;
   }
   TRACE_ALU_RESULT2 (HI, LO);
 }
@@ -1061,13 +1390,17 @@
 "ddiv r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1080,23 +1413,27 @@
 
 
 
-:function:64::void:do_ddivu:int rs, int rt
+:function:::void:do_ddivu:int rs, int rt
 {
   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
   {
     unsigned64 n = GPR[rs];
     unsigned64 d = GPR[rt];
+    unsigned64 hi;
+    unsigned64 lo;
     if (d == 0)
       {
-       LO = SIGNED64 (0x8000000000000000);
-       HI = 0;
+       lo = SIGNED64 (0x8000000000000000);
+       hi = 0;
       }
     else
       {
-       LO = (n / d);
-       HI = (n % d);
+       lo = (n / d);
+       hi = (n % d);
       }
+    HI = hi;
+    LO = lo;
   }
   TRACE_ALU_RESULT2 (HI, LO);
 }
@@ -1105,13 +1442,17 @@
 "ddivu r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1150,13 +1491,17 @@
 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 "div r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1194,13 +1539,17 @@
 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 "divu r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1282,6 +1631,10 @@
 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 "dmult r<RS>, r<RT>"
 *mipsIII,mipsIV:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1296,9 +1649,9 @@
 "dmult r<RS>, r<RT>":RD == 0
 "dmult r<RD>, r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   do_dmult (SD_, RS, RT, RD);
 }
@@ -1313,6 +1666,10 @@
 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
 "dmultu r<RS>, r<RT>"
 *mipsIII,mipsIV:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -1327,26 +1684,40 @@
 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
 "dmultu r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   do_dmultu (SD_, RS, RT, RD);
 }
 
+:function:::void:do_dsll:int rt, int rd, int shift
+{
+  GPR[rd] = GPR[rt] << shift;
+}
+
+:function:::void:do_dsllv:int rs, int rt, int rd
+{
+  int s = MASKED64 (GPR[rs], 5, 0);
+  GPR[rd] = GPR[rt] << s;
+}
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 "dsll r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1354,8 +1725,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SHIFT;
-  GPR[RD] = GPR[RT] << s;
+  do_dsll (SD_, RT, RD, SHIFT);
 }
 
 
@@ -1363,13 +1733,17 @@
 "dsll32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1381,19 +1755,21 @@
   GPR[RD] = GPR[RT] << s;
 }
 
-
-
 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
 "dsllv r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1401,23 +1777,30 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = MASKED64 (GPR[RS], 5, 0);
-  GPR[RD] = GPR[RT] << s;
+  do_dsllv (SD_, RS, RT, RD);
 }
 
+:function:::void:do_dsra:int rt, int rd, int shift
+{
+  GPR[rd] = ((signed64) GPR[rt]) >> shift;
+}
 
 
 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
 "dsra r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1425,8 +1808,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SHIFT;
-  GPR[RD] = ((signed64) GPR[RT]) >> s;
+  do_dsra (SD_, RT, RD, SHIFT);
 }
 
 
@@ -1434,13 +1816,17 @@
 "dsra32 r<RT>, r<RD>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1465,13 +1851,17 @@
 "dsra32 r<RT>, r<RD>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1482,18 +1872,27 @@
   do_dsrav (SD_, RS, RT, RD);
 }
 
+:function:::void:do_dsrl:int rt, int rd, int shift
+{
+  GPR[rd] = (unsigned64) GPR[rt] >> shift;
+}
+
 
 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
 "dsrl r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1501,8 +1900,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = SHIFT;
-  GPR[RD] = (unsigned64) GPR[RT] >> s;
+  do_dsrl (SD_, RT, RD, SHIFT);
 }
 
 
@@ -1510,13 +1908,17 @@
 "dsrl32 r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1529,17 +1931,29 @@
 }
 
 
+:function:::void:do_dsrlv:int rs, int rt, int rd
+{
+  int s = MASKED64 (GPR[rs], 5, 0);
+  GPR[rd] = (unsigned64) GPR[rt] >> s;
+}
+
+
+
 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
 "dsrl32 r<RD>, r<RT>, r<RS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1547,8 +1961,7 @@
 *tx19:
 // end-sanitize-tx19
 {
-  int s = MASKED64 (GPR[RS], 5, 0);
-  GPR[RD] = (unsigned64) GPR[RT] >> s;
+  do_dsrlv (SD_, RS, RT, RD);
 }
 
 
@@ -1556,13 +1969,17 @@
 "dsub r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1591,13 +2008,17 @@
 "dsubu r<RD>, r<RS>, r<RT>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1612,13 +2033,17 @@
 000010,26.INSTR_INDEX:NORMAL:32::J
 "j <INSTR_INDEX>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1637,13 +2062,17 @@
 000011,26.INSTR_INDEX:NORMAL:32::JAL
 "jal <INSTR_INDEX>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1659,18 +2088,21 @@
   DELAY_SLOT (region | (INSTR_INDEX << 2));
 }
 
-
 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
 "jalr r<RS>":RD == 31
 "jalr r<RD>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1688,13 +2120,17 @@
 000000,5.RS,000000000000000001000:SPECIAL:32::JR
 "jr r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1720,7 +2156,9 @@
 
   vaddr = base + offset;
   if ((vaddr & access) != 0)
-    SignalExceptionAddressLoad ();
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
+    }
   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
@@ -1732,13 +2170,17 @@
 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
 "lb r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1754,13 +2196,17 @@
 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
 "lbu r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1777,13 +2223,17 @@
 "ld r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1800,13 +2250,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -1822,13 +2276,17 @@
 "ldl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1844,13 +2302,17 @@
 "ldr r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1865,13 +2327,17 @@
 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
 "lh r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1887,13 +2353,17 @@
 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
 "lhu r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1911,13 +2381,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1934,7 +2408,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 3) != 0)
-      SignalExceptionAddressLoad();
+      {
+        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
@@ -1961,13 +2437,17 @@
 "lld r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -1984,7 +2464,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 7) != 0)
-      SignalExceptionAddressLoad();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
@@ -2003,13 +2485,17 @@
 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
 "lui r<RT>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2027,13 +2513,17 @@
 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
 "lw r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2049,13 +2539,17 @@
 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2074,33 +2568,53 @@
   address_word reverseendian = (ReverseEndian ? -1 : 0);
   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
   unsigned int byte;
+  unsigned int word;
   address_word paddr;
   int uncached;
   unsigned64 memval;
   address_word vaddr;
+  int nr_lhs_bits;
+  int nr_rhs_bits;
+  unsigned_word lhs_mask;
+  unsigned_word temp;
 
   vaddr = base + offset;
   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem == 0)
     paddr = paddr & ~access;
-  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
-  LoadMemory (&memval, NULL, uncached, byte & access, paddr, vaddr, isDATA, isREAL);
-  /* printf ("ll: 0x%08lx %d@0x%08lx 0x%08lx\n",
-     (long) vaddr, byte, (long) paddr, (long) memval); */
-  if ((byte & ~access) == 0)
+
+  /* compute where within the word/mem we are */
+  byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+  word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+  nr_lhs_bits = 8 * byte + 8;
+  nr_rhs_bits = 8 * access - 8 * byte;
+  /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+
+  /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+          (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+          (long) ((unsigned64) paddr >> 32), (long) paddr,
+          word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+  LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
+  if (word == 0)
     {
-      int bits = 8 * (access - byte);
-      unsigned_word screen = LSMASK (bits - 1, 0);
-      rt &= screen;
-      rt |= ((memval << bits) & ~screen);
+      /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
+      temp = (memval << nr_rhs_bits);
     }
   else
     {
-      unsigned_word screen = LSMASK (8 * (access - (byte & access)) - 1, 0);
-      rt &= screen;
-      rt |= ((memval >> (8 * (mask - byte))) & ~screen);
+      /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
+      temp = (memval >> nr_lhs_bits);
     }
+  lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
+  rt = (rt & ~lhs_mask) | (temp & lhs_mask);
+
+  /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
+          (long) ((unsigned64) memval >> 32), (long) memval,
+          (long) ((unsigned64) temp >> 32), (long) temp,
+          (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
+          (long) (rt >> 32), (long) rt); */
   return rt;
 }
 
@@ -2108,13 +2622,17 @@
 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
 "lwl r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2161,13 +2679,17 @@
 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
 "lwr r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2184,13 +2706,17 @@
 "lwu r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2213,13 +2739,17 @@
 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
 "mfhi r<RD>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2244,13 +2774,17 @@
 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
 "mflo r<RD>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2268,12 +2802,15 @@
 "movn r<RD>, r<RS>, r<RT>"
 *mipsIV:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2291,9 +2828,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2307,13 +2844,17 @@
 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
 "mthi r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2331,13 +2872,17 @@
 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
 "mtlo r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2369,6 +2914,10 @@
 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
 "mult r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
@@ -2380,9 +2929,9 @@
 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
 "mult r<RD>, r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2412,6 +2961,10 @@
 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
 "multu r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
@@ -2422,9 +2975,9 @@
 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
 "multu r<RD>, r<RS>, r<RT>"
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2447,13 +3000,17 @@
 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
 "nor r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2476,13 +3033,17 @@
 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
 "or r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2506,13 +3067,17 @@
 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
 "ori r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2531,9 +3096,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2566,7 +3131,9 @@
 
   vaddr = base + offset;
   if ((vaddr & access) != 0)
-    SignalExceptionAddressStore ();
+    {
+      SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
+    }
   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
   byte = ((vaddr & mask) ^ bigendiancpu);
@@ -2578,13 +3145,17 @@
 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
 "sb r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2602,13 +3173,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2625,7 +3200,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 3) != 0)
-      SignalExceptionAddressStore();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
@@ -2652,13 +3229,17 @@
 "scd r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2675,7 +3256,9 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 7) != 0)
-      SignalExceptionAddressStore();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
@@ -2698,13 +3281,17 @@
 "sd r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2721,16 +3308,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -2743,13 +3331,17 @@
 "sdl r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2765,13 +3357,17 @@
 "sdr r<RT>, <OFFSET>(r<BASE>)"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2786,13 +3382,17 @@
 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
 "sh r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2816,13 +3416,17 @@
 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
 "sll r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2847,13 +3451,17 @@
 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
 "sllv r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2876,13 +3484,17 @@
 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
 "slt r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2905,13 +3517,17 @@
 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
 "slti r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2934,13 +3550,17 @@
 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2964,13 +3584,17 @@
 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
 "sltu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -2994,13 +3618,17 @@
 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
 "sra r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3026,13 +3654,17 @@
 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
 "srav r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3057,13 +3689,17 @@
 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
 "srl r<RD>, r<RT>, <SHIFT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3088,13 +3724,17 @@
 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
 "srlv r<RD>, r<RT>, r<RS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3110,13 +3750,17 @@
 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
 "sub r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3145,13 +3789,17 @@
 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
 "subu r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3167,6 +3815,10 @@
 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
 "sw r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
@@ -3175,9 +3827,9 @@
 *vr4320:
 // end-sanitize-vr4320
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3189,13 +3841,17 @@
 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3212,35 +3868,60 @@
   address_word reverseendian = (ReverseEndian ? -1 : 0);
   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
   unsigned int byte;
+  unsigned int word;
   address_word paddr;
   int uncached;
   unsigned64 memval;
   address_word vaddr;
+  int nr_lhs_bits;
+  int nr_rhs_bits;
 
   vaddr = base + offset;
   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
   paddr = (paddr ^ (reverseendian & mask));
   if (BigEndianMem == 0)
     paddr = paddr & ~access;
-  byte = ((vaddr & mask) ^ (bigendiancpu & mask));
-  if ((byte & ~access) == 0)
-    memval = (rt >> (8 * (access - byte)));
+
+  /* compute where within the word/mem we are */
+  byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
+  word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
+  nr_lhs_bits = 8 * byte + 8;
+  nr_rhs_bits = 8 * access - 8 * byte;
+  /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
+  /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
+          (long) ((unsigned64) vaddr >> 32), (long) vaddr,
+          (long) ((unsigned64) paddr >> 32), (long) paddr,
+          word, byte, nr_lhs_bits, nr_rhs_bits); */
+
+  if (word == 0)
+    {
+      memval = (rt >> nr_rhs_bits);
+    }
   else
-    memval = (rt << (8 * (mask - byte)));
-  StoreMemory (uncached, byte & access, memval, 0, paddr, vaddr, isREAL);
+    {
+      memval = (rt << nr_lhs_bits);
+    }
+  /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
+          (long) ((unsigned64) rt >> 32), (long) rt,
+          (long) ((unsigned64) memval >> 32), (long) memval); */
+  StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
 }
 
 
 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
 "swl r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3277,13 +3958,17 @@
 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
 "swr r<RT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3302,13 +3987,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3324,13 +4013,17 @@
 000000,20.CODE,001100:SPECIAL:32::SYSCALL
 "syscall <CODE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3348,13 +4041,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3372,13 +4069,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3396,13 +4097,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3420,13 +4125,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3444,13 +4153,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3468,13 +4181,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3492,13 +4209,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3516,13 +4237,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3540,13 +4265,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3564,13 +4293,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3588,13 +4321,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3612,13 +4349,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3641,13 +4382,17 @@
 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
 "xor r<RD>, r<RS>, r<RT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3670,13 +4415,17 @@
 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
 "xori r<RT>, r<RS>, <IMMEDIATE>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3762,13 +4511,17 @@
 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
 "abs.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3791,13 +4544,17 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3823,18 +4580,20 @@
 // BC1T
 // BC1TL
 
-010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
 "bc1%s<TF>%s<ND> <OFFSET>"
 *mipsI,mipsII,mipsIII:
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
 {
+  check_branch_bug ();
   TRACE_BRANCH_INPUT (PREVCOC1());
   if (PREVCOC1() == TF)
     {
       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
       TRACE_BRANCH_RESULT (dest);
+      mark_branch_bug (dest);
       DELAY_SLOT (dest);
     }
   else if (ND)
@@ -3848,25 +4607,37 @@
     }
 }
 
-010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
+// start-sanitize-vr4xxx
+// FIXME: vr4100,vr4320, and 4121 all should be in the
+// previous insn, but the renameing thing wasn't working
+// so I cheated -gavin
+// end-sanitize-vr4xxx
+010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
 *mipsIV:
 *vr5000:
+#*vr4100:
 // start-sanitize-vr4320
-*vr4320:
+//*vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
+  check_branch_bug ();
   if (GETFCC(CC) == TF)
     {
-      DELAY_SLOT (NIA + (EXTEND16 (OFFSET) << 2));
+      address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
+      mark_branch_bug (dest);
+      DELAY_SLOT (dest);
     }
   else if (ND)
     {
@@ -3876,6 +4647,9 @@
 
 
 
+
+
+
 // C.EQ.S
 // C.EQ.D
 // ...
@@ -3916,24 +4690,28 @@
     }
 }
 
-010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
+"c.%s<COND>.%s<FMT> f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII:
-"c.%s<COND>.%s<FMT> f<FS>, f<FT>":
 {
   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
 }
 
-010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
+010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -3947,13 +4725,17 @@
 "ceil.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -3979,13 +4761,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4009,7 +4795,7 @@
 
 // CFC1
 // CTC1
-010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
 "c%s<X>c1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
@@ -4033,16 +4819,20 @@
       /* else NOP */
     }
 }
-010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
+010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
 "c%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4093,13 +4883,17 @@
 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
 "cvt.d.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4122,13 +4916,17 @@
 "cvt.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4153,13 +4951,17 @@
 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
 "cvt.s.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4181,13 +4983,17 @@
 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
 "cvt.w.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4209,13 +5015,17 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4237,7 +5047,7 @@
 
 // DMFC1
 // DMTC1
-010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
 "dm%s<X>c1 r<RT>, f<FS>"
 *mipsIII:
 {
@@ -4261,16 +5071,20 @@
        PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
     }
 }
-010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
+010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
 "dm%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4302,13 +5116,17 @@
 "floor.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4335,13 +5153,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4368,13 +5190,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4391,9 +5217,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
 }
@@ -4403,13 +5229,17 @@
 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1 
 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4429,9 +5259,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
 }
@@ -4448,9 +5278,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4470,9 +5300,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4487,7 +5317,7 @@
 
 // MFC1
 // MTC1
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
 "m%s<X>c1 r<RT>, f<FS>"
 *mipsI:
 *mipsII:
@@ -4503,21 +5333,26 @@
   else /*MFC1*/
     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
 }
-010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
+010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
 "m%s<X>c1 r<RT>, f<FS>"
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
 // end-sanitize-tx19
 {
+  int fs = FS;
   if (X)
     /*MTC1*/
     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
@@ -4529,13 +5364,17 @@
 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
 "mov.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4559,9 +5398,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4579,9 +5418,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4603,9 +5442,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4634,9 +5473,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4659,9 +5498,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4685,9 +5524,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4709,13 +5548,17 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4738,13 +5581,17 @@
 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
 "neg.%s<FMT> f<FD>, f<FS>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -4771,9 +5618,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4794,9 +5641,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4817,9 +5664,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4840,9 +5687,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4862,9 +5709,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int fs = ((instruction >> 11) & 0x0000001F);
@@ -4886,9 +5733,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4907,13 +5754,17 @@
 "round.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4940,13 +5791,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -4975,9 +5830,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int destreg = ((instruction >> 6) & 0x0000001F);
@@ -4997,13 +5852,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -5020,9 +5879,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
 }
@@ -5033,13 +5892,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -5061,13 +5924,17 @@
 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -5091,13 +5958,17 @@
 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
 "swc1 f<FT>, <OFFSET>(r<BASE>)"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5115,21 +5986,23 @@
     address_word paddr;
     int uncached;
     if ((vaddr & 3) != 0)
-      SignalExceptionAddressStore();
+      {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
+      }
     else
       {
        if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
          {
            uword64 memval = 0;
            uword64 memval1 = 0;
-           uword64 mask = 0x7;
+           uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
+           address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
+           address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
            unsigned int byte;
-           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
-           byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
+           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
+           byte = ((vaddr & mask) ^ bigendiancpu);
            memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
-           {
-             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
-           }
+           StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
          }
       }
   }
@@ -5143,9 +6016,9 @@
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 {
   unsigned32 instruction = instruction_0;
   int fs = ((instruction >> 11) & 0x0000001F);
@@ -5156,7 +6029,9 @@
    address_word paddr;
    int uncached;
    if ((vaddr & 3) != 0)
-    SignalExceptionAddressStore();
+     {
+       SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
+     }
    else
    {
     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
@@ -5181,13 +6056,17 @@
 "trunc.l.%s<FMT> f<FD>, f<FS>"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5214,13 +6093,17 @@
 *mipsII:
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5252,70 +6135,74 @@
 010000,01000,00000,16.OFFSET:COP0:32::BC0F
 "bc0f <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
 "bc0fl <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,01000,00001,16.OFFSET:COP0:32::BC0T
 "bc0t <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
-
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 
 
 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
 "bc0tl <OFFSET>"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 *r3900:
 // start-sanitize-tx19
 *tx19:
@@ -5338,44 +6225,50 @@
 010000,10000,000000000000000,111001:COP0:32::DI
 "di"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,10000,000000000000000,111000:COP0:32::EI
 "ei"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,10000,000000000000000,011000:COP0:32::ERET
 "eret"
 *mipsIII:
 *mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5399,13 +6292,17 @@
 "mfc0 r<RT>, r<RD> # <REGX>"
 *mipsI,mipsII,mipsIII,mipsIV:
 *r3900:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5422,13 +6319,17 @@
 *tx19:
 // end-sanitize-tx19
 *r3900:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5444,13 +6345,17 @@
 *tx19:
 // end-sanitize-tx19
 *r3900:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
 *vr5000:
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 *r5900:
 // end-sanitize-r5900
@@ -5459,78 +6364,99 @@
 }
 
 
+0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
+"cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
+*mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
+// start-sanitize-r5900
+*r5900:
+// end-sanitize-r5900
+*r3900:
+// start-sanitize-tx19
+*tx19:
+// end-sanitize-tx19
+{
+  DecodeCoproc (instruction_0);
+}
+
+
+
 010000,10000,000000000000000,001000:COP0:32::TLBP
 "tlbp"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,10000,000000000000000,000001:COP0:32::TLBR
 "tlbr"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,10000,000000000000000,000010:COP0:32::TLBWI
 "tlbwi"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 
 010000,10000,000000000000000,000110:COP0:32::TLBWR
 "tlbwr"
 *mipsI,mipsII,mipsIII,mipsIV:
+*vr4100:
 *vr5000:
+// start-sanitize-vr4xxx
+*vr4121:
+// end-sanitize-vr4xxx
 // start-sanitize-vr4320
 *vr4320:
 // end-sanitize-vr4320
-// start-sanitize-vr5400
+// start-sanitize-cygnus
 *vr5400:
-// end-sanitize-vr5400
-// start-sanitize-r5900
-*r5900:
-// end-sanitize-r5900
+// end-sanitize-cygnus
 
 \f
 :include:::m16.igen
-// start-sanitize-vr4320
-:include::vr4320:vr4320.igen
-// end-sanitize-vr4320
-// start-sanitize-vr5400
-:include::vr5400:vr5400.igen
+// start-sanitize-cygnus
 :include:64,f::mdmx.igen
-// end-sanitize-vr5400
+// end-sanitize-cygnus
 // start-sanitize-r5900
 :include::r5900:r5900.igen
 // end-sanitize-r5900
 :include:::tx.igen
+:include:::vr.igen
 \f
 // start-sanitize-cygnus-never
 
@@ -5589,45 +6515,3 @@
 // }
 
 // end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101000:SPECIAL:32::MADD16
-// *vr4100:
-// {
-//   unsigned32 instruction = instruction_0;
-//   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-//   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-//   {
-//     CHECKHILO("Multiply-Add");
-//     {
-//       unsigned64 temp = (op1 * op2);
-//       temp += (SET64HI(VL4_8(HI)) | VL4_8(LO));
-//       LO = SIGNEXTEND((unsigned64)VL4_8(temp),32);
-//       HI = SIGNEXTEND((unsigned64)VH4_8(temp),32);
-//     }
-//   }
-// }
-
-// end-sanitize-cygnus-never
-// start-sanitize-cygnus-never
-
-// // FIXME FIXME FIXME This apparently belongs to the vr4100 which
-// // isn't yet reconized by this simulator.
-// 000000,5.RS,5.RT,0000000000101001:SPECIAL:64::DMADD16
-// *vr4100:
-// {
-//   unsigned32 instruction = instruction_0;
-//   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
-//   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
-//   {
-//     CHECKHILO("Multiply-Add");
-//     {
-//       unsigned64 temp = (op1 * op2);
-//       LO = LO + temp;
-//     }
-//   }
-// }
-
-// end-sanitize-cygnus-never