* rx.c (SHIFT_OP): A shift by zero still sets the condition codes.

[thirdparty/binutils-gdb.git] / sim / rx / rx.c

diff --git a/sim/rx/rx.c b/sim/rx/rx.c
index 17f5b46f4af23a4b8563b796c88d4b4cb6fe8764..dd886760aee10a7a3a9a6c04f632315192c1581e 100644 (file)
--- a/sim/rx/rx.c
+++ b/sim/rx/rx.c
@@ -1,6 +1,6 @@
 /* rx.c --- opcode semantics for stand-alone RX simulator.
 
-Copyright (C) 2008, 2009, 2010 Free Software Foundation, Inc.
+Copyright (C) 2008-2013 Free Software Foundation, Inc.
 Contributed by Red Hat, Inc.
 
 This file is part of the GNU simulators.
@@ -136,7 +136,7 @@ static const char * id_names[] = {
 };
 
 static const char * optype_names[] = {
-  "    ",
+  " -  ",
   "#Imm",      /* #addend */
   " Rn ",      /* Rn */
   "[Rn]",      /* [Rn + addend] */
@@ -264,6 +264,52 @@ cycles (int throughput)
       new_rt = r;                              \
     }
 
+static int
+lsb_count (unsigned long v, int is_signed)
+{
+  int i, lsb;
+  if (is_signed && (v & 0x80000000U))
+    v = (unsigned long)(long)(-v);
+  for (i=31; i>=0; i--)
+    if (v & (1 << i))
+      {
+       /* v is 0..31, we want 1=1-2, 2=3-4, 3=5-6, etc. */
+       lsb = (i + 2) / 2;
+       return lsb;
+      }
+  return 0;
+}
+
+static int
+divu_cycles(unsigned long num, unsigned long den)
+{
+  int nb = lsb_count (num, 0);
+  int db = lsb_count (den, 0);
+  int rv;
+
+  if (nb < db)
+    rv = 2;
+  else
+    rv = 3 + nb - db;
+  E (rv);
+  return rv;
+}
+
+static int
+div_cycles(long num, long den)
+{
+  int nb = lsb_count ((unsigned long)num, 1);
+  int db = lsb_count ((unsigned long)den, 1);
+  int rv;
+
+  if (nb < db)
+    rv = 3;
+  else
+    rv = 5 + nb - db;
+  E (rv);
+  return rv;
+}
+
 #else /* !CYCLE_ACCURATE */
 
 #define cycles(t)
@@ -274,6 +320,9 @@ cycles (int throughput)
 #define RL(r)
 #define RLD(r)
 
+#define divu_cycles(n,d)
+#define div_cycles(n,d)
+
 #endif /* else CYCLE_ACCURATE */
 
 static int size2bytes[] = {
@@ -683,8 +732,7 @@ poppc()
       c = val & carry_mask; \
       val OP 1; \
     } \
-  if (count) \
-    set_oszc (val, 4, c); \
+  set_oszc (val, 4, c); \
   PD (val); \
 }
 
@@ -1038,10 +1086,10 @@ decode_opcode ()
       break;
 
     case RXO_branchrel:
-      if (GS())
+      if (opcode->op[1].type == RX_Operand_None || GS())
        {
          int delta = GD();
-         regs.r_pc += delta;
+         regs.r_pc = opcode_pc + delta;
 #ifdef CYCLE_ACCURATE
          /* Note: specs say 3, chip says 2.  */
          if (delta >= 0 && delta < 16
@@ -1126,6 +1174,7 @@ decode_opcode ()
        {
          tprintf("#NAN\n");
          set_flags (FLAGBIT_O, FLAGBIT_O);
+         cycles (3);
        }
       else
        {
@@ -1133,9 +1182,8 @@ decode_opcode ()
          tprintf("%d\n", v);
          set_flags (FLAGBIT_O, 0);
          PD (v);
+         div_cycles (mb, ma);
        }
-      /* Note: spec says 3 to 22 cycles, we are pessimistic.  */
-      cycles (22);
       break;
 
     case RXO_divu: /* d = d / s */
@@ -1146,6 +1194,7 @@ decode_opcode ()
        {
          tprintf("#NAN\n");
          set_flags (FLAGBIT_O, FLAGBIT_O);
+         cycles (2);
        }
       else
        {
@@ -1153,9 +1202,8 @@ decode_opcode ()
          tprintf("%u\n", v);
          set_flags (FLAGBIT_O, 0);
          PD (v);
+         divu_cycles (umb, uma);
        }
-      /* Note: spec says 2 to 20 cycles, we are pessimistic.  */
-      cycles (20);
       break;
 
     case RXO_emul:
@@ -1232,7 +1280,9 @@ decode_opcode ()
       v = GS ();
       if (v == 255)
        {
-         DO_RETURN (rx_syscall (regs.r[5]));
+         int rc = rx_syscall (regs.r[5]);
+         if (! RX_STEPPED (rc))
+           DO_RETURN (rc);
        }
       else
        {
@@ -1328,6 +1378,14 @@ decode_opcode ()
     case RXO_mov:
       v = GS ();
 
+      if (opcode->op[1].type == RX_Operand_Register
+         && opcode->op[1].reg == 17 /* PC */)
+       {
+         /* Special case.  We want the address of the insn, not the
+            address of the next insn.  */
+         v = opcode_pc;
+       }
+
       if (opcode->op[0].type == RX_Operand_Register
          && opcode->op[0].reg == 16 /* PSW */)
        {
@@ -1743,6 +1801,22 @@ decode_opcode ()
       E1;
       break;
 
+    case RXO_satr:
+      if (FLAG_O && ! FLAG_S)
+       {
+         put_reg (6, 0x0);
+         put_reg (5, 0x7fffffff);
+         put_reg (4, 0xffffffff);
+       }
+      else if (FLAG_O && FLAG_S)
+       {
+         put_reg (6, 0xffffffff);
+         put_reg (5, 0x80000000);
+         put_reg (4, 0x0);
+       }
+      E1;
+      break;
+      
     case RXO_sbb:
       MATH_OP (-, ! carry);
       break;
@@ -1904,7 +1978,7 @@ decode_opcode ()
     case RXO_suntil:
       RL(3);
 #ifdef CYCLE_ACCURATE
-      tx = regs.r[3];
+      tx = 0;
 #endif
       if (regs.r[3] == 0)
        {
@@ -1920,10 +1994,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_si (get_reg (1));
              regs.r[1] += 4;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb == uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * tx);
+#endif
          break;
        case RX_Word:
          uma = get_reg (2) & 0xffff;
@@ -1932,10 +2011,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_hi (get_reg (1));
              regs.r[1] += 2;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb == uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 2) + 3 * (tx % 2));
+#endif
          break;
        case RX_Byte:
          uma = get_reg (2) & 0xff;
@@ -1944,10 +2028,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_qi (regs.r[1]);
              regs.r[1] += 1;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb == uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 4) + 3 * (tx % 4));
+#endif
          break;
        default:
          abort();
@@ -1961,7 +2050,7 @@ decode_opcode ()
     case RXO_swhile:
       RL(3);
 #ifdef CYCLE_ACCURATE
-      tx = regs.r[3];
+      tx = 0;
 #endif
       if (regs.r[3] == 0)
        break;
@@ -1974,10 +2063,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_si (get_reg (1));
              regs.r[1] += 4;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb != uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * tx);
+#endif
          break;
        case RX_Word:
          uma = get_reg (2) & 0xffff;
@@ -1986,10 +2080,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_hi (get_reg (1));
              regs.r[1] += 2;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb != uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 2) + 3 * (tx % 2));
+#endif
          break;
        case RX_Byte:
          uma = get_reg (2) & 0xff;
@@ -1998,10 +2097,15 @@ decode_opcode ()
              regs.r[3] --;
              umb = mem_get_qi (regs.r[1]);
              regs.r[1] += 1;
+#ifdef CYCLE_ACCURATE
+             tx ++;
+#endif
              if (umb != uma)
                break;
            }
+#ifdef CYCLE_ACCURATE
          cycles (3 + 3 * (tx / 4) + 3 * (tx % 4));
+#endif
          break;
        default:
          abort();