+2002-06-16 Andrew Cagney <ac131313@redhat.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+2002-06-08 Andrew Cagney <cagney@redhat.com>
+
+ * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
+
+2001-01-30 Ben Elliston <bje@redhat.com>
+
+ * interp.c (sim_create_inferior): Record program arguments for
+ later inspection by the trap handler.
+ (count_argc): New function.
+ (prog_argv): Declare static.
+ (sim_write): Declare.
+ (trap): Implement argc, argnlen and argn system calls. Do not
+ abort on unknown system calls--simply return -1.
+ * syscall.h (SYS_argc, SYS_argnlen, SYS_argn): Define.
+
+2001-01-24 Alexandre Oliva <aoliva@redhat.com>
+
+ * interp.c (trap): Implement time.
+
+2000-10-24 Ben Elliston <bje@redhat.com>
+
+ * gencode.c (tab): Delimit strings with commas where applicable.
+
+Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon May 15 22:04:51 2000 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+sh-dsp support, simulator speedup by using host byte order:
+
+ * Makefile.in (interp.o): Depends on ppi.c .
+ (ppi.c): New rule.
+ * gencode.c (printonmatch, think, genopc): Deleted.
+ (MAX_NR_STUFF): Now 42.
+ (tab): Add SH-DSP CPU instructions.
+ Amalgamate ldc / stc / lds / sts instructions with similar
+ bit patterns. Fix opcodes of stc Rm_BANK,@-<REG_N>.
+ Fix semantics of lds.l @<REG_N>+,MACH (no sign extend).
+ (movsxy_tab): New array.
+ For movs, change MMMM field to GGGG, and mmmm field to MMMM.
+ Added entries for movx, movy and parallel processing insns.
+ (ppi_tab): New array.
+ (qfunc): Stabilize sort.
+ (expand_opcode): Handle [01][01]NN, [01][01]xx and [01][01]yy.
+ Handle 'M', 'G' 's' 'X', 'a', 'Y' and 'A'.
+ (dumptable): Now takes three arguments. Changed all callers.
+ Emit just one contigous jump table.
+ (filltable): Now takes an argument. Changed all callers.
+ Make index static.
+ (ppi_moves, expand_ppi_code, ppi_filltable, ppi_gensim): New functions.
+ (gensim_caselist): New function, broken out of gensim.
+ Handle opcode fields 'x', 'y', 's', 'M', 'G', 'X', 'a', and 'Y'.
+ Handle ref '9'.
+ (gensim): Handle 'N' in code field and '8' in refs field.
+ Call gensim_caselist - twice.
+ (ppi_index): New static variable.
+ (main): Unsupport default action.
+ Add dsp support for -x / -s option. Add -p option.
+ * interp.c (sh_jump_table, sh_dsp_table, ppi_table): Declare.
+ (saved_state_type): Rearrange to allow amalgamated ldc / stc /
+ lds / sts to work efficiently.
+ (target_dsp): New static variable.
+ (GBR, VBR, SSR, SPC, MACH, MACL): Reflect saved_state_type change.
+ (FPUL, Rn_BANK, SET_Rn_BANK, M, Q, S, T, SR_BL, SR_RB): Likewise.
+ (SR_MD, SR_RC, SET_SR_BIT, GET_SR, SET_RC, GET_FPSCR): Likewise.
+ (RS, RE, MOD, MOD_ME, DSP_R): Likewise.
+ (set_fpscr1): Likewise. Use target_dsp to check for dsp.
+ (MOD_MSi, SIG_BUS_FETCH): Deleted.
+ (CREG, SREG, PR, SR_MASK_DMY, SR_MASK_DMX, SR_DMY): New macros.
+ (SR_DMX, DSR, MOD_DELTA, GET_DSP_GRD): Likewise.
+ (SET_MOD): Reflect saved_state_type change. Set MOD_DELTA instead
+ of MOD_MS, and encode SR_DMY / SR_DMX into high word of MOD_ME.
+ (set_sr): Reflect saved_state_type change. Fix SR_RB handling.
+ Use SET_MOD.
+ (MA, L, TL, TB): Now controlled by ACE_FAST.
+ (SEXT32): Just cast to int.
+ (SIGN32): Fixed to only shift by 31.
+ (CHECK_INSN_PTR): SIGBUS at insn fetch now represented by insn_end 0.
+ (ppi_insn): Declare.
+ (ppi.c): Include.
+ (init_dsp): Set target_dsp. When it changes, switch end of
+ sh_jump_table with sh_dsp_table.
+ (sim_resume) Don't declare sh_jump_table0. Use sh_jump_table instead.
+ Don't Declare PR if it's #defined.
+ Fix single-stepping (Was broken in Mar 6 16:59:10 patch).
+ (sim_store_register, sim_read_register): Translate accesses to
+ reflect saved_state_type change.
+
+ * interp.c (set_sr): Set sr.
+ (SET_RC, MOD, MOD_MS, MOD_ME, SET_MOD, MOD_MS, MOD_ME): New macros.
+ (set_fpscr1): Don't bank-switch fpu registers when simulating sh-dsp.
+ (DSP_R): Fix definition.
+ (sim_resume): Remove outdated SET_SR use.
+
+ * interp.c (saved_state): New members for struct member asregs:
+ rs, re, insn_end, xram_start, yram_start.
+ (struct loop_bounds): New struct.
+ (SKIP_INSN): New macro.
+ (get_loop_bounds): New function.
+ (endianw): Renamed to global_endianw.
+ (maskw): negated bits.
+ (PC): Now insn_ptr.
+ (SR_MASK_RC, SR_RC_INCREMENT, SR_RC, RAISE_EXCEPTION): New macros.
+ (RS, RE, DSP_R, DSP_GRD, A1, A0, X0, X1, Y0, Y1, M0, A1G): Likewise.
+ (M1, A0G, RIAT, PT2H, PH2T, SET_NIP, CHECK_INSN_PTR): Likewise.
+ (SIG_BUS_FETCH): Likewise
+ (raise_exception, riat_fast): New functions.
+ (raise_buserror, sim_stop): Use raise_exception.
+ (PROCESS_SPECIAL_ADDRESS): Use xram_start / yram_start.
+ (BUSERROR, WRITE_BUSERROR, READ_BUSERROR):
+ Reverse sense of mask argument.
+ (FP_OP, set_dr): Use RAISE_EXCEPTION.
+ (wlat_fast, wwat_fast, wbat_fast, rlat_fast, rwat_fast, rbat_fast):
+ Declare. Remove redundant masking.
+ (wwat_fast, rwat_fast): Add argument endianw. Changed callers.
+ (MA): Updated for change pc -> PC.
+ (Delay_Slot): Use RIAT.
+ (empty): Deleted.
+ (trap): Remove argument little_endian. Add argument endianw.
+ Changed all callers. Use raise_exception.
+ (macw): Add argument endainw. Changed all callers.
+ (init_dsp): New function, extended after broken out of init_pointers.
+ (sim_resume): Replace pc with insn_ptr. Replace little_endian with
+ endianw. Replace nia with nip. Reverse sense of maskb / maskw /
+ maskl. Implement logic for zero-overhead loops. Don't try to
+ interpret garbage when getting a SIGBUS at insn fetch.
+ (sim_open): Call init_dsp.
+ * gencode.c (tab): Use SET_NIP instead of nia = . Use PH2T / PT2H /
+ RAISE_EXCEPTION where appropriate.
+ Add extra cycles for brai, braf , bsr, bsrf, jmp, jsr.
+
+ * interp.c (sim_store_register, sim_fetch_register):
+ Do proper endianness switch.
+
+ * interp.c (saved_state_type): New members for struct member asregs:
+ xymem_select, xmem, ymem, xmem_offset, ymem_offset.
+ (special_address): Delete.
+ (BUSERROR): Now a two-argument predicate.
+ (PROCESS_SPECIAL_ADDRESS, WRITE_BUSERROR, READ_BUSERROR): New macros.
+ (wlat_little, wwat_little, wbat_any, wlat_big, wwat_big): Delete.
+ (process_wlat_addr, process_wwat_addr): New functions.
+ (process_wbat_addr, process_rlat_addr, process_rwat_addr): Likewise.
+ (process_rbat_addr): Likewise.
+ (wlat_fast, wwat_fast, wbat_fast): Use WRITE_BUSERROR.
+ (rlat_little, rwat_little, rbat_any, rlat_big, rwat_big): Delete.
+ (rlat_fast, rwat_fast, rbat_fast): Use READ_BUSERROR.
+ (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Delete SLOW versions.
+ (do_rdat, trap): Delete SLOW code.
+ (SEXT32, SIGN32): New macros.
+ (swap, swap16): Now integer in - integer out. Changed all callers.
+ (strswaplen, strnswap): Delete SLOW versions.
+ (init_pointers): Initialize dsp memory selection (preliminary).
+ (sim_store_register, sim_fetch_register): Use swap instead of
+ big / little endian read / write functions.
+
+ * interp.c (maskl): Deleted.
+ (endianw, endianb): New variables.
+ (special_address): Now inline.
+ (bp_holder): Put raising of buserror there, rename to:
+ (raise_buserror).
+ (BUSERROR): Now yields a value. Changed all users.
+ (wbat_big): Delete.
+ (wlat_fast, wwat_fast, wbat_fast): New functions.
+ (rlat_fast, rwat_fast, rbat_fast): Likewise.
+ (RWAT, RLAT, RBAT, WWAT, WLAT, WBAT): Use new functions.
+ (do_rdat, do_wdat): Likewise. Take maskl argument instead of
+ little_endian one. Changed caller macros.
+ (swap, swap16): Use w[rw]lat_big / w[rw]lat_little directly.
+ (strswaplen, strnswap): New functions.
+ (trap): Use them to fix up endian mismatches;
+ disable SYS_execve and SYS_execv; fix double address translation for
+ SYS_pipe and SYS_stat.
+ (sym_write, sym_read): Add endianness translation.
+ (sym_store_register, sym_fetch_register): Add maskl local variable.
+ (sim_open): Set endianw and endianb.
+
+Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Aug 25 07:55:23 1999 Brendan Kehoe <brendan@cygnus.com>
+
+ * gencode.c (fcnvds <DR_N>,FPUL): Rewrite to use a local anonymous
+ union type, instead of casting to an int* then a float*.
+ (fcnvsd FPUL,<DR_N>): Likewise.
+ (flds <FREG_N>,FPUL): Likewise.
+ (fsts FPUL,<FREG_N>): Likewise.
+
+1999-05-08 Felix Lee <flee@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+1999-04-02 Keith Seitz <keiths@cygnus.com>
+
+ * interp.c (POLL_QUIT_INTERVAL): Define. Used to tweak the
+ frequency at which the poll_quit callback is called.
+ (sim_resume): Use POLL_QUIT_INTERVAL instead of a
+ hard-coded value.
+
+Thu Sep 10 02:16:39 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * interp.c (saved_state.asregs): Add new member pad_dummy.
+ (sim_store_register, sim_fetch_regsiter): Add 1 to rn for use
+ as index into saved_state.asints.
+
+Mon Jun 29 19:35:24 1998 Jason Molenda (crash@bugshack.cygnus.com)
+
+ * interp.c (sim_open): set endianness based on the ABFD if a -E
+ option is not present and we have an ABFD.
+
+Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Sun Apr 26 15:19:48 1998 Tom Tromey <tromey@cygnus.com>
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 24 11:18:35 1998 Tom Tromey <tromey@cygnus.com>
+
+ * configure.in: Don't call sinclude.
+
+Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Feb 17 12:49:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_fetch_register, sim_store_register): Pass in
+ length parameter. Return -1.
+
+Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Oct 22 14:43:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_load): Pass lma_p and sim_write args to
+ sim_load_file.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 9 20:52:21 1997 Felix Lee <flee@cygnus.com>
+
+ * interp.c (sim_resume): poll_quit() at least once per call;
+ otherwise gdb can loop sim_resume() uninterruptably.
+
+Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 2 13:15:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (tab): Order instructions according to SH3 document.
+
+Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Tue Aug 26 10:41:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_kill): Delete.
+ (sim_create_inferior): Add ABFD argument.
+ (sim_load): Move setting of PC from here.
+ (sim_create_inferior): To here.
+
+Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Mon Aug 25 16:17:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Add ABFD argument.
+
+Mon Jun 23 15:49:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (get_dr): Avoid SIGFPE by moving integers instead of
+ FP's around.
+ (set_dr): Ditto.
+
+Mon Jun 23 15:02:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (XD, SET_XD): Delete.
+ (XF, SET_XF, XD_TO_XF): Define, move around registers in either
+ FP bank.
+
+ * gencode.c (fmov): Update.
+
+Sun Jun 22 19:33:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (set_fpscr1): From J"orn Rennecke
+ <amylaar@cygnus.co.uk>, Fix typo. Ditto for comment.
+
+Tue Aug 12 00:19:11 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * interp.c (special_address): New function.
+ (BUSERROR): Call it. Added parameters bits_written and data.
+ Changed all callers.
+ * gencode.c (tab): Fixed ocbwb and pref.
+
+Fri Jun 20 22:03:18 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * interp.c (do_wdat, do_wdat): Fix bug in register number calculation.
+
+Thu Jun 19 00:28:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_create_inferior): Clear registers each time an
+ inferior is started.
+
+Mon Jun 16 14:01:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (*FP, FP_OP, FP_CMP, FP_UNARY): Provide a hook for
+ when a host doesn't support IEEE FP.
+ (*DP): Provide alternative definition that supports 64bit floating
+ point.
+ (target_little_endian): Combine little_endian and little_endian_p.
+ (saved_state_type): Make fpscr and sr simple integers.
+ (SET_FPSCR, GET_FPSCR): Use macros to update fpscr register.
+ (set_fpscr1): New function. Handle swapping when PR / FR bits
+ changed. Call via *_FPSCR macro.
+ (SET_SR*, GET_SR*): Use macro's to access the SR bits - avoids
+ endian problems.
+
+ * gencode.c (tab): Update.
+
+Sun Jun 15 15:22:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (main): Perform basic checks on tab entries.
+
+ * Makefile.in (gencode): Always compile with -g.
+
+Sat Jun 14 13:45:09 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * gencode.c (gensim): Move ref checking code to before `stuff'.
+ For branches with delay slots refs were not being checked.
+
+ * interp.c (sim_resume): Use nia to specify the next instruction
+ address instead of overloading pc.
+ (C): Delete definiton - refer to cycles directly.
+ (SEXT12): New macro - sign extend a 12 bit quantity.
+ (Delay_Slot): Rename from SL.
+
+ * gencode.c (tab): Update/simplify.
+
+ * gencode.c (gensim): Better formatting of output code.
+ (gensim): Replace 10 with constant MAX_NR_STUFF- define as 15.
+ (tab): Sort alphabetically. Break `stuff' into multiple lines.
+
+Fri Jun 13 22:10:13 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * gencode.c (braf, bsrf): Fix branch destination calculation to
+ be in accordance with the documentation.
+
+Fri Jun 13 15:33:53 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * interp.c (init_pointers): Fix little endian test.
+
+Thu Jun 5 12:56:08 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * interp.c (init_pointers): SH4 hardware is always WORDS_BIT_ENDIAN.
+ * gencode (fmov from/to memory): take endian_mismatch into account
+ for 32 bit moves too.
+
+Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * gencode.c (swap.b): Fix treatment of high word.
+
+Wed May 28 23:42:35 1997 J"orn Rennecke <amylaar@cygnus.co.uk>
+
+ * sh/gencode.c,
+ * interp.c: experimental SH4 support.
+ DFmode moves are probaly broken for target little endian.
+
+Tue May 20 10:23:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Add callback argument.
+ (sim_set_callbacks): Delete SIM_DESC argument.
+
+Wed Apr 30 11:38:08 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * Makefile.in (SIM_EXTRA_CLEAN): Define.
+ (clean targets): Delete.
+ (sh-clean): New target.
+
+Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Apr 23 17:55:22 1997 Doug Evans <dje@canuck.cygnus.com>
+
+ * tconfig.in: New file.
+ * interp.c (sim_open): Handle missing arg to -E.
+
Tue Apr 22 08:55:35 1997 Stu Grossman (grossman@critters.cygnus.com)
* Makefile.in: Add clean targets.
projects / thirdparty / binutils-gdb.git / blobdiff