c80 simulator fixes.

[thirdparty/binutils-gdb.git] / sim / tic80 / ChangeLog

diff --git a/sim/tic80/ChangeLog b/sim/tic80/ChangeLog
index 1b1a1678f1e93dd58de8704962f1bfd36fa19193..8df333eed9974698f5d40c2dda179afa4b4777bb 100644 (file)
--- a/sim/tic80/ChangeLog
+++ b/sim/tic80/ChangeLog
@@ -1,3 +1,53 @@
+Mon May 12 11:12:24 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * insns (do_ld): For 64bit loads, always store LSW in rDest, MSW in
+       rDest + 1. Also done by Michael Meissner  <meissner@cygnus.com>
+       (do_st): Converse for store.
+
+       * misc.c (tic80_trace_fpu2i): Correct printf format for int type.
+
+Sun May 11 11:02:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
+
+       * sim-calls.c (sim_stop_reason): Return a SIGINT if keep_running
+       was cleared.
+
+       * interp.c (engine_step): New function.  Single step the simulator
+       taking care of cntrl-c during a step.
+
+       * sim-calls.c (sim_resume): Differentiate between stepping and
+       running so that a cntrl-c during a step is reported.
+
+Sun May 11 10:54:31 1997  Mark Alexander    <marka@cygnus.com>
+
+       * sim-calls.c (sim_fetch_register): Use correct reg base.
+       (sim_store_register): Ditto.
+
+Sun May 11 10:25:14 1997  Michael Meissner  <meissner@cygnus.com>
+
+       * cpu.h (tic80_trace_shift): Add declaration.
+       (TRACE_SHIFT): New macro to trace shift instructions.
+
+       * misc.c (tic80_trace_alu2): Align spacing.
+       (tic80_trace_shift): New function to trace shifts.
+
+       * insns (lmo): Add missing 0b prefix to bits.
+       (do_shift): Use ~ (unsigned32)0, instead of -1.  Use TRACE_SHIFT
+       instead of TRACE_ALU2.
+       (sl r): Use EndMask as is, instead of using Source+1 register.
+       (subu): Operands are unsigned, not signed.
+       (do_{ld,st}): Fix endian problems with ld.d/st.d.
+
+Sat May 10 12:35:47 1997  Michael Meissner  <meissner@cygnus.com>
+
+       * insns (and{.tt,.tf,.ft,.ff}): Immediate values are unsigned, not
+       signed.
+
+Fri May  9 15:47:36 1997  Mike Meissner  <meissner@cygnus.com>
+
+       * insns (cmp_vals,do_cmp): Produce the correct bits as specified
+       by the architecture.
+       (xor): Fix xor immediate patterns to use the correct bits.
+
 Fri May  9 09:55:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
 
        * alu.h (long_immediate): Adjust the CIA delay-pointer as well as