+Wed Nov 25 17:52:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (simops.o): Depends on targ-vals.h
+ * simops.c: Include targ-vals.h instead of
+ libgloss/.../syscall.h. Replace SYS_* with TARGET_SYS_*.
+start-sanitize-v850e
+ (divn, divun, OP_1C007E0, OP_18207E0, OP_1C207E0,OP_18007E0):
+ Replace signed long int with signed32.
+end-sanitize-v850e
+
+Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * interp.c: #include "itable.h".
+ (get_insn_name): New function.
+ (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
+ * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
+
+start-sanitize-v850e
+Wed Aug 26 10:43:01 1998 Nick Clifton <nickc@cygnus.com>
+
+ * v850.igen: Sanitize out references to PSW_US in sld.b and
+ sld.h.
+
+end-sanitize-v850e
+Wed May 6 19:43:27 1998 Doug Evans <devans@canuck.cygnus.com>
+
+ * sim-main.h (INSN_NAME): New arg `cpu'.
+
+Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Sun Apr 26 15:19:14 1998 Tom Tromey <tromey@cygnus.com>
+
+ * acconfig.h: New file.
+ * configure.in: Reverted change of Apr 24; use sinclude again.
+
+Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Apr 24 11:18:08 1998 Tom Tromey <tromey@cygnus.com>
+
+ * configure.in: Don't call sinclude.
+
+Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * sim-main.h (SIM_MAIN_H): Wrap header.
+
+Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Mar 10 15:54:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_stop): Delete, second attempt.
+
+Thu Feb 26 19:09:47 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_info): Delete.
+
+Wed Feb 18 10:47:32 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (TRACE_ALU_INPUT*): Delete. Moved to sim-trace.[hc].
+
+ * simops.c (trace_result): Call trace_generic instead of
+ trace_one_insn.
+ (trace_module): Change variable type to integer.
+ (trace_input): Initialize trace_module with TRACE_ALU_IDX.
+
+ * sim-main.h (trace_module): Change variable decl to integer type.
+ (TRACE_BRANCH*, TRACE_LD, TRACE_ST): Update.
+
+Tue Feb 17 12:51:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_store_register, sim_fetch_register): Pass in
+ length parameter. Return -1.
+
+Tue Feb 3 16:24:42 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (IMEM16, IMEM16_IMMED): Rename IMEM and
+ IMEM_IMMED. To match recent igen change.
+
+Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Jan 30 09:51:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (CPU_CIA): Delete, replaced by.
+ (CIA_SET, CIA_SET): Define.
+
+Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * config.in: Ditto.
+
+Fri Dec 5 09:26:08 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850.igen: Revert break value back to its old value.
+
+Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Dec 3 17:27:19 1997 Nick Clifton <nickc@cygnus.com>
+
+ * v850.igen: Make break have a zero first field, since otherwise
+ it clashes with the DIVH instruction.
+
+Sat Nov 22 21:32:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (OP_10007E0): Rename SIGABRT -> SIM_SIGABRT. Give
+ sim_stopped instead of sim_signalled.
+
+ * v850.igen (BREAK), simops.c (OP_12007E0): Rename SIGTRAP to
+ SIM_SIGTRAP.
+ (illegal): Rename SIGILL to SIM_SIGILL.
+
+ * sim-main.h, simops.c, interp.c: Do not include signal.h.
+
+ * sim-main.h: Include sim-signal.h instead of signal.h.
+ (SIGTRAP, SIGQUIT): Delete definition.
+ (SIG_V850_EXIT): Delete definition.
+
+Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
+
+ * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
+
+Fri Oct 31 10:33:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Check state magic number.
+ (sim-assert.h): Include.
+
+Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * v850.igen: Add model filter field to records.
+
+Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 26 11:56:02 1997 Felix Lee <flee@cygnus.com>
+
+ * sim-main.h: delete null override of SIM_ENGINE_HALT_HOOK and
+ SIM_ENGINE_RESTART_HOOK.
+
+Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Wed Sep 24 17:28:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (WITH_TARGET_WORD_MSB): Delete.
+
+ * configure.in (SIM_AC_OPTION_BITSIZE): Specify 32 bit
+ architecture with MSB == 31.
+
+Wed Sep 24 14:04:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * v850.igen: Make divh insn with RRRRR==0 breakpoint.
+
+Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (SIM_WARNINGS, SIM_ALIGNMENT, SIM_ENDIAN,
+ SIM_HOSTENDIAN, SIM_RESERVED_BITS): Delete, moved to common.
+ (SIM_EXTRA_CFLAGS): Update.
+
+Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+ * configure.in: Really specify NONSTRICT_ALIGNMENT as the default.
+
+Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * configure.in: Specify NONSTRICT_ALIGNMENT as the default.
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Fri Sep 19 10:37:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * v850.igen (disp16): Use EXTEND16 to sign extend disp.
+ (disp22): Only shift left by 1, not 2.
+ ("jmp"): Ensure PC is 2 byte aligned.
+
+ * simops.c, v850.igen: Move "Bcond", "jr", "jarl" code to
+ v850.igen. Fix tracing.
+
+ * simops.c (OP_300, OP_400, OP_500): Move "sdl.b", "sld.h",
+ "sld.w" insns to v850.igen. Fix tracing.
+start-sanitize-v850e
+ (OP_70): Ditto for "sld.hu".
+end-sanitize-v850e
+
+ * v850.igen: Clarify tracing of "sld.b", "sld.h" et.al.
+
+ * simops.c (condition_met): Make global.
+
+ * sim-main.h (TRACE_ALU_INPUT3, TRACE_BRANCH0, TRACE_LD,
+ TRACE_ST): Define.
+start-sanitize-v850e
+ (TRACE_LD_NAME): Define.
+end-sanitize-v850e
+
+start-sanitize-v850e
+ * simops.c: Move "cmov", "cmov imm" to v850.igen, fix.
+
+end-sanitize-v850e
+Wed Sep 17 16:21:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c: Move "mov", "reti", to v850.igen, fix tracing.
+
+ * interp.c (hash): Delete.
+
+ * v850.igen (nop): Really do nothing.
+
+ * interp.c (do_interrupt): Mask interrupts after PSW is saved, not
+ before.
+ * v850.igen (reti): Return to current PC not previous.
+
+start-sanitize-v850e
+Wed Sep 17 14:02:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c: Move "ctret", "bsw", "hsw" to v850.igen, fix tracing.
+ (trace_module): Global, save component/module name across insn.
+
+ * simops.c: Move "bsh" to v850.igen, fix.
+
+ * v850.igen (callt): Load correct number of bytes. Fix tracing.
+ (stsr, ldsr): Correct src, dest fields. Fix tracing.
+ (ctret): Force alignment. Fix tracing.
+
+end-sanitize-v850e
+Tue Sep 16 22:14:01 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (trace_output): Add result argument.
+ (trace_result): New function. Simpler version of trace_output,
+ assumes trace needed.
+ (trace_output): Call trace_result.
+ (trace_output): For IMM_REG_REG, trace correct register.
+ (trace_input): Add case for 16bit immediates.
+ (OP_600, OP_640, OP_680, OP_6C0, OP_6A0): Use.
+
+ * sim-main.h (TRACE_ALU_INPUT, TRACE_ALU_RESULT): Define.
+ (trace_values, trace_name, trace_pc, trace_num_values): Make
+ global.
+ (GR, SR): Define.
+
+ v850.insn (movea, stsr): Use.
+start-sanitize-v850e
+ (sxb, sxh, zxb, zxh): Ditto.
+end-sanitize-v850e
+
+Tue Sep 16 21:14:01 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c: Move "movea" from here.
+ * v850.igen: To here.
+
+ * v850.igen (simm16): Define, sign extend imm16.
+ (uimm16): Define, no sign extension.
+ (addi, andi, movea, movhi, mulhi, ori, satsubi, xori): Use.
+
+start-sanitize-v850e
+ * simops.c: Move "sxh", "switch", "sxb", "callt", "dispose",
+ "mov32" from here.
+ * v850.igen: To here.
+ (switch): Fix off by two error in NIA calc.
+
+end-sanitize-v850e
+Tue Sep 16 15:14:01 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (trace_pc, trace_name, trace_values, trace_num_values):
+ New static globals.
+ (trace_input): Just save pc, name and values for trace_output.
+ (trace_output): Write trace values to a buffer. Use
+ trace_one_insn to print trace info and buffer.
+ (SIZE_OPERANDS, SIZE_LOCATION): Delete.
+
+Tue Sep 16 09:02:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-main.h (struct _sim_cpu): Add psw_mask so that reserved bits
+ can be masked out.
+
+ * simops.c (OP_2007E0, OP_4007E0): Move "ldsr", "stsr"
+ instructions from here.
+ * v850.igen (ldsr, stsr): To here. Mask out reserved bits when
+ setting PSW.
+
+ * interp.c (sim_open): Set psw_mask if machine known.
+
+Tue Sep 16 10:20:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+start-sanitize-v850e
+ * v850-dc: Add rule to diferentiate between breakpoint and divh.
+ * v850.igen (break): New instruction, breakpoint simulator.
+
+end-sanitize-v850e
+ * v850.igen (breakpoint): Enable. Change to a 32bit instruction.
+
+start-sanitize-v850e
+Mon Sep 15 18:44:05 1997 Jim Wilson <wilson@cygnus.com>
+
+ * simops.c (Multiply64): Don't store into register zero.
+
+end-sanitize-v850e
+Tue Sep 16 09:02:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * Makefile.in (semantics.o): Add dependency.
+
+ * sim-main.h (SAVE_1, SAVE_2): Perform backward compatible save,
+ do not adjust CIA/NIA.
+
+Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+start-sanitize-v850e
+ * simops.c (OP_300, OP_400, OP_70): Make behavour depend on PSW[US].
+
+ * simops.c: Move "divun", "sld.bu", "divhn", "divhun", "divn",
+ "divun", "pushml" code from here to v850.igen.
+ (divun): Make global.
+ (type3_regs): Make global
+
+ * v850.igen: Move simops.c code to here.
+
+ * interp.c (sim_create_inferior): For v850eq set US bit by
+ default.
+
+ * interp.c (sim_open): Don't set arch, now set by
+ sim_analyze_program.
+
+end-sanitize-v850e
+ * configure: Regenerated to track ../common/aclocal.m4 changes.
+
+Mon Sep 15 14:39:34 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (op_types): Move from here.
+ sim-main.h: To here.
+
+ * sim-main.h (trace_input, trace_output), simops.c: Make global.
+
+ * simops.c (OP_60): Move "jmp" code from here.
+ * v850.igen (jmp): To here.
+
+start-sanitize-v850e
+ * simops.c (OP_60): Move "sld.bu" code from here.
+ * v850.igen (sld.bu): To here.
+
+Fri Sep 12 15:11:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * v850.igen (prepare, ...): Add to v850eq architecture.
+
+ * interp.c (sim_open): Default to v850eq.
+
+ * interp.c (sim_open): Default to v850e.
+end-sanitize-v850e
+ * sim-main.h (signal.h): Include.
+
+ * v850.igen (illegal): Report/halt illegal instructions.
+
+ * Makefile.in (SIM_EXTRA_CFLAGS): Add SIM_RESERVED_BITS.
+
+ * configure.in: Add reserved bits option.
+ * configure: Regenerate.
+
+Thu Sep 11 08:40:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_open): Use sim_do_commandf instead of asprintf.
+
+ * sim-main.h (INSN_NAME):
+
+ * Makefile.in (INCLUDE): Add SIM_EXTRA_DEPS.
+ (SIM_EXTRA_DEPS): Add itable.h
+ (tmp-gencode): Does not depend on simops.h
+
+ * sim-main.h (itable.h): Include.
+ (MAX_INSNS, INSN_NAME): Define.
+
+ * interp.c: Compute inttype from the interrupt_names index that
+ was passed in.
+
+Wed Sep 10 10:25:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * simops.c (trace_input): Use trace_printf instead of
+ sim_io_printf.
+ (trace_output): Ditto.
+ (trace_input): Only trace when TRACE_ALU_P. Delete code
+ disasembling instruction.
+ (trace_output): Only trace when TRACE_ALU_P.
+
Tue Sep 9 01:29:50 1997 Andrew Cagney <cagney@b1.cygnus.com>
* simops.c (trace_input, trace_output): Use sim_io_printf.
* simops.c (unsigned divide instructions): S bit set if result has
top bit set.
-start-sanitize-v850eq
+end-sanitize-v850e
* simops.c (pushml, pushmh, popml, popmh): Lower numbered
registers go to higher numbered address.
-end-sanitize-v850eq
-end-sanitize-v850e
Wed Aug 20 13:56:35 1997 Nick Clifton <nickc@cygnus.com>
* simops.c (OP_107E0, OP_107F0, OP_307E0, OP_307F0): Use correct
interpretation of SR bit in list18 structure.
-start-sanitize-v850eq
(divn, divun): New functions to perform N step divide functions.
-end-sanitize-v850eq
-start-sanitize-v850eq
+start-sanitize-v850e
Mon Aug 18 10:59:02 1997 Nick Clifton <nickc@cygnus.com>
* simops.c (OP_300, OP_400, OP_60, OP_70): Support variant opcodes
with US bit set in the PSW.
-start-sanitize-v850eq
+end-sanitize-v850e
Wed Aug 13 19:06:55 1997 Nick Clifton <nickc@cygnus.com>
* simops.c: Add support for v850e instructions.
- * .Sanitize (Do-first, Do-last): Add support for keep-v850e
- command line option.
-
-end-sanitize-v850e
-
-start-sanitize-v850eq
- * .Sanitize (Do-first, Do-last): Add support for keep-v850eq
- command line option.
-
* simops.c: Add support for v850eq instructions.
-end-sanitize-v850eq
+end-sanitize-v850e
Tue May 20 10:24:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
projects / thirdparty / binutils-gdb.git / blobdiff