Move xen patchset to new version's subdir.

[ipfire-2.x.git] / src / patches / suse-2.6.27.31 / patches.drivers / e1000e_add_ECC

diff --git a/src/patches/suse-2.6.27.31/patches.drivers/e1000e_add_ECC b/src/patches/suse-2.6.27.31/patches.drivers/e1000e_add_ECC
new file mode 100644 (file)
index 0000000..158d177
--- /dev/null
+++ b/src/patches/suse-2.6.27.31/patches.drivers/e1000e_add_ECC
@@ -0,0 +1,62 @@
+From: John Ronciak <john.ronciak@intel.com>
+Acked-by: Karsten Keil <kkeil@novell.com>
+Subject: e1000e: enable ECC
+Bugzilla: bnc#445829
+
+Small fix accepted upstream to enable ECC in Ophir HW in the e1000e driver. 
+I'll attach the patch next.  IBM is asking for us to get this fix into the
+disti releases.
+
+ drivers/net/e1000e/82571.c   |    6 ++++++
+ drivers/net/e1000e/defines.h |    7 +++++++
+ drivers/net/e1000e/hw.h      |    1 +
+ 3 files changed, 14 insertions(+), 0 deletions(-)
+
+
+Index: linux-2.6.27/drivers/net/e1000e/82571.c
+===================================================================
+--- linux-2.6.27.orig/drivers/net/e1000e/82571.c
++++ linux-2.6.27/drivers/net/e1000e/82571.c
+@@ -973,6 +973,12 @@ static void e1000_initialize_hw_bits_825
+               ew32(CTRL_EXT, reg);
+       }
+ 
++      if (hw->mac.type == e1000_82571) {
++              reg = er32(PBA_ECC);
++              reg |= E1000_PBA_ECC_CORR_EN;
++              ew32(PBA_ECC, reg);
++      }
++
+       /* PCI-Ex Control Register */
+       if (hw->mac.type == e1000_82574) {
+               reg = er32(GCR);
+Index: linux-2.6.27/drivers/net/e1000e/defines.h
+===================================================================
+--- linux-2.6.27.orig/drivers/net/e1000e/defines.h
++++ linux-2.6.27/drivers/net/e1000e/defines.h
+@@ -372,6 +372,13 @@
+ #define E1000_ICR_TXQ1          0x00800000 /* Tx Queue 1 Interrupt */
+ #define E1000_ICR_OTHER         0x01000000 /* Other Interrupts */
+ 
++/* PBA ECC Register */
++#define E1000_PBA_ECC_COUNTER_MASK  0xFFF00000 /* ECC counter mask */
++#define E1000_PBA_ECC_COUNTER_SHIFT 20         /* ECC counter shift value */
++#define E1000_PBA_ECC_CORR_EN       0x00000001 /* ECC correction enable */
++#define E1000_PBA_ECC_STAT_CLR      0x00000002 /* Clear ECC error counter */
++#define E1000_PBA_ECC_INT_EN        0x00000004 /* Enable ICR bit 5 for ECC */
++
+ /*
+  * This defines the bits that are set in the Interrupt Mask
+  * Set/Read Register.  Each bit is documented below:
+Index: linux-2.6.27/drivers/net/e1000e/hw.h
+===================================================================
+--- linux-2.6.27.orig/drivers/net/e1000e/hw.h
++++ linux-2.6.27/drivers/net/e1000e/hw.h
+@@ -87,6 +87,7 @@ enum e1e_registers {
+       E1000_EEMNGCTL = 0x01010, /* MNG EEprom Control */
+       E1000_EEWR     = 0x0102C, /* EEPROM Write Register - RW */
+       E1000_FLOP     = 0x0103C, /* FLASH Opcode Register */
++      E1000_PBA_ECC  = 0x01100, /* PBA ECC Register */
+       E1000_ERT      = 0x02008, /* Early Rx Threshold - RW */
+       E1000_FCRTL    = 0x02160, /* Flow Control Receive Threshold Low - RW */
+       E1000_FCRTH    = 0x02168, /* Flow Control Receive Threshold High - RW */