--- /dev/null
+From: Seth Heasley <seth.heasley@intel.com>
+Date: Thu, 28 Aug 2008 22:40:59 +0000 (-0700)
+Subject: x86/PCI: irq and pci_ids patch for Intel Ibex Peak DeviceIDs
+X-Git-Tag: v2.6.28-rc1~77^2~28
+X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=37a84ec668ba251ae02cf2c2c664baf6b247ae1f
+References: bnc#415383
+
+x86/PCI: irq and pci_ids patch for Intel Ibex Peak DeviceIDs
+
+This patch updates the Intel Ibex Peak (PCH) LPC and SMBus Controller
+DeviceIDs.
+
+The LPC Controller ID is set by Firmware within the range of
+0x3b00-3b1f. This range is included in pci_ids.h using min and max
+values, and irq.c now has code to handle the range (in lieu of 32
+additions to a SWITCH statement).
+
+The SMBus Controller ID is a fixed-value and will not change.
+
+Signed-off-by: Seth Heasley <seth.heasley@intel.com>
+Acked-by: Jean Delvare <khali@linux-fr.org>
+Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
+Acked-by: John Jolly <jjolly@suse.de>
+---
+
+---
+ arch/x86/pci/irq.c | 11 +++++++++--
+ include/linux/pci_ids.h | 6 +++---
+ 2 files changed, 12 insertions(+), 5 deletions(-)
+
+--- a/arch/x86/pci/irq.c
++++ b/arch/x86/pci/irq.c
+@@ -591,13 +591,20 @@ static __init int intel_router_probe(str
+ case PCI_DEVICE_ID_INTEL_ICH10_1:
+ case PCI_DEVICE_ID_INTEL_ICH10_2:
+ case PCI_DEVICE_ID_INTEL_ICH10_3:
+- case PCI_DEVICE_ID_INTEL_PCH_0:
+- case PCI_DEVICE_ID_INTEL_PCH_1:
+ r->name = "PIIX/ICH";
+ r->get = pirq_piix_get;
+ r->set = pirq_piix_set;
+ return 1;
+ }
++
++ if ((device >= PCI_DEVICE_ID_INTEL_PCH_LPC_MIN) &&
++ (device <= PCI_DEVICE_ID_INTEL_PCH_LPC_MAX)) {
++ r->name = "PIIX/ICH";
++ r->get = pirq_piix_get;
++ r->set = pirq_piix_set;
++ return 1;
++ }
++
+ return 0;
+ }
+
+--- a/include/linux/pci_ids.h
++++ b/include/linux/pci_ids.h
+@@ -2446,9 +2446,9 @@
+ #define PCI_DEVICE_ID_INTEL_ICH10_3 0x3a1a
+ #define PCI_DEVICE_ID_INTEL_ICH10_4 0x3a30
+ #define PCI_DEVICE_ID_INTEL_ICH10_5 0x3a60
+-#define PCI_DEVICE_ID_INTEL_PCH_0 0x3b10
+-#define PCI_DEVICE_ID_INTEL_PCH_1 0x3b11
+-#define PCI_DEVICE_ID_INTEL_PCH_2 0x3b30
++#define PCI_DEVICE_ID_INTEL_PCH_LPC_MIN 0x3b00
++#define PCI_DEVICE_ID_INTEL_PCH_LPC_MAX 0x3b1f
++#define PCI_DEVICE_ID_INTEL_PCH_SMBUS 0x3b30
+ #define PCI_DEVICE_ID_INTEL_IOAT_SNB 0x402f
+ #define PCI_DEVICE_ID_INTEL_5100_16 0x65f0
+ #define PCI_DEVICE_ID_INTEL_5100_21 0x65f5