aarch64/fpu: Add vector variants of erf

[thirdparty/glibc.git] / sysdeps / aarch64 / fpu / test-double-advsimd-wrappers.c

diff --git a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
index 3b6b1e343d55459aa2f225e3097dc9443d2efa9e..41fdb92d7ea6e707a4889f22e96e024f0c2eec0f 100644 (file)
--- a/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
+++ b/sysdeps/aarch64/fpu/test-double-advsimd-wrappers.c
@@ -1,6 +1,6 @@
 /* Scalar wrappers for double-precision Advanced SIMD vector math functions.
 
-   Copyright (C) 2023 Free Software Foundation, Inc.
+   Copyright (C) 2023-2024 Free Software Foundation, Inc.
    This file is part of the GNU C Library.
 
    The GNU C Library is free software; you can redistribute it and/or
@@ -23,7 +23,19 @@
 
 #define VEC_TYPE float64x2_t
 
+VPCS_VECTOR_WRAPPER (acos_advsimd, _ZGVnN2v_acos)
+VPCS_VECTOR_WRAPPER (asin_advsimd, _ZGVnN2v_asin)
+VPCS_VECTOR_WRAPPER (atan_advsimd, _ZGVnN2v_atan)
+VPCS_VECTOR_WRAPPER_ff (atan2_advsimd, _ZGVnN2vv_atan2)
 VPCS_VECTOR_WRAPPER (cos_advsimd, _ZGVnN2v_cos)
+VPCS_VECTOR_WRAPPER (erf_advsimd, _ZGVnN2v_erf)
 VPCS_VECTOR_WRAPPER (exp_advsimd, _ZGVnN2v_exp)
+VPCS_VECTOR_WRAPPER (exp10_advsimd, _ZGVnN2v_exp10)
+VPCS_VECTOR_WRAPPER (exp2_advsimd, _ZGVnN2v_exp2)
+VPCS_VECTOR_WRAPPER (expm1_advsimd, _ZGVnN2v_expm1)
 VPCS_VECTOR_WRAPPER (log_advsimd, _ZGVnN2v_log)
+VPCS_VECTOR_WRAPPER (log10_advsimd, _ZGVnN2v_log10)
+VPCS_VECTOR_WRAPPER (log1p_advsimd, _ZGVnN2v_log1p)
+VPCS_VECTOR_WRAPPER (log2_advsimd, _ZGVnN2v_log2)
 VPCS_VECTOR_WRAPPER (sin_advsimd, _ZGVnN2v_sin)
+VPCS_VECTOR_WRAPPER (tan_advsimd, _ZGVnN2v_tan)