X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=board%2Fgumstix%2Fpepper%2Fboard.c;fp=board%2Fgumstix%2Fpepper%2Fboard.c;h=d76c28bd3cc3ff0a24f78c025ec2a0977704e4e5;hb=5e90470a866875984820dbc48c9b881e0ce773ba;hp=beb2fac374594fe0d32fb03bf97ce2376affaf39;hpb=8f0b1e24e2887713bdcbf35b08902e9555ee7b92;p=people%2Fms%2Fu-boot.git

diff --git a/board/gumstix/pepper/board.c b/board/gumstix/pepper/board.c
index beb2fac374..d76c28bd3c 100644
--- a/board/gumstix/pepper/board.c
+++ b/board/gumstix/pepper/board.c
@@ -33,6 +33,46 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #ifdef CONFIG_SPL_BUILD
+#define OSC	(V_OSCK/1000000)
+
+static const struct ddr_data ddr3_data = {
+	.datardsratio0 = MT41K256M16HA125E_RD_DQS,
+	.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
+	.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
+	.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
+};
+
+static const struct cmd_control ddr3_cmd_ctrl_data = {
+	.cmd0csratio = MT41K256M16HA125E_RATIO,
+	.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd1csratio = MT41K256M16HA125E_RATIO,
+	.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+
+	.cmd2csratio = MT41K256M16HA125E_RATIO,
+	.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
+};
+
+static struct emif_regs ddr3_emif_reg_data = {
+	.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
+	.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
+	.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
+	.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
+	.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
+	.zq_config = MT41K256M16HA125E_ZQ_CFG,
+	.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
+};
+
+const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
+
+const struct ctrl_ioregs ioregs_ddr3 = {
+	.cm0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+	.cm2ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt0ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+	.dt1ioctl               = MT41K256M16HA125E_IOCTRL_VALUE,
+};
+
 static const struct ddr_data ddr2_data = {
 	.datardsratio0 = MT47H128M16RT25E_RD_DQS,
 	.datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
@@ -56,6 +96,70 @@ static const struct emif_regs ddr2_emif_reg_data = {
 	.emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
 };
 
+const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
+
+const struct ctrl_ioregs ioregs_ddr2 = {
+	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
+};
+
+static int read_eeprom(struct pepper_board_id *header)
+{
+	if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
+		return -ENODEV;
+	}
+
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
+		sizeof(struct pepper_board_id))) {
+		return -EIO;
+	}
+
+	return 0;
+}
+
+const struct dpll_params *get_dpll_ddr_params(void)
+{
+	struct pepper_board_id header;
+
+	enable_i2c0_pin_mux();
+	i2c_set_bus_num(0);
+
+	if (read_eeprom(&header) < 0)
+		return &dpll_ddr3;
+
+	switch (header.device_vendor) {
+	case GUMSTIX_PEPPER:
+		return &dpll_ddr2;
+	case GUMSTIX_PEPPER_DVI:
+		return &dpll_ddr3;
+	default:
+		return &dpll_ddr3;
+	}
+}
+
+void sdram_init(void)
+{
+	const struct dpll_params *dpll = get_dpll_ddr_params();
+
+	/*
+	 * Here we are assuming PLL clock reveals the type of RAM.
+	 * DDR2 = 266
+	 * DDR3 = 400
+	 * Note that DDR3 is the default.
+	 */
+	if (dpll->m == 266) {
+		config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
+			&ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
+	}
+	else if (dpll->m == 400) {
+		config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
+			&ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
+	}
+}
+
 #ifdef CONFIG_SPL_OS_BOOT
 int spl_start_uboot(void)
 {
@@ -64,14 +168,6 @@ int spl_start_uboot(void)
 }
 #endif
 
-#define OSC	(V_OSCK/1000000)
-const struct dpll_params dpll_ddr = {266, OSC-1, 1, -1, -1, -1, -1};
-
-const struct dpll_params *get_dpll_ddr_params(void)
-{
-	return &dpll_ddr;
-}
-
 void set_uart_mux_conf(void)
 {
 	enable_uart0_pin_mux();
@@ -82,19 +178,7 @@ void set_mux_conf_regs(void)
 	enable_board_pin_mux();
 }
 
-const struct ctrl_ioregs ioregs = {
-	.cm0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.cm1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.cm2ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.dt0ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-	.dt1ioctl		= MT47H128M16RT25E_IOCTRL_VALUE,
-};
 
-void sdram_init(void)
-{
-	config_ddr(266, &ioregs, &ddr2_data,
-		   &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
-}
 #endif
 
 int board_init(void)