X-Git-Url: http://git.ipfire.org/?a=blobdiff_plain;f=sim%2Faarch64%2Fcpustate.c;fp=sim%2Faarch64%2Fcpustate.c;h=0656af546cdbcae7d2fc3534f44210833c616941;hb=5ab6d79e708633e8e602e6363bae46002bfc3831;hp=50a83c927d1b656c3c2fd89934945f039e184090;hpb=cc651c1cdd00dc821a0906dc648e89d71dcfc963;p=thirdparty%2Fbinutils-gdb.git

diff --git a/sim/aarch64/cpustate.c b/sim/aarch64/cpustate.c
index 50a83c927d1..0656af546cd 100644
--- a/sim/aarch64/cpustate.c
+++ b/sim/aarch64/cpustate.c
@@ -277,6 +277,21 @@ aarch64_clear_CPSR_bit (sim_cpu *cpu, FlagMask bit)
 		    decode_cpsr (old_flags), decode_cpsr (cpu->CPSR));
 }
 
+float
+aarch64_get_FP_half (sim_cpu *cpu, VReg reg)
+{
+  union
+  {
+    uint16_t h[2];
+    float    f;
+  } u;
+
+  u.h[0] = cpu->fr[reg].h[0];
+  u.h[1] = 0;
+  return u.f;
+}
+
+
 float
 aarch64_get_FP_float (sim_cpu *cpu, VReg reg)
 {
@@ -296,6 +311,21 @@ aarch64_get_FP_long_double (sim_cpu *cpu, VReg reg, FRegister *a)
   a->v[1] = cpu->fr[reg].v[1];
 }
 
+void
+aarch64_set_FP_half (sim_cpu *cpu, VReg reg, float val)
+{
+  union
+  {
+    uint16_t h[2];
+    float    f;
+  } u;
+
+  u.f = val;
+  cpu->fr[reg].h[0] = u.h[0];
+  cpu->fr[reg].h[1] = 0;
+}
+
+
 void
 aarch64_set_FP_float (sim_cpu *cpu, VReg reg, float val)
 {
@@ -541,3 +571,24 @@ aarch64_test_FPSR_bit (sim_cpu *cpu, FPSRMask flag)
 {
   return cpu->FPSR & flag;
 }
+
+uint64_t
+aarch64_get_thread_id (sim_cpu * cpu)
+{
+  return cpu->tpidr;
+}
+
+uint32_t
+aarch64_get_FPCR (sim_cpu * cpu)
+{
+  return cpu->FPCR;
+}
+
+void
+aarch64_set_FPCR (sim_cpu * cpu, uint32_t val)
+{
+  if (cpu->FPCR != val)
+    TRACE_REGISTER (cpu,
+		    "FPCR changes from %x to %x", cpu->FPCR, val);
+  cpu->FPCR = val;
+}