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(parent: 1d3f828) | patch
x86: also optimize zeroing-masking variants of insns
authorJan Beulich <jbeulich@novell.com>
Thu, 26 Apr 2018 06:53:20 +0000 (08:53 +0200)
committerJan Beulich <jbeulich@suse.com>
Thu, 26 Apr 2018 06:53:20 +0000 (08:53 +0200)
commit7a69eac330adff3913a8698eac450cc7968ba8b0
treeb18ae6062dbee55c24b75a279a83558f730dfec7tree | snapshot
parent1d3f82868db8881cd9ce79ad151fb0a7ebeb2c5acommit | diff
x86: also optimize zeroing-masking variants of insns

When zeroing an element of a register it doesn't matter whether the zero
results from the actual operation (xor, sub, or nand) or from the
zeroing-masking taking effect due to a clear mask register bit.
gas/ChangeLog diff | blob | blame | history
gas/config/tc-i386.c diff | blob | blame | history
gas/testsuite/gas/i386/optimize-1.d diff | blob | blame | history
gas/testsuite/gas/i386/optimize-4.d diff | blob | blame | history
gas/testsuite/gas/i386/optimize-5.d diff | blob | blame | history
gas/testsuite/gas/i386/x86-64-optimize-2.d diff | blob | blame | history
gas/testsuite/gas/i386/x86-64-optimize-5.d diff | blob | blame | history
gas/testsuite/gas/i386/x86-64-optimize-6.d diff | blob | blame | history
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