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author	Mike Frysinger <vapier@gentoo.org>
	Wed, 24 Jun 2015 13:52:21 +0000 (19:37 +0545)
committer	Mike Frysinger <vapier@gentoo.org>
	Wed, 24 Jun 2015 14:40:17 +0000 (10:40 -0400)
commit	fa8f87e53b68881c5e3aab296b517203407c4378
tree	6eb1f8996ae765cd81589f6c8e8f318ee92a673b	tree \| snapshot
parent	cf304b56ca48631836bdc4035134b5b5ec3b9d49	commit \| diff

sim: trace: add a basic cpu register class

The bfin/msp430 ports already had trace logic set up for reading/writing
cpu registers, albeit using different unrelated levels (core & vpu). Add
a proper register class for these and for other ports.

sim/bfin/ChangeLog		diff \| blob \| blame \| history
sim/bfin/interp.c		diff \| blob \| blame \| history
sim/bfin/sim-main.h		diff \| blob \| blame \| history
sim/common/ChangeLog		diff \| blob \| blame \| history
sim/common/sim-trace.c		diff \| blob \| blame \| history
sim/common/sim-trace.h		diff \| blob \| blame \| history
sim/msp430/ChangeLog		diff \| blob \| blame \| history
sim/msp430/msp430-sim.c		diff \| blob \| blame \| history

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