]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
aarch64: fp8 convert and scale - add sme2 insn variants
authorVictor Do Nascimento <vicdon01@e133397.arm.com>
Tue, 27 Feb 2024 16:17:25 +0000 (16:17 +0000)
committerVictor Do Nascimento <victor.donascimento@arm.com>
Thu, 16 May 2024 12:22:30 +0000 (13:22 +0100)
commita09771e687bacc24163d1f1978cc46d9c72b3a08
treebbe9f361a5748eb6df0c558f3595aa2fb4e2f30f
parenteef66d27fcdc55c83a63a17f295409bb4a13688b
aarch64: fp8 convert and scale - add sme2 insn variants

Add the SME2 variant of the FP8 convert and scale
instructions, enabled at assembly-time using the `+sme2+fp8'
architectural extension flag.  More specifically, support is
added for the following instructions:

Multi-vector floating-point convert from FP8 to
BFloat16 (in-order):
-----------------------------------------------

  - bf1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
  - bf2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B

Multi-vector floating-point convert from FP8 to
deinterleaved BFloat16:
-----------------------------------------------

  - bf1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
  - bf2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B

Multi-vector floating-point convert from BFloat16
to packed FP8 format:
-------------------------------------------------

  - bfcvt <Zd>.B, { <Zn1>.H-<Zn2>.H }

Multi-vector floating-point convert from FP8 to
half-precision (in-order):
-----------------------------------------------

  - f1cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B
  - f2cvt { <Zd1>.H-<Zd2>.H }, <Zn>.B

Multi-vector floating-point convert from FP8 to
deinterleaved half-precision:
-----------------------------------------------

  - f1cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B
  - f2cvtl { <Zd1>.H-<Zd2>.H }, <Zn>.B

Multi-vector floating-point convert from half-precision
to packed FP8 format:
-------------------------------------------------------

fcvt_2h

Multi-vector floating-point convert from single-precision
to packed FP8 format:
---------------------------------------------------------
fcvt_4s

Multi-vector floating-point convert from single-precision
to interleaved FP8 format:
---------------------------------------------------------

  - fcvtn <Zd>.B, { <Zn1>.S-<Zn4>.S }

Multi-vector floating-point adjust exponent by vector:
------------------------------------------------------

  - fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
   <Zm>.H
  - fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
   <Zm>.S
  - fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
   <Zm>.D

Multi-vector floating-point adjust exponent:
--------------------------------------------

  - fscale { <Zdn1>.H-<Zdn2>.H }, { <Zdn1>.H-<Zdn2>.H },
   { <Zm1>.H - <Zm2>.H }
  - fscale { <Zdn1>.S-<Zdn2>.S }, { <Zdn1>.S-<Zdn2>.S },
   { <Zm1>.S - <Zm2>.S }
  - fscale { <Zdn1>.D-<Zdn2>.D }, { <Zdn1>.D-<Zdn2>.D },
   { <Zm1>.D - <Zm2>.D }
gas/testsuite/gas/aarch64/sme2-24-invalid.l
gas/testsuite/gas/aarch64/sme2-fp8-fail.d [new file with mode: 0644]
gas/testsuite/gas/aarch64/sme2-fp8-fail.l [new file with mode: 0644]
gas/testsuite/gas/aarch64/sme2-fp8-fail.s [new file with mode: 0644]
gas/testsuite/gas/aarch64/sme2-fp8.d [new file with mode: 0644]
gas/testsuite/gas/aarch64/sme2-fp8.s [new file with mode: 0644]
opcodes/aarch64-dis-2.c
opcodes/aarch64-tbl.h