]> git.ipfire.org Git - thirdparty/binutils-gdb.git/commit
RISC-V: Add support for the Zvbb ISA extension
authorChristoph Müllner <christoph.muellner@vrull.eu>
Fri, 30 Jun 2023 20:43:33 +0000 (22:43 +0200)
committerChristoph Müllner <christoph.muellner@vrull.eu>
Sat, 1 Jul 2023 05:14:45 +0000 (07:14 +0200)
commitc8cb37347fde3ae12c943c2133a1043eece4c127
tree0605dc42c2c8534960374271cd486567a2ca8a0d
parent4ced24d1907a8ce28868cc3fe403d769197352be
RISC-V: Add support for the Zvbb ISA extension

Zvbb is part of the vector crypto extensions.

This extension adds the following instructions:
- vandn.[vv,vx]
- vbrev.v
- vbrev8.v
- vrev8.v
- vclz.v
- vctz.v
- vcpop.v
- vrol.[vv,vx]
- vror.[vv,vx,vi]
- vwsll.[vv,vx,vi]

bfd/ChangeLog:

* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction
class support for Zvbb.
(riscv_multi_subset_supports_ext): Likewise.

gas/ChangeLog:

* config/tc-riscv.c (validate_riscv_insn): Add 'l' as new format
string directive.
(riscv_ip): Likewise.
* testsuite/gas/riscv/zvbb.d: New test.
* testsuite/gas/riscv/zvbb.s: New test.

include/ChangeLog:

* opcode/riscv-opc.h (MATCH_VANDN_VV): New.
(MASK_VANDN_VV): New.
(MATCH_VANDN_VX): New.
(MASK_VANDN_VX): New.
(MATCH_VBREV8_V): New.
(MASK_VBREV8_V): New.
(MATCH_VBREV_V): New.
(MASK_VBREV_V): New.
(MATCH_VCLZ_V): New.
(MASK_VCLZ_V): New.
(MATCH_VCPOP_V): New.
(MASK_VCPOP_V): New.
(MATCH_VCTZ_V): New.
(MASK_VCTZ_V): New.
(MATCH_VREV8_V): New.
(MASK_VREV8_V): New.
(MATCH_VROL_VV): New.
(MASK_VROL_VV): New.
(MATCH_VROL_VX): New.
(MASK_VROL_VX): New.
(MATCH_VROR_VI): New.
(MASK_VROR_VI): New.
(MATCH_VROR_VV): New.
(MASK_VROR_VV): New.
(MATCH_VROR_VX): New.
(MASK_VROR_VX): New.
(MATCH_VWSLL_VI): New.
(MASK_VWSLL_VI): New.
(MATCH_VWSLL_VV): New.
(MASK_VWSLL_VV): New.
(MATCH_VWSLL_VX): New.
(MASK_VWSLL_VX): New.
(DECLARE_INSN): New.
* opcode/riscv.h (EXTRACT_RVV_VI_UIMM6): New.
(ENCODE_RVV_VI_UIMM6): New.
(enum riscv_insn_class): Add instruction class for Zvbb.

opcodes/ChangeLog:

* riscv-dis.c (print_insn_args): Add 'l' as new format string
directive.
* riscv-opc.c: Add Zvbb instructions.

Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
bfd/elfxx-riscv.c
gas/config/tc-riscv.c
gas/testsuite/gas/riscv/zvbb.d [new file with mode: 0644]
gas/testsuite/gas/riscv/zvbb.s [new file with mode: 0644]
include/opcode/riscv-opc.h
include/opcode/riscv.h
opcodes/riscv-dis.c
opcodes/riscv-opc.c