Use the existing instruction to determine the RISC-V breakpoint kind.

Use the existing instruction to determine the RISC-V breakpoint kind.

RISC-V supports instructions of varying lengths.  Standard existing
instructions in the base ISA are 4 bytes in length, but the 'C'
extension adds support for compressed, 2 byte instructions.  RISC-V
supports two different breakpoint instructions: EBREAK is a 4 byte
instruction in the base ISA, and C.EBREAK is a 2 byte instruction only
available on processors implementing the 'C' extension.  Using EBREAK
to set breakpoints on compressed instructions causes problems as the
second half of EBREAK will overwrite the first 2 bytes of the
following instruction breaking other threads in the process if their
PC is the following instruction.  Thus, breakpoints on compressed
instructions need to use C.EBREAK instead of EBREAK.

Previously, the riscv architecture checked the MISA register to
determine if the 'C' extension was available.  If so, it used C.EBREAK
for all breakpoints.  However, the MISA register is not necessarily
available to supervisor mode operating systems.  While native targets
could provide a fake MISA register value, this patch instead examines
the existing instruction at a breakpoint target to determine which
breakpoint instruction to use.  If the existing instruction is a
compressed instruction, C.EBREAK is used, otherwise EBREAK is used.

gdb/ChangeLog:

	* disasm-selftests.c (print_one_insn_test): Add bfd_arch_riscv to
	case with explicit breakpoint kind.
	* riscv-tdep.c (show_use_compressed_breakpoints): Remove
	'additional_info' and related logic.
	(riscv_debug_breakpoints): New variable.
	(riscv_breakpoint_kind_from_pc): Use the length of the existing
	instruction to determine the breakpoint kind.
	(_initialize_riscv_tdep): Add 'set/show debug riscv breakpoints'
	flag.  Update description of 'set/show riscv
	use-compressed-breakpoints' flag.