* simops.c: Fix typos in bset insns. Fix arguments to store_mem

        for bset imm8,(d8,an) and bclr imm8,(d8,an).
Bugs exposed by new compiler optimizations.

diff --git a/sim/mn10300/ChangeLog b/sim/mn10300/ChangeLog
index 7366720902f0ea2f33ec8a88f818351aa72e4a5e..d6010654246c687c64589fa4d8d7fe4cf7e1e445 100644 (file)
--- a/sim/mn10300/ChangeLog
+++ b/sim/mn10300/ChangeLog
@@ -1,3 +1,20 @@
+Wed Mar 12 15:04:00 1997  Jeffrey A Law  (law@cygnus.com)
+
+       * simops.c: Fix typos in bset insns.  Fix arguments to store_mem
+       for bset imm8,(d8,an) and bclr imm8,(d8,an).
+
+Wed Mar  5 15:00:10 1997  Jeffrey A Law  (law@cygnus.com)
+
+       * simops.c: Fix register references when computing Z and N bits
+       for lsr imm8,dn.
+
+Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
+
+       * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
+       COMMON_{PRE,POST}_CONFIG_FRAG instead.
+       * configure.in: sinclude ../common/aclocal.m4.
+       * configure: Regenerated.
+
 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
 
        * interp.c (init_system): Allocate 2^19 bytes of space for the

diff --git a/sim/mn10300/simops.c b/sim/mn10300/simops.c
index 6ed254f2323675f5f11e6fcdb25f20a6a3143da8..cd4c98fea2984e9a23c39798a17e0d4d202c02ff 100644 (file)
--- a/sim/mn10300/simops.c
+++ b/sim/mn10300/simops.c
@@ -2054,7 +2054,8 @@ void OP_FAF00000 (insn, extension)
                     + SEXT8 ((insn & 0xff00) >> 8)), 1);
   z = (temp & (insn & 0xff)) == 0;
   temp |= (insn & 0xff);
-  store_mem (State.regs[REG_A0 + REG0_16 (insn)], 1, temp);
+  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
+             + SEXT8 ((insn & 0xff00) >> 8)), 1, temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }
@@ -2068,7 +2069,7 @@ void OP_F090 (insn, extension)
 
   temp = load_mem (State.regs[REG_A0 + REG0 (insn)], 1);
   z = (temp & State.regs[REG_D0 + REG1 (insn)]) == 0;
-  temp = ~temp & State.regs[REG_D0 + REG1 (insn)];
+  temp = temp & ~State.regs[REG_D0 + REG1 (insn)];
   store_mem (State.regs[REG_A0 + REG0 (insn)], 1, temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
@@ -2083,7 +2084,7 @@ void OP_FE010000 (insn, extension)
 
   temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
   z = (temp & (extension & 0xff)) == 0;
-  temp = ~temp & (extension & 0xff);
+  temp = temp & ~(extension & 0xff);
   store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
@@ -2099,8 +2100,9 @@ void OP_FAF40000 (insn, extension)
   temp = load_mem ((State.regs[REG_A0 + REG0_16 (insn)]
                     + SEXT8 ((insn & 0xff00) >> 8)), 1);
   z = (temp & (insn & 0xff)) == 0;
-  temp = ~temp & (insn & 0xff);
-  store_mem (State.regs[REG_A0 + REG0_16 (insn)], 1, temp);
+  temp = temp & ~(insn & 0xff);
+  store_mem ((State.regs[REG_A0 + REG0_16 (insn)]
+             + SEXT8 ((insn & 0xff00) >> 8)), 1, temp);
   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
   PSW |= (z ? PSW_Z : 0);
 }