They are currently just "integer", but the dot version is fast_compare.
This makes them all "add". Later we should introduce attributes to
distinguish e.g. addc and adde (which aren't currently handled as
separate instructions at all, only in groups).
From-SVN: r210871
+2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
+
+ * config/rs6000/rs6000.md (type): Add "add".
+ (*add<mode>3_internal1, addsi3_high, *add<mode>3_internal2,
+ *add<mode>3_internal3, *neg<mode>2_internal, and 5 anonymous
+ define_insns): Use it.
+ * config/rs6000/rs6000.c (rs6000_adjust_cost): Adjust.
+
+ * config/rs6000/40x.md (ppc403-integer, ppc403-compare): Adjust.
+ * config/rs6000/440.md (ppc440-integer, ppc440-compare): Adjust.
+ * config/rs6000/476.md (ppc476-simple-integer, ppc476-compare):
+ Adjust.
+ * config/rs6000/601.md (ppc601-integer): Adjust.
+ * config/rs6000/603.md (ppc603-integer, ppc603-compare): Adjust.
+ * config/rs6000/6xx.md (ppc604-integer, ppc604-compare): Adjust.
+ * config/rs6000/7450.md (ppc7450-integer, ppc7450-compare): Adjust.
+ * config/rs6000/7xx.md (ppc750-integer, ppc750-compare): Adjust.
+ * config/rs6000/8540.md (ppc8540_su): Adjust.
+ * config/rs6000/cell.md (cell-integer, cell-fast-cmp,
+ cell-cmp-microcoded): Adjust.
+ * config/rs6000/e300c2c3.md (ppce300c3_cmp, ppce300c3_iu): Adjust.
+ * config/rs6000/e500mc.md (e500mc_su): Adjust.
+ * config/rs6000/e500mc64.md (e500mc64_su, e500mc64_su2): Adjust.
+ * config/rs6000/e5500.md (e5500_sfx, e5500_sfx2): Adjust.
+ * config/rs6000/e6500.md (e6500_sfx, e6500_sfx2): Adjust.
+ * config/rs6000/mpc.md (mpccore-integer, mpccore-compare): Adjust.
+ * config/rs6000/power4.md (power4-integer, power4-cmp): Adjust.
+ * config/rs6000/power5.md (power5-integer, power5-cmp): Adjust.
+ * config/rs6000/power6.md (power6-integer, power6-fast-compare):
+ Adjust.
+ * config/rs6000/power7.md (power7-integer, power7-cmp): Adjust.
+ * config/rs6000/power8.md (power8-1cyc, power8-fast-compare):
+ Adjust.
+ * config/rs6000/rs64.md (rs64a-integer, rs64a-compare): Adjust.
+ * config/rs6000/titan.md (titan_fxu_adder, titan_fxu_alu): Adjust.
+
2014-05-23 Segher Boessenkool <segher@kernel.crashing.org>
* config/rs6000/rs6000.md (type): Delete "var_shift_rotate",
(define_insn_reservation "ppc403-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
(define_insn_reservation "ppc403-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc476-simple-integer" 1
(and (ior (eq_attr "type" "integer,insert,exts")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
(define_insn_reservation "ppc476-compare" 4
(and (ior (eq_attr "type" "compare,fast_compare,mfcr,mfcrf,\
mtcr,mfjmpr,mtjmpr")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,exts,isel")
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
(define_insn_reservation "ppc603-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
(define_insn_reservation "ppc603-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
(define_insn_reservation "ppc604-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
(define_insn_reservation "ppc7450-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
(define_insn_reservation "ppc750-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
(and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
(define_insn_reservation "cell-cmp-microcoded" 9
(and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
(and (ior (eq_attr "type" "cmp,compare,fast_compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
- (and (eq_attr "type" "integer,insert,isel")
+ (and (ior (eq_attr "type" "integer,insert,isel")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
(define_insn_reservation "e500mc64_su2" 2
(and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
- (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
;; SFX.
(define_insn_reservation "e6500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
- (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "mpccore-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
(define_insn_reservation "mpccore-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
|(iu2_power4,nothing,iu1_power4))")
(define_insn_reservation "power4-cmp" 3
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"iq_power4")
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
(define_insn_reservation "power5-cmp" 3
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"iq_power5")
"LSU_power6")
(define_insn_reservation "power6-integer" 1
- (and (eq_attr "type" "integer")
+ (and (ior (eq_attr "type" "integer")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power6"))
"FXU_power6")
"FXU_power6")
(define_insn_reservation "power6-fast-compare" 1
- (and (eq_attr "type" "fast_compare")
+ (and (ior (eq_attr "type" "fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power6"))
"FXU_power6")
; FX Unit
(define_insn_reservation "power7-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
(define_insn_reservation "power7-cmp" 1
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
; FX Unit
(define_insn_reservation "power8-1cyc" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
; fast_compare : add./and./nor./etc
(define_insn_reservation "power8-fast-compare" 2
- (and (eq_attr "type" "fast_compare")
+ (and (ior (eq_attr "type" "fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
break;
}
case TYPE_INTEGER:
+ case TYPE_ADD:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
break;
}
case TYPE_INTEGER:
+ case TYPE_ADD:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
;; computations.
(define_attr "type"
"integer,two,three,
- shift,insert,
+ add,shift,insert,
mul,halfmul,div,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
addi %0,%1,%2
addic %0,%1,%2
addis %0,%1,%v2"
- [(set_attr "length" "4,4,4,4")])
+ [(set_attr "type" "add")])
(define_insn "addsi3_high"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
(high:SI (match_operand 2 "" ""))))]
"TARGET_MACHO && !TARGET_64BIT"
"addis %0,%1,ha16(%2)"
- [(set_attr "length" "4")])
+ [(set_attr "type" "add")])
(define_insn "*add<mode>3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
addic. %3,%1,%2
#
#"
- [(set_attr "type" "fast_compare,compare,compare,compare")
+ [(set_attr "type" "add,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
addic. %0,%1,%2
#
#"
- [(set_attr "type" "fast_compare,compare,compare,compare")
+ [(set_attr "type" "add,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
""
"@
subf %0,%2,%1
- subfic %0,%2,%1")
+ subfic %0,%2,%1"
+ [(set_attr "type" "add")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
subf. %3,%2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
"@
subf. %0,%2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
""
- "neg %0,%1")
+ "neg %0,%1"
+ [(set_attr "type" "add")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
"@
neg. %2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
"@
neg. %0,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
(define_insn_reservation "rs64a-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
(define_insn_reservation "rs64a-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
;; instructions. It provides its own, dedicated result-bus, so we
;; don't need the titan_fxu_wb reservation to complete.
(define_insn_reservation "titan_fxu_adder" 1
- (and (eq_attr "type" "cmp,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
"titan_issue,titan_fxu_sh")
(define_insn_reservation "titan_fxu_alu" 1
- (and (eq_attr "type" "integer,exts")
+ (and (ior (eq_attr "type" "integer,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")