meson: rename included C source files to .c.inc

With Makefiles that have automatically generated dependencies, you
generated includes are set as dependencies of the Makefile, so that they
are built before everything else and they are available when first
building the .c files.

Alternatively you can use a fine-grained dependency, e.g.

        target/arm/translate.o: target/arm/decode-neon-shared.inc.c

With Meson you have only one choice and it is a third option, namely
"build at the beginning of the corresponding target"; the way you
express it is to list the includes in the sources of that target.

The problem is that Meson decides if something is a source vs. a
generated include by looking at the extension: '.c', '.cc', '.m', '.C'
are sources, while everything else is considered an include---including
'.inc.c'.

Use '.c.inc' to avoid this, as it is consistent with our other convention
of using '.rst.inc' for included reStructuredText files.  The editorconfig
file is adjusted.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

diff --git a/.editorconfig b/.editorconfig
index a001f340bd8be482016d1f62a00913cf5b765b2b..22681d91c6ff3c6256b04e7b064da6c5510f8de2 100644 (file)
--- a/.editorconfig
+++ b/.editorconfig
@@ -22,9 +22,10 @@ indent_style = tab
 indent_size = 8
 file_type_emacs = makefile
 
-[*.{c,h}]
+[*.{c,h,c.inc,h.inc}]
 indent_style = space
 indent_size = 4
+file_type_emacs = c
 
 [*.sh]
 indent_style = space

diff --git a/.gitignore b/.gitignore
index 656e39050b42ea299277a12824d8dc7b885299e7..f8b3cd6fd52b1ae072bf41179cfba0a4ef227cf6 100644 (file)
--- a/.gitignore
+++ b/.gitignore
@@ -18,7 +18,7 @@
 /ui/shader/texture-blit-frag.h
 /ui/shader/texture-blit-vert.h
 /ui/shader/texture-blit-flip-vert.h
-/ui/input-keymap-*.c
+/ui/input-keymap-*.c.inc
 *-timestamp
 /*-softmmu
 /*-darwin-user
@@ -161,4 +161,4 @@ trace-dtrace-root.h
 trace-dtrace-root.dtrace
 trace-ust-all.h
 trace-ust-all.c
-/target/arm/decode-sve.inc.c
+/target/arm/decode-sve.c.inc

diff --git a/Makefile b/Makefile
index 00cadebf994be85ab10c7d63a77e7515ee975082..5596482dbd7fa0300af36208adfb4f9f21684b5d 100644 (file)
--- a/Makefile
+++ b/Makefile
@@ -289,28 +289,28 @@ KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen
 KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv
 
 KEYCODEMAP_FILES = \
-                ui/input-keymap-atset1-to-qcode.c \
-                ui/input-keymap-linux-to-qcode.c \
-                ui/input-keymap-qcode-to-atset1.c \
-                ui/input-keymap-qcode-to-atset2.c \
-                ui/input-keymap-qcode-to-atset3.c \
-                ui/input-keymap-qcode-to-linux.c \
-                ui/input-keymap-qcode-to-qnum.c \
-                ui/input-keymap-qcode-to-sun.c \
-                ui/input-keymap-qnum-to-qcode.c \
-                ui/input-keymap-usb-to-qcode.c \
-                ui/input-keymap-win32-to-qcode.c \
-                ui/input-keymap-x11-to-qcode.c \
-                ui/input-keymap-xorgevdev-to-qcode.c \
-                ui/input-keymap-xorgkbd-to-qcode.c \
-                ui/input-keymap-xorgxquartz-to-qcode.c \
-                ui/input-keymap-xorgxwin-to-qcode.c \
-                ui/input-keymap-osx-to-qcode.c \
+                ui/input-keymap-atset1-to-qcode.c.inc \
+                ui/input-keymap-linux-to-qcode.c.inc \
+                ui/input-keymap-qcode-to-atset1.c.inc \
+                ui/input-keymap-qcode-to-atset2.c.inc \
+                ui/input-keymap-qcode-to-atset3.c.inc \
+                ui/input-keymap-qcode-to-linux.c.inc \
+                ui/input-keymap-qcode-to-qnum.c.inc \
+                ui/input-keymap-qcode-to-sun.c.inc \
+                ui/input-keymap-qnum-to-qcode.c.inc \
+                ui/input-keymap-usb-to-qcode.c.inc \
+                ui/input-keymap-win32-to-qcode.c.inc \
+                ui/input-keymap-x11-to-qcode.c.inc \
+                ui/input-keymap-xorgevdev-to-qcode.c.inc \
+                ui/input-keymap-xorgkbd-to-qcode.c.inc \
+                ui/input-keymap-xorgxquartz-to-qcode.c.inc \
+                ui/input-keymap-xorgxwin-to-qcode.c.inc \
+                ui/input-keymap-osx-to-qcode.c.inc \
                 $(NULL)
 
 generated-files-$(CONFIG_SOFTMMU) += $(KEYCODEMAP_FILES)
 
-ui/input-keymap-%.c: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs
+ui/input-keymap-%.c.inc: $(KEYCODEMAP_GEN) $(KEYCODEMAP_CSV) $(SRC_PATH)/ui/Makefile.objs
        $(call quiet-command,\
            stem=$* && src=$${stem%-to-*} dst=$${stem#*-to-} && \
            test -e $(KEYCODEMAP_GEN) && \

diff --git a/accel/tcg/atomic_common.inc.c b/accel/tcg/atomic_common.c.inc
similarity index 100%
rename from accel/tcg/atomic_common.inc.c
rename to accel/tcg/atomic_common.c.inc

diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 5349ee6b0e0df11e8923f4c6b08efd2293370159..2d48281942ff00e92bd633a8bf2713ee5b8e5392 100644 (file)
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -2354,7 +2354,7 @@ void cpu_stq_le_data(CPUArchState *env, target_ulong ptr, uint64_t val)
 #define ATOMIC_MMU_CLEANUP
 #define ATOMIC_MMU_IDX   get_mmuidx(oi)
 
-#include "atomic_common.inc.c"
+#include "atomic_common.c.inc"
 
 #define DATA_SIZE 1
 #include "atomic_template.h"

diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 1d34c57ff5c75c21a4ee24f547dd29ca313c4a7d..bb039eb32d67008a463fc78a4ef7bf594b6f0bc4 100644 (file)
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -1189,7 +1189,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr,
 #define ATOMIC_NAME(X)   HELPER(glue(glue(atomic_ ## X, SUFFIX), END))
 #define EXTRA_ARGS
 
-#include "atomic_common.inc.c"
+#include "atomic_common.c.inc"
 
 #define DATA_SIZE 1
 #include "atomic_template.h"

diff --git a/contrib/gitdm/filetypes.txt b/contrib/gitdm/filetypes.txt
index 2d5002fea0c926fb4f10e5ef3401528272f635ee..9e9c50520550af22239e349c3d0a6d63c185dbce 100644 (file)
--- a/contrib/gitdm/filetypes.txt
+++ b/contrib/gitdm/filetypes.txt
@@ -42,7 +42,7 @@ order build,interface,tests,code,documentation,devel-doc,blobs
 # (most common languages first
 #
 filetype code \.c$     # C
-filetype code \.inc.c$ # C
+filetype code \.c.inc$ # C
 filetype code \.C$     # C++
 filetype code \.cpp$   # C++
 filetype code \.c\+\+$ # C++

diff --git a/exec.c b/exec.c
index 8047bf2ff923a8e254e407dc11e6fd62e5c2995b..7683afb6a8e1d48e85aa0bb220328f9b5d9bd99b 100644 (file)
--- a/exec.c
+++ b/exec.c
@@ -3659,7 +3659,7 @@ void cpu_physical_memory_unmap(void *buffer, hwaddr len,
 #define TRANSLATE(...)           address_space_translate(as, __VA_ARGS__)
 #define RCU_READ_LOCK(...)       rcu_read_lock()
 #define RCU_READ_UNLOCK(...)     rcu_read_unlock()
-#include "memory_ldst.inc.c"
+#include "memory_ldst.c.inc"
 
 int64_t address_space_cache_init(MemoryRegionCache *cache,
                                  AddressSpace *as,
@@ -3795,7 +3795,7 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
 #define TRANSLATE(...)           address_space_translate_cached(cache, __VA_ARGS__)
 #define RCU_READ_LOCK()          ((void)0)
 #define RCU_READ_UNLOCK()        ((void)0)
-#include "memory_ldst.inc.c"
+#include "memory_ldst.c.inc"
 
 /* virtual memory access for debug (includes writing to ROM) */
 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr,

diff --git a/fpu/softfloat-specialize.inc.c b/fpu/softfloat-specialize.c.inc
similarity index 100%
rename from fpu/softfloat-specialize.inc.c
rename to fpu/softfloat-specialize.c.inc

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 79be4f58405d9c4b2a2fe5756d4a1078c2faad22..5dce791eb6dae0dc691e740659e31ce976226e95 100644 (file)
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -621,7 +621,7 @@ static inline float64 float64_pack_raw(FloatParts p)
 | are propagated from function inputs to output.  These details are target-
 | specific.
 *----------------------------------------------------------------------------*/
-#include "softfloat-specialize.inc.c"
+#include "softfloat-specialize.c.inc"
 
 /* Canonicalize EXP and FRAC, setting CLS.  */
 static FloatParts sf_canonicalize(FloatParts part, const FloatFmt *parm,

diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index e63450a89366340ba66dc3ff2549c5b53ae4f643..d40c925d04d64e44bbd26d4e7e170ab215f8f260 100644 (file)
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -636,7 +636,7 @@ struct TCGContext {
     /* Track which vCPU triggers events */
     CPUState *cpu;                      /* *_trans */
 
-    /* These structures are private to tcg-target.inc.c.  */
+    /* These structures are private to tcg-target.c.inc.  */
 #ifdef TCG_TARGET_NEED_LDST_LABELS
     QSIMPLEQ_HEAD(, TCGLabelQemuLdst) ldst_labels;
 #endif

diff --git a/memory_ldst.inc.c b/memory_ldst.c.inc
similarity index 100%
rename from memory_ldst.inc.c
rename to memory_ldst.c.inc

diff --git a/scripts/clean-includes b/scripts/clean-includes
index 795b3bea318e97ab0177085b146aa0de91160951..aaa7d4ceb3891a4fce7e286452c842b24514e62c 100755 (executable)
--- a/scripts/clean-includes
+++ b/scripts/clean-includes
@@ -113,7 +113,7 @@ EOT
 
 for f in "$@"; do
   case "$f" in
-    *.inc.c)
+    *.c.inc)
       # These aren't standalone C source files
       echo "SKIPPING $f (not a standalone source file)"
       continue

diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs
index fa39fd7c831e86ade53ff412cb33f0201d41ea79..317eed993f0c20896eb9bcaa0ac747b9a66e8a84 100644 (file)
--- a/target/arm/Makefile.objs
+++ b/target/arm/Makefile.objs
@@ -13,66 +13,66 @@ obj-$(call lnot,$(CONFIG_KVM)) += kvm-stub.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/arm/decode-sve.inc.c: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
+target/arm/decode-sve.c.inc: $(SRC_PATH)/target/arm/sve.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --decode disas_sve -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-neon-shared.inc.c: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
+target/arm/decode-neon-shared.c.inc: $(SRC_PATH)/target/arm/neon-shared.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_neon_shared -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-neon-dp.inc.c: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
+target/arm/decode-neon-dp.c.inc: $(SRC_PATH)/target/arm/neon-dp.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_neon_dp -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-neon-ls.inc.c: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
+target/arm/decode-neon-ls.c.inc: $(SRC_PATH)/target/arm/neon-ls.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_neon_ls -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-vfp.inc.c: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
+target/arm/decode-vfp.c.inc: $(SRC_PATH)/target/arm/vfp.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_vfp -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-vfp-uncond.inc.c: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
+target/arm/decode-vfp-uncond.c.inc: $(SRC_PATH)/target/arm/vfp-uncond.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_vfp_uncond -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-a32.inc.c: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
+target/arm/decode-a32.c.inc: $(SRC_PATH)/target/arm/a32.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_a32 -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-a32-uncond.inc.c: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
+target/arm/decode-a32-uncond.c.inc: $(SRC_PATH)/target/arm/a32-uncond.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_a32_uncond -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-t32.inc.c: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
+target/arm/decode-t32.c.inc: $(SRC_PATH)/target/arm/t32.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --static-decode disas_t32 -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/decode-t16.inc.c: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
+target/arm/decode-t16.c.inc: $(SRC_PATH)/target/arm/t16.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) -w 16 --static-decode disas_t16 -o $@ $<,\
          "GEN", $(TARGET_DIR)$@)
 
-target/arm/translate-sve.o: target/arm/decode-sve.inc.c
-target/arm/translate.o: target/arm/decode-neon-shared.inc.c
-target/arm/translate.o: target/arm/decode-neon-dp.inc.c
-target/arm/translate.o: target/arm/decode-neon-ls.inc.c
-target/arm/translate.o: target/arm/decode-vfp.inc.c
-target/arm/translate.o: target/arm/decode-vfp-uncond.inc.c
-target/arm/translate.o: target/arm/decode-a32.inc.c
-target/arm/translate.o: target/arm/decode-a32-uncond.inc.c
-target/arm/translate.o: target/arm/decode-t32.inc.c
-target/arm/translate.o: target/arm/decode-t16.inc.c
+target/arm/translate-sve.o: target/arm/decode-sve.c.inc
+target/arm/translate.o: target/arm/decode-neon-shared.c.inc
+target/arm/translate.o: target/arm/decode-neon-dp.c.inc
+target/arm/translate.o: target/arm/decode-neon-ls.c.inc
+target/arm/translate.o: target/arm/decode-vfp.c.inc
+target/arm/translate.o: target/arm/decode-vfp-uncond.c.inc
+target/arm/translate.o: target/arm/decode-a32.c.inc
+target/arm/translate.o: target/arm/decode-a32-uncond.c.inc
+target/arm/translate.o: target/arm/decode-t32.c.inc
+target/arm/translate.o: target/arm/decode-t16.c.inc
 
 obj-y += tlb_helper.o debug_helper.o
 obj-y += translate.o op_helper.o

diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.c.inc
similarity index 99%
rename from target/arm/translate-neon.inc.c
rename to target/arm/translate-neon.c.inc
index f6cb92157395e7d20da72a4e7e16bea2da22719d..8fbe8cef9f60f1e48cad0ff02e0d2cf7cc5156f5 100644 (file)
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.c.inc
@@ -50,9 +50,9 @@ static inline int rsub_8(DisasContext *s, int x)
 }
 
 /* Include the generated Neon decoder */
-#include "decode-neon-dp.inc.c"
-#include "decode-neon-ls.inc.c"
-#include "decode-neon-shared.inc.c"
+#include "decode-neon-dp.c.inc"
+#include "decode-neon-ls.c.inc"
+#include "decode-neon-shared.c.inc"
 
 /* Return the offset of a 2**SIZE piece of a NEON register, at index ELE,
  * where 0 is the least significant end of the register.

diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 88a2fb271d1ae83a7ffa5b6999a0ad4ba6178fbb..8c7fbbd5033092b2392cf6ec1c5ac87c10c328f3 100644 (file)
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -100,7 +100,7 @@ static inline int msz_dtype(DisasContext *s, int msz)
  * Include the generated decoder.
  */
 
-#include "decode-sve.inc.c"
+#include "decode-sve.c.inc"
 
 /*
  * Implement all of the translator functions referenced by the decoder.

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.c.inc
similarity index 99%
rename from target/arm/translate-vfp.inc.c
rename to target/arm/translate-vfp.c.inc
index afa8a5f88850a5b4887ed2c9bac47ab9e6eb4dc3..2d63fa0d3992cfc8494dc7b76553efc3a0be4dee 100644 (file)
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.c.inc
@@ -27,8 +27,8 @@
  */
 
 /* Include the generated VFP decoder */
-#include "decode-vfp.inc.c"
-#include "decode-vfp-uncond.inc.c"
+#include "decode-vfp.c.inc"
+#include "decode-vfp-uncond.c.inc"
 
 /*
  * The imm8 encodes the sign bit, enough bits to represent an exponent in

diff --git a/target/arm/translate.c b/target/arm/translate.c
index c39a929b938c1fb1b3c694a0b981e12bab13a3ed..556588d92fe3fb0e1f49e5c03b5a176fb0dbb004 100644 (file)
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1176,8 +1176,8 @@ static TCGv_ptr vfp_reg_ptr(bool dp, int reg)
 #define ARM_CP_RW_BIT   (1 << 20)
 
 /* Include the VFP and Neon decoders */
-#include "translate-vfp.inc.c"
-#include "translate-neon.inc.c"
+#include "translate-vfp.c.inc"
+#include "translate-neon.c.inc"
 
 static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
 {
@@ -5217,10 +5217,10 @@ static int t16_pop_list(DisasContext *s, int x)
  * Include the generated decoders.
  */
 
-#include "decode-a32.inc.c"
-#include "decode-a32-uncond.inc.c"
-#include "decode-t32.inc.c"
-#include "decode-t16.inc.c"
+#include "decode-a32.c.inc"
+#include "decode-a32-uncond.c.inc"
+#include "decode-t32.c.inc"
+#include "decode-t16.c.inc"
 
 /* Helpers to swap operands for reverse-subtract.  */
 static void gen_rsb(TCGv_i32 dst, TCGv_i32 a, TCGv_i32 b)

diff --git a/target/avr/Makefile.objs b/target/avr/Makefile.objs
index 6e35ba2c5c1c04b33261a322c996073a7bf4deaa..fb94a0b0697ffb67b82d15df262edeb8075cab70 100644 (file)
--- a/target/avr/Makefile.objs
+++ b/target/avr/Makefile.objs
@@ -21,12 +21,12 @@
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 decode-y = $(SRC_PATH)/target/avr/insn.decode
 
-target/avr/decode_insn.inc.c: $(decode-y) $(DECODETREE)
+target/avr/decode_insn.c.inc: $(decode-y) $(DECODETREE)
        $(call quiet-command, \
          $(PYTHON) $(DECODETREE) -o $@ --decode decode_insn --insnwidth 16 $<, \
          "GEN", $(TARGET_DIR)$@)
 
-target/avr/translate.o: target/avr/decode_insn.inc.c
+target/avr/translate.o: target/avr/decode_insn.c.inc
 
 obj-y += translate.o cpu.o helper.o
 obj-y += gdbstub.o

diff --git a/target/avr/disas.c b/target/avr/disas.c
index 8e1bac4d76394fec14b99c2b4729b79bb0c8bbed..f15dc7911a070c4cf4fb2a3b4564ef0bd322bc8a 100644 (file)
--- a/target/avr/disas.c
+++ b/target/avr/disas.c
@@ -60,7 +60,7 @@ static int append_16(DisasContext *ctx, int x)
 
 /* Include the auto-generated decoder.  */
 static bool decode_insn(DisasContext *ctx, uint16_t insn);
-#include "decode_insn.inc.c"
+#include "decode_insn.c.inc"
 
 #define output(mnemonic, format, ...) \
     (pctx->info->fprintf_func(pctx->info->stream, "%-9s " format, \

diff --git a/target/avr/translate.c b/target/avr/translate.c
index 648dcd5c3ebb8a66b12353755446bbe5844dc88e..9eb14f63f0889f7362eef2ff24c7277b459f85cd 100644 (file)
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -198,7 +198,7 @@ static bool avr_have_feature(DisasContext *ctx, int feature)
 }
 
 static bool decode_insn(DisasContext *ctx, uint16_t insn);
-#include "decode_insn.inc.c"
+#include "decode_insn.c.inc"
 
 /*
  * Arithmetic Instructions

diff --git a/target/cris/translate.c b/target/cris/translate.c
index aaa46b5bcaaecdacb81158ec87f42692d62217b7..ee5e359c778867e3d3e8c2a16d7127a2b27ac1ca 100644 (file)
--- a/target/cris/translate.c
+++ b/target/cris/translate.c
@@ -3037,7 +3037,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc)
     return insn_len;
 }
 
-#include "translate_v10.inc.c"
+#include "translate_v10.c.inc"
 
 /*
  * Delay slots on QEMU/CRIS.

diff --git a/target/cris/translate_v10.inc.c b/target/cris/translate_v10.c.inc
similarity index 100%
rename from target/cris/translate_v10.inc.c
rename to target/cris/translate_v10.c.inc

diff --git a/target/hppa/Makefile.objs b/target/hppa/Makefile.objs
index 174f50a96caebb76e2a8be1d2f216355cbae23e3..190cbff1976c21c4cc2ba0d99894aadf836610f2 100644 (file)
--- a/target/hppa/Makefile.objs
+++ b/target/hppa/Makefile.objs
@@ -4,8 +4,8 @@ obj-$(CONFIG_SOFTMMU) += machine.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/hppa/decode.inc.c: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
+target/hppa/decode.c.inc: $(SRC_PATH)/target/hppa/insns.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
 
-target/hppa/translate.o: target/hppa/decode.inc.c
+target/hppa/translate.o: target/hppa/decode.c.inc

diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 4bd22d4820b72c8dfd625c89ab18ee05de440e5f..316f58562ebf43ac38a30a976f589b66fd832f4f 100644 (file)
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -334,7 +334,7 @@ static int expand_shl11(DisasContext *ctx, int val)
 
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 /* We are not using a goto_tb (for whatever reason), but have updated
    the iaq (for whatever reason), so don't do it again on exit.  */

diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9fad58ea2c18ef65ab6061fa514347bc11723d7b..899b90ae0ffb5044ae9e478cc87a382e11f5be08 100644 (file)
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -31322,7 +31322,7 @@ void mips_tcg_init(void)
 #endif
 }
 
-#include "translate_init.inc.c"
+#include "translate_init.c.inc"
 
 void cpu_mips_realize_env(CPUMIPSState *env)
 {

diff --git a/target/mips/translate_init.inc.c b/target/mips/translate_init.c.inc
similarity index 100%
rename from target/mips/translate_init.inc.c
rename to target/mips/translate_init.c.inc

diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs
index b5432f46843ee40f1f66693a09416b9c0a7a4b88..423d64512eeb75a98d5d62740693ad4f952ca946 100644 (file)
--- a/target/openrisc/Makefile.objs
+++ b/target/openrisc/Makefile.objs
@@ -6,10 +6,10 @@ obj-y += gdbstub.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/openrisc/decode.inc.c: \
+target/openrisc/decode.c.inc: \
   $(SRC_PATH)/target/openrisc/insns.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
 
-target/openrisc/translate.o: target/openrisc/decode.inc.c
-target/openrisc/disas.o: target/openrisc/decode.inc.c
+target/openrisc/translate.o: target/openrisc/decode.c.inc
+target/openrisc/disas.o: target/openrisc/decode.c.inc

diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
index ce112640b95c8f00872f2c88bcbbb9d8539f5095..cc91775344666a03a68c78d8cad7eeda0ea1a4f9 100644 (file)
--- a/target/openrisc/disas.c
+++ b/target/openrisc/disas.c
@@ -25,7 +25,7 @@
 typedef disassemble_info DisasContext;
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 #define output(mnemonic, format, ...) \
     (info->fprintf_func(info->stream, "%-9s " format, \

diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 52323a16df4efde063f68048ba2a9a2a10ce5430..573428b8ea6d338cceed7a19431168c427a47003 100644 (file)
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -65,7 +65,7 @@ static inline bool is_user(DisasContext *dc)
 }
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 static TCGv cpu_sr;
 static TCGv cpu_regs[32];

diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c
index d8bd3c234a16e528451638828683e1b41856b7ee..43ebf1daad4509a8c34ebbcd2401fe650ac5bfe7 100644 (file)
--- a/target/ppc/int_helper.c
+++ b/target/ppc/int_helper.c
@@ -398,7 +398,7 @@ target_ulong helper_divso(CPUPPCState *env, target_ulong arg1,
 target_ulong helper_602_mfrom(target_ulong arg)
 {
     if (likely(arg < 602)) {
-#include "mfrom_table.inc.c"
+#include "mfrom_table.c.inc"
         return mfrom_ROM_table[arg];
     } else {
         return 0;

diff --git a/target/ppc/mfrom_table.inc.c b/target/ppc/mfrom_table.c.inc
similarity index 100%
rename from target/ppc/mfrom_table.inc.c
rename to target/ppc/mfrom_table.c.inc

diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4ce3d664b5dd6a5e82d04a7ffc092f98dd1b3a4d..04db0d865cae306ab9d16aa63a698b7e0704ca9b 100644 (file)
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6900,15 +6900,15 @@ static inline void set_avr64(int regno, TCGv_i64 src, bool high)
     tcg_gen_st_i64(src, cpu_env, avr64_offset(regno, high));
 }
 
-#include "translate/fp-impl.inc.c"
+#include "translate/fp-impl.c.inc"
 
-#include "translate/vmx-impl.inc.c"
+#include "translate/vmx-impl.c.inc"
 
-#include "translate/vsx-impl.inc.c"
+#include "translate/vsx-impl.c.inc"
 
-#include "translate/dfp-impl.inc.c"
+#include "translate/dfp-impl.c.inc"
 
-#include "translate/spe-impl.inc.c"
+#include "translate/spe-impl.c.inc"
 
 /* Handles lfdp, lxsd, lxssp */
 static void gen_dform39(DisasContext *ctx)
@@ -7587,19 +7587,19 @@ GEN_HANDLER2_E(treclaim, "treclaim", 0x1F, 0x0E, 0x1D, 0x03E0F800, \
 GEN_HANDLER2_E(trechkpt, "trechkpt", 0x1F, 0x0E, 0x1F, 0x03FFF800, \
                PPC_NONE, PPC2_TM),
 
-#include "translate/fp-ops.inc.c"
+#include "translate/fp-ops.c.inc"
 
-#include "translate/vmx-ops.inc.c"
+#include "translate/vmx-ops.c.inc"
 
-#include "translate/vsx-ops.inc.c"
+#include "translate/vsx-ops.c.inc"
 
-#include "translate/dfp-ops.inc.c"
+#include "translate/dfp-ops.c.inc"
 
-#include "translate/spe-ops.inc.c"
+#include "translate/spe-ops.c.inc"
 };
 
 #include "helper_regs.h"
-#include "translate_init.inc.c"
+#include "translate_init.c.inc"
 
 /*****************************************************************************/
 /* Misc PowerPC helpers */

diff --git a/target/ppc/translate/dfp-impl.inc.c b/target/ppc/translate/dfp-impl.c.inc
similarity index 100%
rename from target/ppc/translate/dfp-impl.inc.c
rename to target/ppc/translate/dfp-impl.c.inc

diff --git a/target/ppc/translate/dfp-ops.inc.c b/target/ppc/translate/dfp-ops.c.inc
similarity index 100%
rename from target/ppc/translate/dfp-ops.inc.c
rename to target/ppc/translate/dfp-ops.c.inc

diff --git a/target/ppc/translate/fp-impl.inc.c b/target/ppc/translate/fp-impl.c.inc
similarity index 100%
rename from target/ppc/translate/fp-impl.inc.c
rename to target/ppc/translate/fp-impl.c.inc

diff --git a/target/ppc/translate/fp-ops.inc.c b/target/ppc/translate/fp-ops.c.inc
similarity index 100%
rename from target/ppc/translate/fp-ops.inc.c
rename to target/ppc/translate/fp-ops.c.inc

diff --git a/target/ppc/translate/spe-impl.inc.c b/target/ppc/translate/spe-impl.c.inc
similarity index 100%
rename from target/ppc/translate/spe-impl.inc.c
rename to target/ppc/translate/spe-impl.c.inc

diff --git a/target/ppc/translate/spe-ops.inc.c b/target/ppc/translate/spe-ops.c.inc
similarity index 100%
rename from target/ppc/translate/spe-ops.inc.c
rename to target/ppc/translate/spe-ops.c.inc

diff --git a/target/ppc/translate/vmx-impl.inc.c b/target/ppc/translate/vmx-impl.c.inc
similarity index 100%
rename from target/ppc/translate/vmx-impl.inc.c
rename to target/ppc/translate/vmx-impl.c.inc

diff --git a/target/ppc/translate/vmx-ops.inc.c b/target/ppc/translate/vmx-ops.c.inc
similarity index 100%
rename from target/ppc/translate/vmx-ops.inc.c
rename to target/ppc/translate/vmx-ops.c.inc

diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.c.inc
similarity index 100%
rename from target/ppc/translate/vsx-impl.inc.c
rename to target/ppc/translate/vsx-impl.c.inc

diff --git a/target/ppc/translate/vsx-ops.inc.c b/target/ppc/translate/vsx-ops.c.inc
similarity index 100%
rename from target/ppc/translate/vsx-ops.inc.c
rename to target/ppc/translate/vsx-ops.c.inc

diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.c.inc
similarity index 100%
rename from target/ppc/translate_init.inc.c
rename to target/ppc/translate_init.c.inc

diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs
index ff38df6219ce1ca150d07afcf794aead3a4dd9cb..1cd4c580059e01a31f6176f77d008d1325e34040 100644 (file)
--- a/target/riscv/Makefile.objs
+++ b/target/riscv/Makefile.objs
@@ -14,15 +14,15 @@ decode16-y = $(SRC_PATH)/target/riscv/insn16.decode
 decode16-$(TARGET_RISCV32) += $(SRC_PATH)/target/riscv/insn16-32.decode
 decode16-$(TARGET_RISCV64) += $(SRC_PATH)/target/riscv/insn16-64.decode
 
-target/riscv/decode_insn32.inc.c: $(decode32-y) $(DECODETREE)
+target/riscv/decode_insn32.c.inc: $(decode32-y) $(DECODETREE)
        $(call quiet-command, \
          $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn32 \
           $(decode32-y), "GEN", $(TARGET_DIR)$@)
 
-target/riscv/decode_insn16.inc.c: $(decode16-y) $(DECODETREE)
+target/riscv/decode_insn16.c.inc: $(decode16-y) $(DECODETREE)
        $(call quiet-command, \
          $(PYTHON) $(DECODETREE) -o $@ --static-decode decode_insn16 \
           --insnwidth 16 $(decode16-y), "GEN", $(TARGET_DIR)$@)
 
-target/riscv/translate.o: target/riscv/decode_insn32.inc.c \
-       target/riscv/decode_insn16.inc.c
+target/riscv/translate.o: target/riscv/decode_insn32.c.inc \
+       target/riscv/decode_insn16.c.inc

diff --git a/target/riscv/insn_trans/trans_privileged.inc.c b/target/riscv/insn_trans/trans_privileged.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_privileged.inc.c
rename to target/riscv/insn_trans/trans_privileged.c.inc

diff --git a/target/riscv/insn_trans/trans_rva.inc.c b/target/riscv/insn_trans/trans_rva.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rva.inc.c
rename to target/riscv/insn_trans/trans_rva.c.inc

diff --git a/target/riscv/insn_trans/trans_rvd.inc.c b/target/riscv/insn_trans/trans_rvd.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvd.inc.c
rename to target/riscv/insn_trans/trans_rvd.c.inc

diff --git a/target/riscv/insn_trans/trans_rvf.inc.c b/target/riscv/insn_trans/trans_rvf.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvf.inc.c
rename to target/riscv/insn_trans/trans_rvf.c.inc

diff --git a/target/riscv/insn_trans/trans_rvh.inc.c b/target/riscv/insn_trans/trans_rvh.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvh.inc.c
rename to target/riscv/insn_trans/trans_rvh.c.inc

diff --git a/target/riscv/insn_trans/trans_rvi.inc.c b/target/riscv/insn_trans/trans_rvi.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvi.inc.c
rename to target/riscv/insn_trans/trans_rvi.c.inc

diff --git a/target/riscv/insn_trans/trans_rvm.inc.c b/target/riscv/insn_trans/trans_rvm.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvm.inc.c
rename to target/riscv/insn_trans/trans_rvm.c.inc

diff --git a/target/riscv/insn_trans/trans_rvv.inc.c b/target/riscv/insn_trans/trans_rvv.c.inc
similarity index 100%
rename from target/riscv/insn_trans/trans_rvv.inc.c
rename to target/riscv/insn_trans/trans_rvv.c.inc

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 9632e79cf32c03c2abb6473b2c0dc320cb7f09f4..5ef561390903c719775925ecc355143b1f45351d 100644 (file)
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -583,7 +583,7 @@ static int ex_rvc_shifti(DisasContext *ctx, int imm)
 }
 
 /* Include the auto-generated decoder for 32 bit insn */
-#include "decode_insn32.inc.c"
+#include "decode_insn32.c.inc"
 
 static bool gen_arith_imm_fn(DisasContext *ctx, arg_i *a,
                              void (*func)(TCGv, TCGv, target_long))
@@ -718,17 +718,17 @@ static bool gen_shift(DisasContext *ctx, arg_r *a,
 }
 
 /* Include insn module translation function */
-#include "insn_trans/trans_rvi.inc.c"
-#include "insn_trans/trans_rvm.inc.c"
-#include "insn_trans/trans_rva.inc.c"
-#include "insn_trans/trans_rvf.inc.c"
-#include "insn_trans/trans_rvd.inc.c"
-#include "insn_trans/trans_rvh.inc.c"
-#include "insn_trans/trans_rvv.inc.c"
-#include "insn_trans/trans_privileged.inc.c"
+#include "insn_trans/trans_rvi.c.inc"
+#include "insn_trans/trans_rvm.c.inc"
+#include "insn_trans/trans_rva.c.inc"
+#include "insn_trans/trans_rvf.c.inc"
+#include "insn_trans/trans_rvd.c.inc"
+#include "insn_trans/trans_rvh.c.inc"
+#include "insn_trans/trans_rvv.c.inc"
+#include "insn_trans/trans_privileged.c.inc"
 
 /* Include the auto-generated decoder for 16 bit insn */
-#include "decode_insn16.inc.c"
+#include "decode_insn16.c.inc"
 
 static void decode_opc(CPURISCVState *env, DisasContext *ctx, uint16_t opcode)
 {

diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs
index a0018d5bc55576abaf8a536b02911373b34afc4b..cc3c4204a12aeee8adef667b2ac87154d64e864b 100644 (file)
--- a/target/rx/Makefile.objs
+++ b/target/rx/Makefile.objs
@@ -2,10 +2,10 @@ obj-y += translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o
 
 DECODETREE = $(SRC_PATH)/scripts/decodetree.py
 
-target/rx/decode.inc.c: \
+target/rx/decode.c.inc: \
   $(SRC_PATH)/target/rx/insns.decode $(DECODETREE)
        $(call quiet-command,\
          $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR)$@)
 
-target/rx/translate.o: target/rx/decode.inc.c
-target/rx/disas.o: target/rx/decode.inc.c
+target/rx/translate.o: target/rx/decode.c.inc
+target/rx/disas.o: target/rx/decode.c.inc

diff --git a/target/rx/disas.c b/target/rx/disas.c
index 6dee7a0342baf4fcb8cabe95eeaaecc44442a4ca..60eff6f55f405d786cb3aee42a7fbd31aee9c437 100644 (file)
--- a/target/rx/disas.c
+++ b/target/rx/disas.c
@@ -100,7 +100,7 @@ static int bdsp_s(DisasContext *ctx, int d)
 }
 
 /* Include the auto-generated decoder.  */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 static void dump_bytes(DisasContext *ctx)
 {

diff --git a/target/rx/translate.c b/target/rx/translate.c
index 61e86653a41335aa02fa610379b45dd02bc765c5..bc49614cbb7fd61afdcf30ac91ee8cae470d6ce6 100644 (file)
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -124,7 +124,7 @@ static int bdsp_s(DisasContext *ctx, int d)
 }
 
 /* Include the auto-generated decoder. */
-#include "decode.inc.c"
+#include "decode.c.inc"
 
 void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
 {

diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index 4f6f1e31cdfd345542a40ad6b76f60b368b8dd56..a777343821bb9a2cc0ed4e391a98198cc11288e1 100644 (file)
--- a/target/s390x/translate.c
+++ b/target/s390x/translate.c
@@ -5120,7 +5120,7 @@ static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
 }
 #endif
 
-#include "translate_vx.inc.c"
+#include "translate_vx.c.inc"
 
 /* ====================================================================== */
 /* The "Cc OUTput" generators.  Given the generated output (and in some cases

diff --git a/target/s390x/translate_vx.inc.c b/target/s390x/translate_vx.c.inc
similarity index 100%
rename from target/s390x/translate_vx.inc.c
rename to target/s390x/translate_vx.c.inc

diff --git a/target/xtensa/core-dc232b.c b/target/xtensa/core-dc232b.c
index 7851bcb63687d995edff12fa059c6a9c5923d850..c982d09c24b770893537260eb1d90766b62ee54c 100644 (file)
--- a/target/xtensa/core-dc232b.c
+++ b/target/xtensa/core-dc232b.c
@@ -35,13 +35,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_dc232b
-#include "core-dc232b/xtensa-modules.inc.c"
+#include "core-dc232b/xtensa-modules.c.inc"
 
 static XtensaConfig dc232b __attribute__((unused)) = {
     .name = "dc232b",
     .gdb_regmap = {
         .reg = {
-#include "core-dc232b/gdb-config.inc.c"
+#include "core-dc232b/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/target/xtensa/core-dc232b/gdb-config.inc.c b/target/xtensa/core-dc232b/gdb-config.c.inc
similarity index 100%
rename from target/xtensa/core-dc232b/gdb-config.inc.c
rename to target/xtensa/core-dc232b/gdb-config.c.inc

diff --git a/target/xtensa/core-dc232b/xtensa-modules.inc.c b/target/xtensa/core-dc232b/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-dc232b/xtensa-modules.inc.c
rename to target/xtensa/core-dc232b/xtensa-modules.c.inc

diff --git a/target/xtensa/core-dc233c.c b/target/xtensa/core-dc233c.c
index f8204f704529739eea25ed11b1f1bced2f35fcd3..595ab9a90fade96e1e3a0847516ad468dda87537 100644 (file)
--- a/target/xtensa/core-dc233c.c
+++ b/target/xtensa/core-dc233c.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_dc233c
-#include "core-dc233c/xtensa-modules.inc.c"
+#include "core-dc233c/xtensa-modules.c.inc"
 
 static XtensaConfig dc233c __attribute__((unused)) = {
     .name = "dc233c",
     .gdb_regmap = {
         .reg = {
-#include "core-dc233c/gdb-config.inc.c"
+#include "core-dc233c/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/target/xtensa/core-dc233c/gdb-config.inc.c b/target/xtensa/core-dc233c/gdb-config.c.inc
similarity index 100%
rename from target/xtensa/core-dc233c/gdb-config.inc.c
rename to target/xtensa/core-dc233c/gdb-config.c.inc

diff --git a/target/xtensa/core-dc233c/xtensa-modules.inc.c b/target/xtensa/core-dc233c/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-dc233c/xtensa-modules.inc.c
rename to target/xtensa/core-dc233c/xtensa-modules.c.inc

diff --git a/target/xtensa/core-de212.c b/target/xtensa/core-de212.c
index a061158f6e3c50356b1b8c8f3ffb45153c69451e..50c995ba790b0846c399a70cf4f9a453b4d6b653 100644 (file)
--- a/target/xtensa/core-de212.c
+++ b/target/xtensa/core-de212.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_de212
-#include "core-de212/xtensa-modules.inc.c"
+#include "core-de212/xtensa-modules.c.inc"
 
 static XtensaConfig de212 __attribute__((unused)) = {
     .name = "de212",
     .gdb_regmap = {
         .reg = {
-#include "core-de212/gdb-config.inc.c"
+#include "core-de212/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/target/xtensa/core-de212/gdb-config.inc.c b/target/xtensa/core-de212/gdb-config.c.inc
similarity index 100%
rename from target/xtensa/core-de212/gdb-config.inc.c
rename to target/xtensa/core-de212/gdb-config.c.inc

diff --git a/target/xtensa/core-de212/xtensa-modules.inc.c b/target/xtensa/core-de212/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-de212/xtensa-modules.inc.c
rename to target/xtensa/core-de212/xtensa-modules.c.inc

diff --git a/target/xtensa/core-fsf.c b/target/xtensa/core-fsf.c
index 1221a296fa9a9c5f535941be5ff57d9822f2bd99..3327c50b4fb2d1a93e3422b43743e1ad0766dda2 100644 (file)
--- a/target/xtensa/core-fsf.c
+++ b/target/xtensa/core-fsf.c
@@ -34,7 +34,7 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_fsf
-#include "core-fsf/xtensa-modules.inc.c"
+#include "core-fsf/xtensa-modules.c.inc"
 
 static XtensaConfig fsf __attribute__((unused)) = {
     .name = "fsf",

diff --git a/target/xtensa/core-fsf/xtensa-modules.inc.c b/target/xtensa/core-fsf/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-fsf/xtensa-modules.inc.c
rename to target/xtensa/core-fsf/xtensa-modules.c.inc

diff --git a/target/xtensa/core-sample_controller.c b/target/xtensa/core-sample_controller.c
index a1d220bb9a71c62620083b441187320ba84e3586..fd5de5576bab8890bd9e5d64bd6b97fb08e4371f 100644 (file)
--- a/target/xtensa/core-sample_controller.c
+++ b/target/xtensa/core-sample_controller.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_sample_controller
-#include "core-sample_controller/xtensa-modules.inc.c"
+#include "core-sample_controller/xtensa-modules.c.inc"
 
 static XtensaConfig sample_controller __attribute__((unused)) = {
     .name = "sample_controller",
     .gdb_regmap = {
         .reg = {
-#include "core-sample_controller/gdb-config.inc.c"
+#include "core-sample_controller/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/target/xtensa/core-sample_controller/gdb-config.inc.c b/target/xtensa/core-sample_controller/gdb-config.c.inc
similarity index 100%
rename from target/xtensa/core-sample_controller/gdb-config.inc.c
rename to target/xtensa/core-sample_controller/gdb-config.c.inc

diff --git a/target/xtensa/core-sample_controller/xtensa-modules.inc.c b/target/xtensa/core-sample_controller/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-sample_controller/xtensa-modules.inc.c
rename to target/xtensa/core-sample_controller/xtensa-modules.c.inc

diff --git a/target/xtensa/core-test_kc705_be.c b/target/xtensa/core-test_kc705_be.c
index ab73c3885f35973e2403ef5e0ca07fad77c4083a..294c16f2f441c04d86c49e5ada79334a11837c7c 100644 (file)
--- a/target/xtensa/core-test_kc705_be.c
+++ b/target/xtensa/core-test_kc705_be.c
@@ -34,13 +34,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_test_kc705_be
-#include "core-test_kc705_be/xtensa-modules.inc.c"
+#include "core-test_kc705_be/xtensa-modules.c.inc"
 
 static XtensaConfig test_kc705_be __attribute__((unused)) = {
     .name = "test_kc705_be",
     .gdb_regmap = {
         .reg = {
-#include "core-test_kc705_be/gdb-config.inc.c"
+#include "core-test_kc705_be/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/target/xtensa/core-test_kc705_be/gdb-config.inc.c b/target/xtensa/core-test_kc705_be/gdb-config.c.inc
similarity index 100%
rename from target/xtensa/core-test_kc705_be/gdb-config.inc.c
rename to target/xtensa/core-test_kc705_be/gdb-config.c.inc

diff --git a/target/xtensa/core-test_kc705_be/xtensa-modules.inc.c b/target/xtensa/core-test_kc705_be/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-test_kc705_be/xtensa-modules.inc.c
rename to target/xtensa/core-test_kc705_be/xtensa-modules.c.inc

diff --git a/target/xtensa/core-test_mmuhifi_c3.c b/target/xtensa/core-test_mmuhifi_c3.c
index 089ed7da5d37084837dcf157fde6f226467e3d87..123c630b0da7dd25607b8c7f078f1ac886df36ba 100644 (file)
--- a/target/xtensa/core-test_mmuhifi_c3.c
+++ b/target/xtensa/core-test_mmuhifi_c3.c
@@ -35,13 +35,13 @@
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_test_mmuhifi_c3
-#include "core-test_mmuhifi_c3/xtensa-modules.inc.c"
+#include "core-test_mmuhifi_c3/xtensa-modules.c.inc"
 
 static XtensaConfig test_mmuhifi_c3 __attribute__((unused)) = {
     .name = "test_mmuhifi_c3",
     .gdb_regmap = {
         .reg = {
-#include "core-test_mmuhifi_c3/gdb-config.inc.c"
+#include "core-test_mmuhifi_c3/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c b/target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc
similarity index 100%
rename from target/xtensa/core-test_mmuhifi_c3/gdb-config.inc.c
rename to target/xtensa/core-test_mmuhifi_c3/gdb-config.c.inc

diff --git a/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c b/target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc
similarity index 100%
rename from target/xtensa/core-test_mmuhifi_c3/xtensa-modules.inc.c
rename to target/xtensa/core-test_mmuhifi_c3/xtensa-modules.c.inc

diff --git a/target/xtensa/import_core.sh b/target/xtensa/import_core.sh
index 8f844cf9e2a6c3f0bc0789fd5861deb748aace13..c8626a8c02ebb41e2ab9aab3648f1311e329b85e 100755 (executable)
--- a/target/xtensa/import_core.sh
+++ b/target/xtensa/import_core.sh
@@ -23,7 +23,7 @@ tar -xf "$OVERLAY" -C "$TARGET" --strip-components=2 \
     xtensa/config/core-isa.h \
     xtensa/config/core-matmap.h
 tar -xf "$OVERLAY" -O gdb/xtensa-config.c | \
-    sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.inc.c
+    sed -n '1,/*\//p;/XTREG/,/XTREG_END/p' > "$TARGET"/gdb-config.c.inc
 #
 # Fix up known issues in the xtensa-modules.c
 #
@@ -35,7 +35,7 @@ tar -xf "$OVERLAY" -O binutils/xtensa-modules.c | \
         -e '/^#include "ansidecl.h"/d' \
         -e '/^Slot_[a-zA-Z0-9_]\+_decode (const xtensa_insnbuf insn)/,/^}/s/^  return 0;$/  return XTENSA_UNDEFINED;/' \
         -e 's/#include <xtensa-isa.h>/#include "xtensa-isa.h"/' \
-    > "$TARGET"/xtensa-modules.inc.c
+    > "$TARGET"/xtensa-modules.c.inc
 
 cat <<EOF > "${TARGET}.c"
 #include "qemu/osdep.h"
@@ -49,13 +49,13 @@ cat <<EOF > "${TARGET}.c"
 #include "overlay_tool.h"
 
 #define xtensa_modules xtensa_modules_$NAME
-#include "core-$NAME/xtensa-modules.inc.c"
+#include "core-$NAME/xtensa-modules.c.inc"
 
 static XtensaConfig $NAME __attribute__((unused)) = {
     .name = "$NAME",
     .gdb_regmap = {
         .reg = {
-#include "core-$NAME/gdb-config.inc.c"
+#include "core-$NAME/gdb-config.c.inc"
         }
     },
     .isa_internal = &xtensa_modules,

diff --git a/tcg/README b/tcg/README
index a64f67809b8bd639d7d96d4ea496e28e6c7dccf7..2f051e5c970977ac4d7d0155f50215da44f6e738 100644 (file)
--- a/tcg/README
+++ b/tcg/README
@@ -652,7 +652,7 @@ function tcg_gen_xxx(args).
 
 4) Backend
 
-tcg-target.h contains the target specific definitions. tcg-target.inc.c
+tcg-target.h contains the target specific definitions. tcg-target.c.inc
 contains the target specific code; it is #included by tcg/tcg.c, rather
 than being a standalone C file.
 

diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.c.inc
similarity index 99%
rename from tcg/aarch64/tcg-target.inc.c
rename to tcg/aarch64/tcg-target.c.inc
index 760b0e742db2f798a2c185ed096feb4be53c7d52..948c35d82599bb6c9919bad254534dda7347cec2 100644 (file)
--- a/tcg/aarch64/tcg-target.inc.c
+++ b/tcg/aarch64/tcg-target.c.inc
@@ -10,7 +10,7 @@
  * See the COPYING file in the top-level directory for details.
  */
 
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 #include "qemu/bitops.h"
 
 /* We're going to re-use TCGType in setting of the SF bit, which controls
@@ -1542,7 +1542,7 @@ static void tcg_out_cltz(TCGContext *s, TCGType ext, TCGReg d,
 }
 
 #ifdef CONFIG_SOFTMMU
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     TCGMemOpIdx oi, uintptr_t ra)

diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.c.inc
similarity index 99%
rename from tcg/arm/tcg-target.inc.c
rename to tcg/arm/tcg-target.c.inc
index 6aa7757aac630a4f5cd7dcf3fbee7ec123abf2a3..bc1e1b5a710f83b7f17a7e55b4f1e987a9c7ab7c 100644 (file)
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.c.inc
@@ -23,7 +23,7 @@
  */
 
 #include "elf.h"
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 
 int arm_arch = __ARM_ARCH;
 
@@ -1131,7 +1131,7 @@ static TCGCond tcg_out_cmp2(TCGContext *s, const TCGArg *args,
 }
 
 #ifdef CONFIG_SOFTMMU
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     int mmu_idx, uintptr_t ra)

diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.c.inc
similarity index 99%
rename from tcg/i386/tcg-target.inc.c
rename to tcg/i386/tcg-target.c.inc
index ae0228238b456e0e7c41fc7adc5047b9da2ac202..0155c0691c9763dc65530d6eaedd1c28fe5c913e 100644 (file)
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.c.inc
@@ -22,7 +22,7 @@
  * THE SOFTWARE.
  */
 
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@@ -1647,7 +1647,7 @@ static void tcg_out_nopn(TCGContext *s, int n)
 }
 
 #if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     int mmu_idx, uintptr_t ra)

diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.c.inc
similarity index 99%
rename from tcg/mips/tcg-target.inc.c
rename to tcg/mips/tcg-target.c.inc
index 4d32ebc1df60cfe1f4d2fe63414c13ff431f7790..bd5b8e09a099cfaabdd0094561ff535dea471ddc 100644 (file)
--- a/tcg/mips/tcg-target.inc.c
+++ b/tcg/mips/tcg-target.c.inc
@@ -1107,7 +1107,7 @@ static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
 }
 
 #if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 static void * const qemu_ld_helpers[16] = {
     [MO_UB]   = helper_ret_ldub_mmu,

diff --git a/tcg/ppc/tcg-target.inc.c b/tcg/ppc/tcg-target.c.inc
similarity index 99%
rename from tcg/ppc/tcg-target.inc.c
rename to tcg/ppc/tcg-target.c.inc
index c8d1e765d98ea80a2d02e67e555186166778d4f4..3bef3789b328dac07ac4900874138893e89f5943 100644 (file)
--- a/tcg/ppc/tcg-target.inc.c
+++ b/tcg/ppc/tcg-target.c.inc
@@ -23,7 +23,7 @@
  */
 
 #include "elf.h"
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 
 #if defined _CALL_DARWIN || defined __APPLE__
 #define TCG_TARGET_CALL_DARWIN
@@ -1845,7 +1845,7 @@ static const uint32_t qemu_exts_opc[4] = {
 };
 
 #if defined (CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
  *                                 int mmu_idx, uintptr_t ra)

diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.c.inc
similarity index 99%
rename from tcg/riscv/tcg-target.inc.c
rename to tcg/riscv/tcg-target.c.inc
index 3c11ab8b7ad5084e239c14e55fac105e355b4d73..2dfb07e2472b073085dd96b3dca5ec02301bbc6c 100644 (file)
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.c.inc
@@ -27,7 +27,7 @@
  * THE SOFTWARE.
  */
 
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
@@ -919,7 +919,7 @@ static void tcg_out_mb(TCGContext *s, TCGArg a0)
  */
 
 #if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 /* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
  *                                     TCGMemOpIdx oi, uintptr_t ra)

diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.c.inc
similarity index 99%
rename from tcg/s390/tcg-target.inc.c
rename to tcg/s390/tcg-target.c.inc
index b07e9ff7d66c747d9f9aa2b8386d42909b032d19..985115acfb09b4962e5a58ce092235babb46480a 100644 (file)
--- a/tcg/s390/tcg-target.inc.c
+++ b/tcg/s390/tcg-target.c.inc
@@ -29,7 +29,7 @@
 #error "unsupported code generation mode"
 #endif
 
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 #include "elf.h"
 
 /* ??? The translation blocks produced by TCG are generally small enough to
@@ -1536,7 +1536,7 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp opc, TCGReg data,
 }
 
 #if defined(CONFIG_SOFTMMU)
-#include "../tcg-ldst.inc.c"
+#include "../tcg-ldst.c.inc"
 
 /* We're expecting to use a 20-bit negative offset on the tlb memory ops.  */
 QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);

diff --git a/tcg/sparc/tcg-target.inc.c b/tcg/sparc/tcg-target.c.inc
similarity index 99%
rename from tcg/sparc/tcg-target.inc.c
rename to tcg/sparc/tcg-target.c.inc
index 65fddb310d4b42a0986657de45c3fc15be648e29..0f1d91fc21597f1433b39f2c3b36bdc1c7e5bc6e 100644 (file)
--- a/tcg/sparc/tcg-target.inc.c
+++ b/tcg/sparc/tcg-target.c.inc
@@ -22,7 +22,7 @@
  * THE SOFTWARE.
  */
 
-#include "../tcg-pool.inc.c"
+#include "../tcg-pool.c.inc"
 
 #ifdef CONFIG_DEBUG_TCG
 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {

diff --git a/tcg/tcg-ldst.inc.c b/tcg/tcg-ldst.c.inc
similarity index 100%
rename from tcg/tcg-ldst.inc.c
rename to tcg/tcg-ldst.c.inc

diff --git a/tcg/tcg-pool.inc.c b/tcg/tcg-pool.c.inc
similarity index 99%
rename from tcg/tcg-pool.inc.c
rename to tcg/tcg-pool.c.inc
index 4eaa84b63191854dc10044d40c34344b8920d364..82cbcc89bd83e9fe5bff38c6956d3f6a7ebd96d3 100644 (file)
--- a/tcg/tcg-pool.inc.c
+++ b/tcg/tcg-pool.c.inc
@@ -118,7 +118,7 @@ static inline void new_pool_l8(TCGContext *s, int rtype, tcg_insn_unit *label,
     new_pool_insert(s, n);
 }
 
-/* To be provided by cpu/tcg-target.inc.c.  */
+/* To be provided by cpu/tcg-target.c.inc.  */
 static void tcg_out_nop_fill(tcg_insn_unit *p, int count);
 
 static int tcg_out_pool_finalize(TCGContext *s)

diff --git a/tcg/tcg.c b/tcg/tcg.c
index 1362bc61017ba78ade49e47539d634a85b4f162e..62f299e36e5a02bef82d9746727942f1f78305fa 100644 (file)
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
@@ -65,7 +65,7 @@
 #include "exec/log.h"
 #include "sysemu/sysemu.h"
 
-/* Forward declarations for functions declared in tcg-target.inc.c and
+/* Forward declarations for functions declared in tcg-target.c.inc and
    used here. */
 static void tcg_target_init(TCGContext *s);
 static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode);
@@ -101,7 +101,7 @@ static void tcg_register_jit_int(void *buf, size_t size,
                                  size_t debug_frame_size)
     __attribute__((unused));
 
-/* Forward declarations for functions declared and used in tcg-target.inc.c. */
+/* Forward declarations for functions declared and used in tcg-target.c.inc. */
 static const char *target_parse_constraint(TCGArgConstraint *ct,
                                            const char *ct_str, TCGType type);
 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
@@ -341,7 +341,7 @@ static void set_jmp_reset_offset(TCGContext *s, int which)
     assert(s->tb_jmp_reset_offset[which] == off);
 }
 
-#include "tcg-target.inc.c"
+#include "tcg-target.c.inc"
 
 /* compare a pointer @ptr and a tb_tc @s */
 static int ptr_cmp_tb_tc(const void *ptr, const struct tb_tc *s)

diff --git a/tcg/tci/README b/tcg/tci/README
index 386c3c7507547b598d48b3b3e2d5729e51e514d6..9bb7d7a5d399e6d1e0dff56354f053e94d9fcdc6 100644 (file)
--- a/tcg/tci/README
+++ b/tcg/tci/README
@@ -21,7 +21,7 @@ This is what TCI (Tiny Code Interpreter) does.
 2) Implementation
 
 Like each TCG host frontend, TCI implements the code generator in
-tcg-target.inc.c, tcg-target.h. Both files are in directory tcg/tci.
+tcg-target.c.inc, tcg-target.h. Both files are in directory tcg/tci.
 
 The additional file tcg/tci.c adds the interpreter.
 
@@ -123,7 +123,7 @@ u1 = linux-user-test works
   would also improve speed for hosts which support byte alignment).
 
 * A better disassembler for the pseudo code would be nice (a very primitive
-  disassembler is included in tcg-target.inc.c).
+  disassembler is included in tcg-target.c.inc).
 
 * It might be useful to have a runtime option which selects the native TCG
   or TCI, so QEMU would have to include two TCGs. Today, selecting TCI

diff --git a/tcg/tci/tcg-target.inc.c b/tcg/tci/tcg-target.c.inc
similarity index 100%
rename from tcg/tci/tcg-target.inc.c
rename to tcg/tci/tcg-target.c.inc

diff --git a/tests/fp/fp-test.c b/tests/fp/fp-test.c
index 43ef9628c41c9740b0a8c9e573bfa7142fcc0a31..06ffebd6db17ad5af7fbacc81af5cf800c5d2d66 100644 (file)
--- a/tests/fp/fp-test.c
+++ b/tests/fp/fp-test.c
@@ -116,7 +116,7 @@ static void usage_complete(int argc, char *argv[])
 }
 
 /* keep wrappers separate but do not bother defining headers for all of them */
-#include "wrap.inc.c"
+#include "wrap.c.inc"
 
 static void not_implemented(void)
 {

diff --git a/tests/fp/wrap.inc.c b/tests/fp/wrap.c.inc
similarity index 100%
rename from tests/fp/wrap.inc.c
rename to tests/fp/wrap.c.inc

diff --git a/ui/input-keymap.c b/ui/input-keymap.c
index c4301851bd2428f50cede5c0ab5ab6e5fc50b202..1b756a6970c0049942486efff2f8ce61815c3f26 100644 (file)
--- a/ui/input-keymap.c
+++ b/ui/input-keymap.c
@@ -4,23 +4,23 @@
 
 #include "standard-headers/linux/input.h"
 
-#include "ui/input-keymap-atset1-to-qcode.c"
-#include "ui/input-keymap-linux-to-qcode.c"
-#include "ui/input-keymap-qcode-to-atset1.c"
-#include "ui/input-keymap-qcode-to-atset2.c"
-#include "ui/input-keymap-qcode-to-atset3.c"
-#include "ui/input-keymap-qcode-to-linux.c"
-#include "ui/input-keymap-qcode-to-qnum.c"
-#include "ui/input-keymap-qcode-to-sun.c"
-#include "ui/input-keymap-qnum-to-qcode.c"
-#include "ui/input-keymap-usb-to-qcode.c"
-#include "ui/input-keymap-win32-to-qcode.c"
-#include "ui/input-keymap-x11-to-qcode.c"
-#include "ui/input-keymap-xorgevdev-to-qcode.c"
-#include "ui/input-keymap-xorgkbd-to-qcode.c"
-#include "ui/input-keymap-xorgxquartz-to-qcode.c"
-#include "ui/input-keymap-xorgxwin-to-qcode.c"
-#include "ui/input-keymap-osx-to-qcode.c"
+#include "ui/input-keymap-atset1-to-qcode.c.inc"
+#include "ui/input-keymap-linux-to-qcode.c.inc"
+#include "ui/input-keymap-qcode-to-atset1.c.inc"
+#include "ui/input-keymap-qcode-to-atset2.c.inc"
+#include "ui/input-keymap-qcode-to-atset3.c.inc"
+#include "ui/input-keymap-qcode-to-linux.c.inc"
+#include "ui/input-keymap-qcode-to-qnum.c.inc"
+#include "ui/input-keymap-qcode-to-sun.c.inc"
+#include "ui/input-keymap-qnum-to-qcode.c.inc"
+#include "ui/input-keymap-usb-to-qcode.c.inc"
+#include "ui/input-keymap-win32-to-qcode.c.inc"
+#include "ui/input-keymap-x11-to-qcode.c.inc"
+#include "ui/input-keymap-xorgevdev-to-qcode.c.inc"
+#include "ui/input-keymap-xorgkbd-to-qcode.c.inc"
+#include "ui/input-keymap-xorgxquartz-to-qcode.c.inc"
+#include "ui/input-keymap-xorgxwin-to-qcode.c.inc"
+#include "ui/input-keymap-osx-to-qcode.c.inc"
 
 int qemu_input_linux_to_qcode(unsigned int lnx)
 {

diff --git a/ui/vnc-enc-zrle.c b/ui/vnc-enc-zrle.c
index b4f71e32cfe8ca3dd645103f999db618469d5f6d..bd33b890639f47367e22191e4b4caf89ac7a2883 100644 (file)
--- a/ui/vnc-enc-zrle.c
+++ b/ui/vnc-enc-zrle.c
@@ -199,56 +199,56 @@ static void zrle_write_u8(VncState *vs, uint8_t value)
 
 #define ZRLE_BPP 8
 #define ZYWRLE_ENDIAN ENDIAN_NO
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 #undef ZRLE_BPP
 
 #define ZRLE_BPP 15
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZRLE_BPP
 #define ZRLE_BPP 16
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZRLE_BPP
 #define ZRLE_BPP 32
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #define ZRLE_COMPACT_PIXEL 24a
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZRLE_COMPACT_PIXEL
 #define ZRLE_COMPACT_PIXEL 24b
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_LITTLE
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 
 #undef ZYWRLE_ENDIAN
 #define ZYWRLE_ENDIAN ENDIAN_BIG
-#include "vnc-enc-zrle.inc.c"
+#include "vnc-enc-zrle.c.inc"
 #undef ZRLE_COMPACT_PIXEL
 #undef ZRLE_BPP
 

diff --git a/ui/vnc-enc-zrle.inc.c b/ui/vnc-enc-zrle.c.inc
similarity index 100%
rename from ui/vnc-enc-zrle.inc.c
rename to ui/vnc-enc-zrle.c.inc