return regno;
}
+/* Parse list of up to eight 64-bit element tile names separated by commas in
+ SME's ZERO instruction:
+
+ ZERO { <mask> }
+
+ Function returns <mask>:
+
+ an 8-bit list of 64-bit element tiles named ZA0.D to ZA7.D.
+*/
+static int
+parse_sme_zero_mask(char **str)
+{
+ char *q;
+ int mask;
+ aarch64_opnd_qualifier_t qualifier;
+
+ mask = 0x00;
+ q = *str;
+ do
+ {
+ const reg_entry *reg = parse_reg_with_qual (&q, REG_TYPE_ZA, &qualifier);
+ if (reg)
+ {
+ int regno = reg->number;
+ if (qualifier == AARCH64_OPND_QLF_S_B && regno == 0)
+ {
+ /* { ZA0.B } is assembled as all-ones immediate. */
+ mask = 0xff;
+ }
+ else if (qualifier == AARCH64_OPND_QLF_S_H && regno < 2)
+ mask |= 0x55 << regno;
+ else if (qualifier == AARCH64_OPND_QLF_S_S && regno < 4)
+ mask |= 0x11 << regno;
+ else if (qualifier == AARCH64_OPND_QLF_S_D && regno < 8)
+ mask |= 0x01 << regno;
+ else
+ {
+ set_syntax_error (_("wrong ZA tile element format"));
+ return PARSE_FAIL;
+ }
+ continue;
+ }
+ else if (strncasecmp (q, "za", 2) == 0
+ && !ISALNUM (q[2]))
+ {
+ /* { ZA } is assembled as all-ones immediate. */
+ mask = 0xff;
+ q += 2;
+ continue;
+ }
+ else
+ {
+ set_syntax_error (_("wrong ZA tile element format"));
+ return PARSE_FAIL;
+ }
+ }
+ while (skip_past_char (&q, ','));
+
+ *str = q;
+ return mask;
+}
+
+/* Wraps in curly braces <mask> operand ZERO instruction:
+
+ ZERO { <mask> }
+
+ Function returns value of <mask> bit-field.
+*/
+static int
+parse_sme_list_of_64bit_tiles (char **str)
+{
+ int regno;
+
+ if (!skip_past_char (str, '{'))
+ {
+ set_syntax_error (_("expected '{'"));
+ return PARSE_FAIL;
+ }
+
+ /* Empty <mask> list is an all-zeros immediate. */
+ if (!skip_past_char (str, '}'))
+ {
+ regno = parse_sme_zero_mask (str);
+ if (regno == PARSE_FAIL)
+ return PARSE_FAIL;
+
+ if (!skip_past_char (str, '}'))
+ {
+ set_syntax_error (_("expected '}'"));
+ return PARSE_FAIL;
+ }
+ }
+ else
+ regno = 0x00;
+
+ return regno;
+}
/* Parse a system register or a PSTATE field name for an MSR/MRS instruction.
Returns the encoding for the option, or PARSE_FAIL.
break;
}
+ case AARCH64_OPND_SME_list_of_64bit_tiles:
+ val = parse_sme_list_of_64bit_tiles (&str);
+ if (val == PARSE_FAIL)
+ goto failure;
+ info->imm.value = val;
+ break;
+
default:
as_fatal (_("unhandled operand code %d"), operands[i]);
}
--- /dev/null
+#as: -march=armv8-a+sme
+#source: sme-4-illegal.s
+#error_output: sme-4-illegal.l
--- /dev/null
+[^:]*: Assembler messages:
+[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero za'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za8\.d}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0\.d,za8.d}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za2\.h}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za4\.s}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za1\.s,za4.s}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0\.d,za3.s,za2.h}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za1.b}'
+[^:]*:[0-9]+: Error: unexpected comma after the mnemonic name `zero' -- `zero ,'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,'
+[^:]*:[0-9]+: Error: expected '{' at operand 1 -- `zero }'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,,}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {,za0.d}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0.d,}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0.d,za1.d,}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za,}'
+[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za.}'
+[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za-}'
+[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za_}'
+[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za#}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {zaX}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {za0}'
+[^:]*:[0-9]+: Error: wrong ZA tile element format at operand 1 -- `zero {zax}'
+[^:]*:[0-9]+: Error: expected '}' at operand 1 -- `zero {za{}'
+[^:]*:[0-9]+: Error: unexpected characters following instruction at operand 1 -- `zero {za}}'
--- /dev/null
+/* Scalable Matrix Extension (SME). */
+
+zero za
+zero { za8.d }
+zero { za0.d, za8.d }
+zero { za2.h }
+zero { za4.s }
+zero { za1.s, za4.s }
+zero { za0.d, za3.s, za2.h }
+zero { za1.b }
+
+/* Parser checks. */
+zero ,
+zero {
+zero { ,
+zero }
+zero { , }
+zero { , , }
+zero { za0 }
+zero { , za0.d }
+zero { za0.d , }
+zero { za0.d , za1.d , }
+zero { za, }
+zero { za. }
+zero { za- }
+zero { za_ }
+zero { za# }
+zero { zaX }
+zero { za0 }
+zero { zax }
+zero { za{ }
+zero { za} }
--- /dev/null
+#name: SME extension (ZERO)
+#as: -march=armv8-a+sme
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <.*>:
+ 0: c0080000 zero {}
+ 4: c00800ff zero {za}
+ 8: c00800ff zero {za}
+ c: c00800ff zero {za}
+ 10: c00800ff zero {za}
+ 14: c00800ff zero {za}
+ 18: c0080001 zero {za0\.d}
+ 1c: c0080002 zero {za1\.d}
+ 20: c0080004 zero {za2\.d}
+ 24: c0080008 zero {za3\.d}
+ 28: c0080010 zero {za4\.d}
+ 2c: c0080020 zero {za5\.d}
+ 30: c0080040 zero {za6\.d}
+ 34: c0080080 zero {za7\.d}
+ 38: c0080001 zero {za0\.d}
+ 3c: c0080003 zero {za0\.d, za1\.d}
+ 40: c0080007 zero {za0\.d, za1\.d, za2\.d}
+ 44: c008000f zero {za0\.d, za1\.d, za2\.d, za3\.d}
+ 48: c008001f zero {za0\.s, za1\.d, za2\.d, za3\.d}
+ 4c: c008003f zero {za0\.s, za1\.s, za2\.d, za3\.d}
+ 50: c008007f zero {za0\.h, za1\.s, za3\.d}
+ 54: c00800ff zero {za}
+ 58: c0080080 zero {za7\.d}
+ 5c: c00800c0 zero {za6\.d, za7\.d}
+ 60: c00800e0 zero {za5\.d, za6\.d, za7\.d}
+ 64: c00800f0 zero {za4\.d, za5\.d, za6\.d, za7\.d}
+ 68: c00800f8 zero {za3\.s, za4\.d, za5\.d, za6\.d}
+ 6c: c00800fc zero {za2\.s, za3\.s, za4\.d, za5\.d}
+ 70: c00800fe zero {za1\.h, za2\.s, za4\.d}
+ 74: c00800ff zero {za}
+ 78: c00800fe zero {za1\.h, za2\.s, za4\.d}
+ 7c: c00800fd zero {za0\.h, za3\.s, za5\.d}
+ 80: c00800fb zero {za1\.h, za0\.s, za6\.d}
+ 84: c00800f7 zero {za0\.h, za1\.s, za7\.d}
+ 88: c00800ef zero {za1\.h, za2\.s, za0\.d}
+ 8c: c00800df zero {za0\.h, za3\.s, za1\.d}
+ 90: c00800bf zero {za1\.h, za0\.s, za2\.d}
+ 94: c008007f zero {za0\.h, za1\.s, za3\.d}
+ 98: c0080055 zero {za0\.h}
+ 9c: c00800aa zero {za1\.h}
+ a0: c0080011 zero {za0\.s}
+ a4: c0080022 zero {za1\.s}
+ a8: c0080044 zero {za2\.s}
+ ac: c0080088 zero {za3\.s}
+ b0: c0080055 zero {za0\.h}
+ b4: c0080055 zero {za0\.h}
+ b8: c0080055 zero {za0\.h}
+ bc: c00800aa zero {za1\.h}
+ c0: c00800aa zero {za1\.h}
+ c4: c00800aa zero {za1\.h}
+ c8: c0080011 zero {za0\.s}
+ cc: c0080022 zero {za1\.s}
+ d0: c0080044 zero {za2\.s}
+ d4: c0080088 zero {za3\.s}
+ d8: c00800d5 zero {za0.h, za7.d}
+ dc: c00800ab zero {za1.h, za0.d}
+ e0: c0080015 zero {za0.s, za2.d}
+ e4: c008002a zero {za1.s, za3.d}
+ e8: c0080054 zero {za2.s, za4.d}
+ ec: c00800a8 zero {za3.s, za5.d}
+ f0: c00800d5 zero {za0.h, za7.d}
+ f4: c0080015 zero {za0.s, za2.d}
--- /dev/null
+/* SME Extension (ZERO). */
+
+/* An all-zeros immediate is disassembled as an empty list { }. */
+zero { }
+
+/* An all-ones immediate is disassembled as {ZA}. */
+zero { za }
+zero { za0.b }
+zero { za0.h, za1.h }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d }
+zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d, za1.d, za0.d }
+
+/* Set each bit individually. */
+zero { za0.d }
+zero { za1.d }
+zero { za2.d }
+zero { za3.d }
+zero { za4.d }
+zero { za5.d }
+zero { za6.d }
+zero { za7.d }
+
+/* Random bits. */
+zero { za0.d }
+zero { za0.d, za1.d }
+zero { za0.d, za1.d, za2.d }
+zero { za0.d, za1.d, za2.d, za3.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d }
+
+zero { za7.d }
+zero { za7.d, za6.d }
+zero { za7.d, za6.d, za5.d }
+zero { za7.d, za6.d, za5.d, za4.d }
+zero { za7.d, za6.d, za5.d, za4.d, za3.d }
+zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d }
+zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d, za1.d }
+zero { za7.d, za6.d, za5.d, za4.d, za3.d, za2.d, za1.d, za0.d }
+
+zero { za1.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d }
+zero { za0.d, za2.d, za3.d, za4.d, za5.d, za6.d, za7.d }
+zero { za0.d, za1.d, za3.d, za4.d, za5.d, za6.d, za7.d }
+zero { za0.d, za1.d, za2.d, za4.d, za5.d, za6.d, za7.d }
+zero { za0.d, za1.d, za2.d, za3.d, za5.d, za6.d, za7.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za6.d, za7.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za7.d }
+zero { za0.d, za1.d, za2.d, za3.d, za4.d, za5.d, za6.d }
+
+/* For programmer convenience an assembler must also accept the names of
+ 32-bit, 16-bit and 8-bit element tiles.
+*/
+zero { za0.h }
+zero { za1.h }
+zero { za0.s }
+zero { za1.s }
+zero { za2.s }
+zero { za3.s }
+
+/* The preferred disassembly of this instruction uses the shortest list of tile
+ names that represent the encoded immediate mask.
+*/
+
+/* To za0.h */
+zero { za0.d, za2.d, za4.d, za6.d }
+zero { za0.s, za2.s }
+zero { za0.h }
+
+/* To za1.h */
+zero { za1.d, za3.d, za5.d, za7.d }
+zero { za1.s, za3.s }
+zero { za1.h }
+
+/* To za[0-3].s */
+zero { za0.d, za4.d }
+zero { za1.d, za5.d }
+zero { za2.d, za6.d }
+zero { za3.d, za7.d }
+
+/* Mix of suffixed. */
+zero { za0.h, za7.d }
+zero { za1.h, za0.d }
+zero { za0.s, za2.d }
+zero { za1.s, za3.d }
+zero { za2.s, za4.d }
+zero { za3.s, za5.d }
+
+/* Register aliases. */
+foo .req za0
+bar .req za2
+baz .req za7
+
+zero { foo.h, baz.d }
+zero { za0.s, bar.d }
AARCH64_OPND_SME_ZA_HV_idx_src, /* SME source ZA tile vector. */
AARCH64_OPND_SME_ZA_HV_idx_dest, /* SME destination ZA tile vector. */
AARCH64_OPND_SME_Pm, /* SME scalable predicate register, bits [15:13]. */
+ AARCH64_OPND_SME_list_of_64bit_tiles, /* SME list of ZA tiles. */
AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
};
case 33:
case 34:
case 35:
- case 215:
+ case 216:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ins_reglist (self, info, code, inst, errors);
case 188:
case 189:
case 214:
+ case 215:
return aarch64_ins_imm (self, info, code, inst, errors);
case 44:
case 45:
{
if (((word >> 17) & 0x1) == 0)
{
- if (((word >> 20) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx00xx0xxxxxxxxxxxxxxxxx
- mov. */
- return 2377;
- }
- else
+ if (((word >> 19) & 0x1) == 0)
{
- if (((word >> 16) & 0x1) == 0)
+ if (((word >> 20) & 0x1) == 0)
{
- if (((word >> 22) & 0x1) == 0)
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x001xx00xxxxxxxxxxxxxxxx
- addha. */
- return 2348;
- }
- else
- {
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x101xx00xxxxxxxxxxxxxxxx
- addha. */
- return 2349;
- }
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx000x0xxxxxxxxxxxxxxxxx
+ mov. */
+ return 2377;
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 16) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x001xx01xxxxxxxxxxxxxxxx
- addva. */
- return 2350;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x0010x00xxxxxxxxxxxxxxxx
+ addha. */
+ return 2348;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x1010x00xxxxxxxxxxxxxxxx
+ addha. */
+ return 2349;
+ }
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x101xx01xxxxxxxxxxxxxxxx
- addva. */
- return 2351;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x0010x01xxxxxxxxxxxxxxxx
+ addva. */
+ return 2350;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x1010x01xxxxxxxxxxxxxxxx
+ addva. */
+ return 2351;
+ }
}
}
}
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx0x1x0xxxxxxxxxxxxxxxxx
+ zero. */
+ return 2380;
+ }
}
else
{
10987654321098765432109876543210
00011001000xxxxxxxxx00xxxxxxxxxx
stlurb. */
- return 2420;
+ return 2421;
}
else
{
10987654321098765432109876543210
10011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2428;
+ return 2429;
}
}
else
10987654321098765432109876543210
01011001000xxxxxxxxx00xxxxxxxxxx
stlurh. */
- return 2424;
+ return 2425;
}
else
{
10987654321098765432109876543210
11011001000xxxxxxxxx00xxxxxxxxxx
stlur. */
- return 2431;
+ return 2432;
}
}
}
10987654321098765432109876543210
00011001010xxxxxxxxx00xxxxxxxxxx
ldapurb. */
- return 2421;
+ return 2422;
}
else
{
10987654321098765432109876543210
10011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2429;
+ return 2430;
}
}
else
10987654321098765432109876543210
01011001010xxxxxxxxx00xxxxxxxxxx
ldapurh. */
- return 2425;
+ return 2426;
}
else
{
10987654321098765432109876543210
11011001010xxxxxxxxx00xxxxxxxxxx
ldapur. */
- return 2432;
+ return 2433;
}
}
}
10987654321098765432109876543210
00011001100xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2423;
+ return 2424;
}
else
{
10987654321098765432109876543210
10011001100xxxxxxxxx00xxxxxxxxxx
ldapursw. */
- return 2430;
+ return 2431;
}
}
else
10987654321098765432109876543210
x1011001100xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2427;
+ return 2428;
}
}
else
10987654321098765432109876543210
x0011001110xxxxxxxxx00xxxxxxxxxx
ldapursb. */
- return 2422;
+ return 2423;
}
else
{
10987654321098765432109876543210
x1011001110xxxxxxxxx00xxxxxxxxxx
ldapursh. */
- return 2426;
+ return 2427;
}
}
}
10987654321098765432109876543210
xxx11010x00xxxxxx0xx10xxxxxxxxxx
setf8. */
- return 2418;
+ return 2419;
}
else
{
10987654321098765432109876543210
xxx11010x00xxxxxx1xx10xxxxxxxxxx
setf16. */
- return 2419;
+ return 2420;
}
}
else
10987654321098765432109876543210
xxx11010000xxxxxxxxx01xxxxxxxxxx
rmif. */
- return 2417;
+ return 2418;
}
else
{
10987654321098765432109876543210
010001x01x1xxxxx000110xxxxxxxxxx
usdot. */
- return 2437;
+ return 2438;
}
}
}
10987654321098765432109876543210
010001x01x1xxxxx000111xxxxxxxxxx
sudot. */
- return 2438;
+ return 2439;
}
}
}
10987654321098765432109876543210
010001x0xx0xxxxx011110xxxxxxxxxx
usdot. */
- return 2436;
+ return 2437;
}
}
}
10987654321098765432109876543210
011001x0100xxx10101xxxxxxxxxxxxx
bfcvtnt. */
- return 2465;
+ return 2466;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxxx00xxxxxxxxxxxxx
ld1rob. */
- return 2441;
+ return 2442;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxxx00xxxxxxxxxxxxx
ld1roh. */
- return 2442;
+ return 2443;
}
}
else
10987654321098765432109876543210
011001x0011xxxxx010xxxxxxxxxxxxx
bfdot. */
- return 2462;
+ return 2463;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx0xxxxxxxxxx
bfmlalb. */
- return 2469;
+ return 2470;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx010xx1xxxxxxxxxx
bfmlalt. */
- return 2468;
+ return 2469;
}
}
else
10987654321098765432109876543210
x11001x0011xxxxx1x0xxxxxxxxxxxxx
bfdot. */
- return 2461;
+ return 2462;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx0xxxxxxxxxx
bfmlalb. */
- return 2467;
+ return 2468;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx1x0xx1xxxxxxxxxx
bfmlalt. */
- return 2466;
+ return 2467;
}
}
else
10987654321098765432109876543210
101001x00x1xxxxx001xxxxxxxxxxxxx
ld1rob. */
- return 2445;
+ return 2446;
}
else
{
10987654321098765432109876543210
101001x01x1xxxxx001xxxxxxxxxxxxx
ld1roh. */
- return 2446;
+ return 2447;
}
}
else
10987654321098765432109876543210
011001x0101xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2439;
+ return 2440;
}
else
{
10987654321098765432109876543210
011001x0011xxxxx111xxxxxxxxxxxxx
bfmmla. */
- return 2463;
+ return 2464;
}
else
{
10987654321098765432109876543210
011001x0111xxxxx111xxxxxxxxxxxxx
fmmla. */
- return 2440;
+ return 2441;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000x00xxxxxxxxxx
zip1. */
- return 2449;
+ return 2450;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000010xxxxxxxxxx
uzp1. */
- return 2451;
+ return 2452;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000110xxxxxxxxxx
trn1. */
- return 2453;
+ return 2454;
}
}
}
10987654321098765432109876543210
000001x1101xxxxx000x01xxxxxxxxxx
zip2. */
- return 2450;
+ return 2451;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000011xxxxxxxxxx
uzp2. */
- return 2452;
+ return 2453;
}
else
{
10987654321098765432109876543210
000001x1101xxxxx000111xxxxxxxxxx
trn2. */
- return 2454;
+ return 2455;
}
}
}
10987654321098765432109876543210
010001x1000xxxxx100110xxxxxxxxxx
smmla. */
- return 2433;
+ return 2434;
}
else
{
10987654321098765432109876543210
010001x1100xxxxx100110xxxxxxxxxx
usmmla. */
- return 2435;
+ return 2436;
}
}
else
10987654321098765432109876543210
010001x1x10xxxxx100110xxxxxxxxxx
ummla. */
- return 2434;
+ return 2435;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx000xxxxxxxxxxxxx
ld1row. */
- return 2443;
+ return 2444;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx000xxxxxxxxxxxxx
ld1rod. */
- return 2444;
+ return 2445;
}
}
}
10987654321098765432109876543210
101001x10x1xxxxx001xxxxxxxxxxxxx
ld1row. */
- return 2447;
+ return 2448;
}
else
{
10987654321098765432109876543210
101001x11x1xxxxx001xxxxxxxxxxxxx
ld1rod. */
- return 2448;
+ return 2449;
}
}
}
10987654321098765432109876543210
011001x110001x10101xxxxxxxxxxxxx
bfcvt. */
- return 2464;
+ return 2465;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1001xxxxxxxxxx
smmla. */
- return 2455;
+ return 2456;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0101xxxxxxxxxx
sdot. */
- return 2381;
+ return 2382;
}
}
else
10987654321098765432109876543210
0x001110xx0xxxxx1x1011xxxxxxxxxx
usmmla. */
- return 2457;
+ return 2458;
}
}
}
10987654321098765432109876543210
0x001110xx0xxxxx1x0111xxxxxxxxxx
usdot. */
- return 2458;
+ return 2459;
}
}
else
10987654321098765432109876543210
1x001110000xxxxxxxxxxxxxxxxxxxxx
eor3. */
- return 2388;
+ return 2389;
}
else
{
10987654321098765432109876543210
1x001110100xxxxxxxxxxxxxxxxxxxxx
xar. */
- return 2390;
+ return 2391;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx0xxxxxxxxxxxxxxx
sm3ss1. */
- return 2392;
+ return 2393;
}
else
{
10987654321098765432109876543210
1x001110010xxxxx1xxx00xxxxxxxxxx
sm3tt1a. */
- return 2393;
+ return 2394;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx00xxxxxxxxxx
sha512su0. */
- return 2386;
+ return 2387;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx10xxxxxxxxxx
sm3tt2a. */
- return 2395;
+ return 2396;
}
}
else
10987654321098765432109876543210
1x001110010xxxxx1xxx01xxxxxxxxxx
sm3tt1b. */
- return 2394;
+ return 2395;
}
else
{
10987654321098765432109876543210
1x001110110xxxxx1xxx01xxxxxxxxxx
sm4e. */
- return 2399;
+ return 2400;
}
}
else
10987654321098765432109876543210
1x001110x10xxxxx1xxx11xxxxxxxxxx
sm3tt2b. */
- return 2396;
+ return 2397;
}
}
}
10987654321098765432109876543210
xx101110xx0xxxxx100101xxxxxxxxxx
udot. */
- return 2380;
+ return 2381;
}
}
else
10987654321098765432109876543210
xx101110xx0xxxxx101x01xxxxxxxxxx
ummla. */
- return 2456;
+ return 2457;
}
else
{
10987654321098765432109876543210
xx101110xx0xxxxx1x1011xxxxxxxxxx
bfmmla. */
- return 2472;
+ return 2473;
}
else
{
10987654321098765432109876543210
xx1011100x0xxxxx1x1111xxxxxxxxxx
bfdot. */
- return 2470;
+ return 2471;
}
else
{
10987654321098765432109876543210
x01011101x0xxxxx1x1111xxxxxxxxxx
bfmlalb. */
- return 2477;
+ return 2478;
}
else
{
10987654321098765432109876543210
x11011101x0xxxxx1x1111xxxxxxxxxx
bfmlalt. */
- return 2476;
+ return 2477;
}
}
}
10987654321098765432109876543210
000011101x1xxxx1011010xxxxxxxxxx
bfcvtn. */
- return 2473;
+ return 2474;
}
else
{
10987654321098765432109876543210
010011101x1xxxx1011010xxxxxxxxxx
bfcvtn2. */
- return 2474;
+ return 2475;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx0xxxxxxxxxxxxxxx
bcax. */
- return 2391;
+ return 2392;
}
}
else
10987654321098765432109876543210
11001110xx1xxxxx100000xxxxxxxxxx
sha512h. */
- return 2384;
+ return 2385;
}
}
}
10987654321098765432109876543210
11001110xx1xxxxx110000xxxxxxxxxx
sm3partw1. */
- return 2397;
+ return 2398;
}
}
}
10987654321098765432109876543210
1x001110xx1xxxxx100010xxxxxxxxxx
sha512su1. */
- return 2387;
+ return 2388;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110010xxxxxxxxxx
sm4ekey. */
- return 2400;
+ return 2401;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100001xxxxxxxxxx
sha512h2. */
- return 2385;
+ return 2386;
}
}
else
10987654321098765432109876543210
1x0011100x1xxxxx110001xxxxxxxxxx
sm3partw2. */
- return 2398;
+ return 2399;
}
}
else
10987654321098765432109876543210
1x001110xx1xxxxx100011xxxxxxxxxx
rax1. */
- return 2389;
+ return 2390;
}
}
else
10987654321098765432109876543210
x01011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2403;
+ return 2404;
}
else
{
10987654321098765432109876543210
x11011100x1xxxxx110011xxxxxxxxxx
fmlal2. */
- return 2407;
+ return 2408;
}
}
}
10987654321098765432109876543210
x01011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2404;
+ return 2405;
}
else
{
10987654321098765432109876543210
x11011101x1xxxxx110011xxxxxxxxxx
fmlsl2. */
- return 2408;
+ return 2409;
}
}
}
10987654321098765432109876543210
x00011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2401;
+ return 2402;
}
else
{
10987654321098765432109876543210
x10011100x1xxxxx111011xxxxxxxxxx
fmlal. */
- return 2405;
+ return 2406;
}
}
else
10987654321098765432109876543210
x00011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2402;
+ return 2403;
}
else
{
10987654321098765432109876543210
x10011101x1xxxxx111011xxxxxxxxxx
fmlsl. */
- return 2406;
+ return 2407;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2409;
+ return 2410;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0000x0xxxxxxxxxx
fmlal. */
- return 2413;
+ return 2414;
}
}
else
10987654321098765432109876543210
x0001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2410;
+ return 2411;
}
else
{
10987654321098765432109876543210
x1001111xxxxxxxx0100x0xxxxxxxxxx
fmlsl. */
- return 2414;
+ return 2415;
}
}
else
10987654321098765432109876543210
x0101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2411;
+ return 2412;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1000x0xxxxxxxxxx
fmlal2. */
- return 2415;
+ return 2416;
}
}
}
10987654321098765432109876543210
x0101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2412;
+ return 2413;
}
else
{
10987654321098765432109876543210
x1101111xxxxxxxx1100x0xxxxxxxxxx
fmlsl2. */
- return 2416;
+ return 2417;
}
}
}
10987654321098765432109876543210
xx001111xxxxxxxx1110x0xxxxxxxxxx
sdot. */
- return 2383;
+ return 2384;
}
else
{
10987654321098765432109876543210
xx101111xxxxxxxx1110x0xxxxxxxxxx
udot. */
- return 2382;
+ return 2383;
}
}
}
10987654321098765432109876543210
xx00111100xxxxxx1111x0xxxxxxxxxx
sudot. */
- return 2460;
+ return 2461;
}
else
{
10987654321098765432109876543210
xx00111110xxxxxx1111x0xxxxxxxxxx
usdot. */
- return 2459;
+ return 2460;
}
}
else
10987654321098765432109876543210
xx00111101xxxxxx1111x0xxxxxxxxxx
bfdot. */
- return 2471;
+ return 2472;
}
else
{
10987654321098765432109876543210
x000111111xxxxxx1111x0xxxxxxxxxx
bfmlalb. */
- return 2479;
+ return 2480;
}
else
{
10987654321098765432109876543210
x100111111xxxxxx1111x0xxxxxxxxxx
bfmlalt. */
- return 2478;
+ return 2479;
}
}
}
case 824: return NULL; /* fsqrt --> NULL. */
case 832: value = 833; break; /* frintz --> frintz. */
case 833: return NULL; /* frintz --> NULL. */
- case 825: value = 2475; break; /* fcvt --> bfcvt. */
- case 2475: return NULL; /* bfcvt --> NULL. */
+ case 825: value = 2476; break; /* fcvt --> bfcvt. */
+ case 2476: return NULL; /* bfcvt --> NULL. */
case 834: value = 835; break; /* frinta --> frinta. */
case 835: return NULL; /* frinta --> NULL. */
case 836: value = 837; break; /* frintx --> frintx. */
case 33:
case 34:
case 35:
- case 215:
+ case 216:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 36:
return aarch64_ext_reglist (self, info, code, inst, errors);
case 188:
case 189:
case 214:
+ case 215:
return aarch64_ext_imm (self, info, code, inst, errors);
case 44:
case 45:
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_src", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_5}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZA_HV_idx_dest", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_size_10,FLD_SME_Q,FLD_SME_V,FLD_SME_Rv,FLD_imm4_2}, "an SME horizontal or vertical vector access register"},
{AARCH64_OPND_CLASS_PRED_REG, "SME_Pm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Pm}, "an SVE predicate register"},
+ {AARCH64_OPND_CLASS_SVE_REG, "SME_list_of_64bit_tiles", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_zero_mask}, "list of 64-bit ZA element tiles"},
{AARCH64_OPND_CLASS_IMMEDIATE, "TME_UIMM16", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm16}, "a 16-bit unsigned immediate for TME tcancel"},
{AARCH64_OPND_CLASS_SIMD_ELEMENT, "SM3_IMM2", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SM3_imm2}, "an indexed SM3 vector immediate"},
{AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"},
{ 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
{ 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
{ 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */
+ { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
{ 11, 2 }, /* rotate1: FCMLA immediate rotate. */
{ 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
{ 12, 1 }, /* rotate3: FCADD immediate rotate. */
snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
}
+/* Print ZA tiles from imm8 in ZERO instruction.
+
+ The preferred disassembly of this instruction uses the shortest list of tile
+ names that represent the encoded immediate mask.
+
+ For example:
+ * An all-ones immediate is disassembled as {ZA}.
+ * An all-zeros immediate is disassembled as an empty list { }.
+*/
+static void
+print_sme_za_list(char *buf, size_t size, int mask)
+{
+ const char* zan[] = { "za", "za0.h", "za1.h", "za0.s",
+ "za1.s", "za2.s", "za3.s", "za0.d",
+ "za1.d", "za2.d", "za3.d", "za4.d",
+ "za5.d", "za6.d", "za7.d", " " };
+ const int zan_v[] = { 0xff, 0x55, 0xaa, 0x11,
+ 0x22, 0x44, 0x88, 0x01,
+ 0x02, 0x04, 0x08, 0x10,
+ 0x20, 0x40, 0x80, 0x00 };
+ int i, k;
+ const int ZAN_SIZE = sizeof(zan) / sizeof(zan[0]);
+
+ k = snprintf (buf, size, "{");
+ for (i = 0; i < ZAN_SIZE; i++)
+ {
+ if ((mask & zan_v[i]) == zan_v[i])
+ {
+ mask &= ~zan_v[i];
+ if (k > 1)
+ k += snprintf (buf + k, size - k, ", %s", zan[i]);
+ else
+ k += snprintf (buf + k, size - k, "%s", zan[i]);
+ }
+ if (mask == 0)
+ break;
+ }
+ snprintf (buf + k, size - k, "}");
+}
+
/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
PC, PCREL_P and ADDRESS are used to pass in and return information about
opnd->za_tile_vector.index.imm);
break;
+ case AARCH64_OPND_SME_list_of_64bit_tiles:
+ print_sme_za_list (buf, size, opnd->reg.regno);
+ break;
+
case AARCH64_OPND_CRn:
case AARCH64_OPND_CRm:
snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
FLD_SME_V,
FLD_SME_Rv,
FLD_SME_Pm,
+ FLD_SME_zero_mask,
FLD_rotate1,
FLD_rotate2,
FLD_rotate3,
SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_misc, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_misc, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SME_BHSDQ_PM_BHSDQ, 0, 0),
+ SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
+
/* SIMD Dot Product (optional in v8.2-A). */
DOT_INSN ("udot", 0x2e009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
DOT_INSN ("sdot", 0xe009400, 0xbf20fc00, dotproduct, OP3 (Vd, Vn, Vm), QL_V3DOT, F_SIZEQ),
"an SME horizontal or vertical vector access register") \
Y(PRED_REG, regno, "SME_Pm", 0, F(FLD_SME_Pm), \
"an SVE predicate register") \
+ Y(SVE_REG, imm, "SME_list_of_64bit_tiles", 0, \
+ F(FLD_SME_zero_mask), "list of 64-bit ZA element tiles") \
Y(IMMEDIATE, imm, "TME_UIMM16", 0, F(FLD_imm16), \
"a 16-bit unsigned immediate for TME tcancel") \
Y(SIMD_ELEMENT, reglane, "SM3_IMM2", 0, F(FLD_SM3_imm2), \
projects / thirdparty / binutils-gdb.git / commitdiff
