sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slots

Parallel insns can only do one 32bit, then two 16bits.  So if we see
a 2nd 32bit insn after the first 32bit in a parallel insn, abort.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>

diff --git a/sim/bfin/ChangeLog b/sim/bfin/ChangeLog
index 899d0ca776fe1c18491a278503c17ef067c101dc..f4422247f940fa2f008af1a8819f7114c6a0170c 100644 (file)
--- a/sim/bfin/ChangeLog
+++ b/sim/bfin/ChangeLog
@@ -1,3 +1,8 @@
+2012-04-01  Mike Frysinger  <vapier@gentoo.org>
+
+       * bfin-sim.c (_interp_insn_bfin): Call illegal_instruction_combination
+       when INSN_LEN is non-zero before 32bit decode.
+
 2012-04-01  Mike Frysinger  <vapier@gentoo.org>
 
        * bfin-dis.c (fmtconst): Replace decimal handling with a single

diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c
index 54d6bcad3462e0d5d7f3425c5d05db8f81c91293..a8c77940ef87c5b9eda60ab4b32029db7c4c1ab4 100644 (file)
--- a/sim/bfin/bfin-sim.c
+++ b/sim/bfin/bfin-sim.c
@@ -6187,6 +6187,9 @@ _interp_insn_bfin (SIM_CPU *cpu, bu32 pc)
   /* Only cache on first run through (in case of parallel insns).  */
   if (INSN_LEN == 0)
     INSN_LEN = insn_len;
+  else
+    /* Once you're past the first slot, only 16bit insns are valid.  */
+    illegal_instruction_combination (cpu);
 
   if ((iw0 & 0xf7ff) == 0xc003 && (iw1 & 0xfe00) == 0x1800)
     {