sunxi: add H3 cpu OPP table

diff --git a/arch/arm/boot/dts/sun8i-h3.dtsi b/arch/arm/boot/dts/sun8i-h3.dtsi
index d99f10cc9a938eaf6a4fe11d29336ad12457ba60..d4a31cdba7a77a59e04c425aea1b52833dbb6de5 100644 (file)
--- a/arch/arm/boot/dts/sun8i-h3.dtsi
+++ b/arch/arm/boot/dts/sun8i-h3.dtsi
@@ -44,6 +44,71 @@
 #include <dt-bindings/thermal/thermal.h>
 
 / {
+       cpu_opp_table: opp_table {
+               compatible = "operating-points-v2";
+               opp-shared;
+
+               opp@240000000 {
+                       opp-hz = /bits/ 64 <240000000>;
+                       opp-microvolt = <980000 980000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@480000000 {
+                       opp-hz = /bits/ 64 <480000000>;
+                       opp-microvolt = <980000 980000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@648000000 {
+                       opp-hz = /bits/ 64 <648000000>;
+                       opp-microvolt = <1000000 1000000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@816000000 {
+                       opp-hz = /bits/ 64 <816000000>;
+                       opp-microvolt = <1020000 1020000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@912000000 {
+                       opp-hz = /bits/ 64 <912000000>;
+                       opp-microvolt = <1040000 1040000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@960000000 {
+                       opp-hz = /bits/ 64 <960000000>;
+                       opp-microvolt = <1080000 1080000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@1008000000 {
+                       opp-hz = /bits/ 64 <1008000000>;
+                       opp-microvolt = <1140000 1140000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@1104000000 {
+                       opp-hz = /bits/ 64 <1104000000>;
+                       opp-microvolt = <1180000 1180000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@1200000000 {
+                       opp-hz = /bits/ 64 <1200000000>;
+                       opp-microvolt = <1240000 1240000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+
+               opp@1296000000 {
+                       opp-hz = /bits/ 64 <1296000000>;
+                       opp-microvolt = <1320000 1320000 1320000>;
+                       clock-latency-ns = <244144>; /* 8 32k periods */
+               };
+       };
+
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;