+2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
+
+ * testsuite/gas/mips/mips.exp: Run coprocessor tests across all
+ ISAs.
+ * testsuite/gas/mips/cp0b.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp0bl.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp0c.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp0m.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp3.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp3b.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp3bl.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp3m.d: Update for ISA exclusions.
+ * testsuite/gas/mips/cp3d.d: Update for ISA exclusions.
+ * testsuite/gas/mips/mips1@cp0b.d: New test.
+ * testsuite/gas/mips/mips2@cp0b.d: New test.
+ * testsuite/gas/mips/mips3@cp0b.d: New test.
+ * testsuite/gas/mips/r3000@cp0b.d: New test.
+ * testsuite/gas/mips/r3900@cp0b.d: New test.
+ * testsuite/gas/mips/r4000@cp0b.d: New test.
+ * testsuite/gas/mips/r5900@cp0b.d: New test.
+ * testsuite/gas/mips/mips2@cp0bl.d: New test.
+ * testsuite/gas/mips/mips3@cp0bl.d: New test.
+ * testsuite/gas/mips/r3900@cp0bl.d: New test.
+ * testsuite/gas/mips/r4000@cp0bl.d: New test.
+ * testsuite/gas/mips/r5900@cp0bl.d: New test.
+ * testsuite/gas/mips/mips1@cp0c.d: New test.
+ * testsuite/gas/mips/mips2@cp0c.d: New test.
+ * testsuite/gas/mips/mips3@cp0c.d: New test.
+ * testsuite/gas/mips/mips4@cp0c.d: New test.
+ * testsuite/gas/mips/mips5@cp0c.d: New test.
+ * testsuite/gas/mips/r3000@cp0c.d: New test.
+ * testsuite/gas/mips/r3900@cp0c.d: New test.
+ * testsuite/gas/mips/r4000@cp0c.d: New test.
+ * testsuite/gas/mips/vr5400@cp0c.d: New test.
+ * testsuite/gas/mips/r5900@cp0c.d: New test.
+ * testsuite/gas/mips/mips1@cp0m.d: New test.
+ * testsuite/gas/mips/r3000@cp0m.d: New test.
+ * testsuite/gas/mips/octeon@cp2.d: New test.
+ * testsuite/gas/mips/mipsr6@cp2b.d: New test.
+ * testsuite/gas/mips/vr5400@cp2b.d: New test.
+ * testsuite/gas/mips/octeon@cp2b.d: New test.
+ * testsuite/gas/mips/mips1@cp2bl.d: New test.
+ * testsuite/gas/mips/mipsr6@cp2bl.d: New test.
+ * testsuite/gas/mips/r3000@cp2bl.d: New test.
+ * testsuite/gas/mips/vr5400@cp2bl.d: New test.
+ * testsuite/gas/mips/octeon@cp2bl.d: New test.
+ * testsuite/gas/mips/vr5400@cp2m.d: New test.
+ * testsuite/gas/mips/r5900@cp2m.d: New test.
+ * testsuite/gas/mips/octeon@cp2m.d: New test.
+ * testsuite/gas/mips/mips1@cp2d.d: New test.
+ * testsuite/gas/mips/r3000@cp2d.d: New test.
+ * testsuite/gas/mips/r3900@cp2d.d: New test.
+ * testsuite/gas/mips/vr5400@cp2d.d: New test.
+ * testsuite/gas/mips/r5900@cp2d.d: New test.
+ * testsuite/gas/mips/octeon@cp2d.d: New test.
+ * testsuite/gas/mips/mips1@cp2-64.d: New test.
+ * testsuite/gas/mips/mips2@cp2-64.d: New test.
+ * testsuite/gas/mips/mips32@cp2-64.d: New test.
+ * testsuite/gas/mips/mips32r2@cp2-64.d: New test.
+ * testsuite/gas/mips/mips32r3@cp2-64.d: New test.
+ * testsuite/gas/mips/mips32r5@cp2-64.d: New test.
+ * testsuite/gas/mips/mips32r6@cp2-64.d: New test.
+ * testsuite/gas/mips/r3000@cp2-64.d: New test.
+ * testsuite/gas/mips/r3900@cp2-64.d: New test.
+ * testsuite/gas/mips/interaptiv-mr2@cp2-64.d: New test.
+ * testsuite/gas/mips/mips1@cp3.d: New test.
+ * testsuite/gas/mips/mips2@cp3.d: New test.
+ * testsuite/gas/mips/mips32@cp3.d: New test.
+ * testsuite/gas/mips/r3000@cp3.d: New test.
+ * testsuite/gas/mips/r3900@cp3.d: New test.
+ * testsuite/gas/mips/mips1@cp3b.d: New test.
+ * testsuite/gas/mips/mips2@cp3b.d: New test.
+ * testsuite/gas/mips/mips32@cp3b.d: New test.
+ * testsuite/gas/mips/r3000@cp3b.d: New test.
+ * testsuite/gas/mips/r3900@cp3b.d: New test.
+ * testsuite/gas/mips/mips2@cp3bl.d: New test.
+ * testsuite/gas/mips/mips32@cp3bl.d: New test.
+ * testsuite/gas/mips/r3900@cp3bl.d: New test.
+ * testsuite/gas/mips/mips1@cp3m.d: New test.
+ * testsuite/gas/mips/mips2@cp3m.d: New test.
+ * testsuite/gas/mips/r3000@cp3m.d: New test.
+ * testsuite/gas/mips/r3900@cp3m.d: New test.
+ * testsuite/gas/mips/mips2@cp3d.d: New test.
+ * testsuite/gas/mips/cp0b.l: New test stderr output.
+ * testsuite/gas/mips/cp0bl.l: New test stderr output.
+ * testsuite/gas/mips/cp0c.l: New test stderr output.
+ * testsuite/gas/mips/cp0m.l: New test stderr output.
+ * testsuite/gas/mips/cp2.l: New test stderr output.
+ * testsuite/gas/mips/cp2-64.l: New test stderr output.
+ * testsuite/gas/mips/cp2b.l: New test stderr output.
+ * testsuite/gas/mips/cp2bl.l: New test stderr output.
+ * testsuite/gas/mips/cp2m.l: New test stderr output.
+ * testsuite/gas/mips/cp2d.l: New test stderr output.
+ * testsuite/gas/mips/cp3.l: New test stderr output.
+ * testsuite/gas/mips/cp3b.l: New test stderr output.
+ * testsuite/gas/mips/cp3bl.l: New test stderr output.
+ * testsuite/gas/mips/cp3m.l: New test stderr output.
+ * testsuite/gas/mips/cp3d.l: New test stderr output.
+
2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
* testsuite/gas/mips/mips32@isa-override-1.d: Update for LDC3
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP0 branch instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 41000001 bc0f [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
-[0-9a-f]+ <[^>]*> 41010001 bc0t [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
- \.\.\.
+#error_output: cp0b.l
+#source: cp0b.s
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc0f 0f'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc0t 0f'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP0 branch likely instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 41020001 bc0fl [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
-[0-9a-f]+ <[^>]*> 41030001 bc0tl [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
- \.\.\.
+#error_output: cp0bl.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc0fl 0f'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc0tl 0f'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP0 control register move instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 40c00000 ctc0 zero,\$0
-[0-9a-f]+ <[^>]*> 40c00800 ctc0 zero,\$1
-[0-9a-f]+ <[^>]*> 40c01000 ctc0 zero,\$2
-[0-9a-f]+ <[^>]*> 40c01800 ctc0 zero,\$3
-[0-9a-f]+ <[^>]*> 40c02000 ctc0 zero,\$4
-[0-9a-f]+ <[^>]*> 40c02800 ctc0 zero,\$5
-[0-9a-f]+ <[^>]*> 40c03000 ctc0 zero,\$6
-[0-9a-f]+ <[^>]*> 40c03800 ctc0 zero,\$7
-[0-9a-f]+ <[^>]*> 40c04000 ctc0 zero,\$8
-[0-9a-f]+ <[^>]*> 40c04800 ctc0 zero,\$9
-[0-9a-f]+ <[^>]*> 40c05000 ctc0 zero,\$10
-[0-9a-f]+ <[^>]*> 40c05800 ctc0 zero,\$11
-[0-9a-f]+ <[^>]*> 40c06000 ctc0 zero,\$12
-[0-9a-f]+ <[^>]*> 40c06800 ctc0 zero,\$13
-[0-9a-f]+ <[^>]*> 40c07000 ctc0 zero,\$14
-[0-9a-f]+ <[^>]*> 40c07800 ctc0 zero,\$15
-[0-9a-f]+ <[^>]*> 40c08000 ctc0 zero,\$16
-[0-9a-f]+ <[^>]*> 40c08800 ctc0 zero,\$17
-[0-9a-f]+ <[^>]*> 40c09000 ctc0 zero,\$18
-[0-9a-f]+ <[^>]*> 40c09800 ctc0 zero,\$19
-[0-9a-f]+ <[^>]*> 40c0a000 ctc0 zero,\$20
-[0-9a-f]+ <[^>]*> 40c0a800 ctc0 zero,\$21
-[0-9a-f]+ <[^>]*> 40c0b000 ctc0 zero,\$22
-[0-9a-f]+ <[^>]*> 40c0b800 ctc0 zero,\$23
-[0-9a-f]+ <[^>]*> 40c0c000 ctc0 zero,\$24
-[0-9a-f]+ <[^>]*> 40c0c800 ctc0 zero,\$25
-[0-9a-f]+ <[^>]*> 40c0d000 ctc0 zero,\$26
-[0-9a-f]+ <[^>]*> 40c0d800 ctc0 zero,\$27
-[0-9a-f]+ <[^>]*> 40c0e000 ctc0 zero,\$28
-[0-9a-f]+ <[^>]*> 40c0e800 ctc0 zero,\$29
-[0-9a-f]+ <[^>]*> 40c0f000 ctc0 zero,\$30
-[0-9a-f]+ <[^>]*> 40c0f800 ctc0 zero,\$31
-[0-9a-f]+ <[^>]*> 40400000 cfc0 zero,\$0
-[0-9a-f]+ <[^>]*> 40400800 cfc0 zero,\$1
-[0-9a-f]+ <[^>]*> 40401000 cfc0 zero,\$2
-[0-9a-f]+ <[^>]*> 40401800 cfc0 zero,\$3
-[0-9a-f]+ <[^>]*> 40402000 cfc0 zero,\$4
-[0-9a-f]+ <[^>]*> 40402800 cfc0 zero,\$5
-[0-9a-f]+ <[^>]*> 40403000 cfc0 zero,\$6
-[0-9a-f]+ <[^>]*> 40403800 cfc0 zero,\$7
-[0-9a-f]+ <[^>]*> 40404000 cfc0 zero,\$8
-[0-9a-f]+ <[^>]*> 40404800 cfc0 zero,\$9
-[0-9a-f]+ <[^>]*> 40405000 cfc0 zero,\$10
-[0-9a-f]+ <[^>]*> 40405800 cfc0 zero,\$11
-[0-9a-f]+ <[^>]*> 40406000 cfc0 zero,\$12
-[0-9a-f]+ <[^>]*> 40406800 cfc0 zero,\$13
-[0-9a-f]+ <[^>]*> 40407000 cfc0 zero,\$14
-[0-9a-f]+ <[^>]*> 40407800 cfc0 zero,\$15
-[0-9a-f]+ <[^>]*> 40408000 cfc0 zero,\$16
-[0-9a-f]+ <[^>]*> 40408800 cfc0 zero,\$17
-[0-9a-f]+ <[^>]*> 40409000 cfc0 zero,\$18
-[0-9a-f]+ <[^>]*> 40409800 cfc0 zero,\$19
-[0-9a-f]+ <[^>]*> 4040a000 cfc0 zero,\$20
-[0-9a-f]+ <[^>]*> 4040a800 cfc0 zero,\$21
-[0-9a-f]+ <[^>]*> 4040b000 cfc0 zero,\$22
-[0-9a-f]+ <[^>]*> 4040b800 cfc0 zero,\$23
-[0-9a-f]+ <[^>]*> 4040c000 cfc0 zero,\$24
-[0-9a-f]+ <[^>]*> 4040c800 cfc0 zero,\$25
-[0-9a-f]+ <[^>]*> 4040d000 cfc0 zero,\$26
-[0-9a-f]+ <[^>]*> 4040d800 cfc0 zero,\$27
-[0-9a-f]+ <[^>]*> 4040e000 cfc0 zero,\$28
-[0-9a-f]+ <[^>]*> 4040e800 cfc0 zero,\$29
-[0-9a-f]+ <[^>]*> 4040f000 cfc0 zero,\$30
-[0-9a-f]+ <[^>]*> 4040f800 cfc0 zero,\$31
- \.\.\.
+#error_output: cp0c.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$0'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$1'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$2'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$4'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$5'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$6'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$7'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$8'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$9'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$10'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$11'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$12'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$13'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$14'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$15'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$16'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$17'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$18'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$19'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$20'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$21'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$22'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$23'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$24'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$25'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$26'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$27'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$28'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$29'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$30'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `ctc0 \$0,\$31'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$0'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$1'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$2'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$3'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$4'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$5'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$6'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$7'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$8'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$9'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$10'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$11'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$12'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$13'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$14'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$15'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$16'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$17'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$18'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$19'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$20'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$21'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$22'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$23'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$24'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$25'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$26'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$27'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$28'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$29'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$30'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `cfc0 \$0,\$31'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP0 memory access instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> c0000000 lwc0 c0_index,0\(zero\)
-[0-9a-f]+ <[^>]*> c0010000 lwc0 c0_random,0\(zero\)
-[0-9a-f]+ <[^>]*> c0020000 lwc0 c0_entrylo,0\(zero\)
-[0-9a-f]+ <[^>]*> c0030000 lwc0 \$3,0\(zero\)
-[0-9a-f]+ <[^>]*> c0040000 lwc0 c0_context,0\(zero\)
-[0-9a-f]+ <[^>]*> c0050000 lwc0 \$5,0\(zero\)
-[0-9a-f]+ <[^>]*> c0060000 lwc0 \$6,0\(zero\)
-[0-9a-f]+ <[^>]*> c0070000 lwc0 \$7,0\(zero\)
-[0-9a-f]+ <[^>]*> c0080000 lwc0 c0_badvaddr,0\(zero\)
-[0-9a-f]+ <[^>]*> c0090000 lwc0 \$9,0\(zero\)
-[0-9a-f]+ <[^>]*> c00a0000 lwc0 c0_entryhi,0\(zero\)
-[0-9a-f]+ <[^>]*> c00b0000 lwc0 \$11,0\(zero\)
-[0-9a-f]+ <[^>]*> c00c0000 lwc0 c0_sr,0\(zero\)
-[0-9a-f]+ <[^>]*> c00d0000 lwc0 c0_cause,0\(zero\)
-[0-9a-f]+ <[^>]*> c00e0000 lwc0 c0_epc,0\(zero\)
-[0-9a-f]+ <[^>]*> c00f0000 lwc0 c0_prid,0\(zero\)
-[0-9a-f]+ <[^>]*> c0100000 lwc0 \$16,0\(zero\)
-[0-9a-f]+ <[^>]*> c0110000 lwc0 \$17,0\(zero\)
-[0-9a-f]+ <[^>]*> c0120000 lwc0 \$18,0\(zero\)
-[0-9a-f]+ <[^>]*> c0130000 lwc0 \$19,0\(zero\)
-[0-9a-f]+ <[^>]*> c0140000 lwc0 \$20,0\(zero\)
-[0-9a-f]+ <[^>]*> c0150000 lwc0 \$21,0\(zero\)
-[0-9a-f]+ <[^>]*> c0160000 lwc0 \$22,0\(zero\)
-[0-9a-f]+ <[^>]*> c0170000 lwc0 \$23,0\(zero\)
-[0-9a-f]+ <[^>]*> c0180000 lwc0 \$24,0\(zero\)
-[0-9a-f]+ <[^>]*> c0190000 lwc0 \$25,0\(zero\)
-[0-9a-f]+ <[^>]*> c01a0000 lwc0 \$26,0\(zero\)
-[0-9a-f]+ <[^>]*> c01b0000 lwc0 \$27,0\(zero\)
-[0-9a-f]+ <[^>]*> c01c0000 lwc0 \$28,0\(zero\)
-[0-9a-f]+ <[^>]*> c01d0000 lwc0 \$29,0\(zero\)
-[0-9a-f]+ <[^>]*> c01e0000 lwc0 \$30,0\(zero\)
-[0-9a-f]+ <[^>]*> c01f0000 lwc0 \$31,0\(zero\)
-[0-9a-f]+ <[^>]*> e0000000 swc0 c0_index,0\(zero\)
-[0-9a-f]+ <[^>]*> e0010000 swc0 c0_random,0\(zero\)
-[0-9a-f]+ <[^>]*> e0020000 swc0 c0_entrylo,0\(zero\)
-[0-9a-f]+ <[^>]*> e0030000 swc0 \$3,0\(zero\)
-[0-9a-f]+ <[^>]*> e0040000 swc0 c0_context,0\(zero\)
-[0-9a-f]+ <[^>]*> e0050000 swc0 \$5,0\(zero\)
-[0-9a-f]+ <[^>]*> e0060000 swc0 \$6,0\(zero\)
-[0-9a-f]+ <[^>]*> e0070000 swc0 \$7,0\(zero\)
-[0-9a-f]+ <[^>]*> e0080000 swc0 c0_badvaddr,0\(zero\)
-[0-9a-f]+ <[^>]*> e0090000 swc0 \$9,0\(zero\)
-[0-9a-f]+ <[^>]*> e00a0000 swc0 c0_entryhi,0\(zero\)
-[0-9a-f]+ <[^>]*> e00b0000 swc0 \$11,0\(zero\)
-[0-9a-f]+ <[^>]*> e00c0000 swc0 c0_sr,0\(zero\)
-[0-9a-f]+ <[^>]*> e00d0000 swc0 c0_cause,0\(zero\)
-[0-9a-f]+ <[^>]*> e00e0000 swc0 c0_epc,0\(zero\)
-[0-9a-f]+ <[^>]*> e00f0000 swc0 c0_prid,0\(zero\)
-[0-9a-f]+ <[^>]*> e0100000 swc0 \$16,0\(zero\)
-[0-9a-f]+ <[^>]*> e0110000 swc0 \$17,0\(zero\)
-[0-9a-f]+ <[^>]*> e0120000 swc0 \$18,0\(zero\)
-[0-9a-f]+ <[^>]*> e0130000 swc0 \$19,0\(zero\)
-[0-9a-f]+ <[^>]*> e0140000 swc0 \$20,0\(zero\)
-[0-9a-f]+ <[^>]*> e0150000 swc0 \$21,0\(zero\)
-[0-9a-f]+ <[^>]*> e0160000 swc0 \$22,0\(zero\)
-[0-9a-f]+ <[^>]*> e0170000 swc0 \$23,0\(zero\)
-[0-9a-f]+ <[^>]*> e0180000 swc0 \$24,0\(zero\)
-[0-9a-f]+ <[^>]*> e0190000 swc0 \$25,0\(zero\)
-[0-9a-f]+ <[^>]*> e01a0000 swc0 \$26,0\(zero\)
-[0-9a-f]+ <[^>]*> e01b0000 swc0 \$27,0\(zero\)
-[0-9a-f]+ <[^>]*> e01c0000 swc0 \$28,0\(zero\)
-[0-9a-f]+ <[^>]*> e01d0000 swc0 \$29,0\(zero\)
-[0-9a-f]+ <[^>]*> e01e0000 swc0 \$30,0\(zero\)
-[0-9a-f]+ <[^>]*> e01f0000 swc0 \$31,0\(zero\)
- \.\.\.
+#error_output: cp0m.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$0,0\(\$0\)'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$1,0\(\$0\)'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$2,0\(\$0\)'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$3,0\(\$0\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$4,0\(\$0\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$5,0\(\$0\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$6,0\(\$0\)'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$7,0\(\$0\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$8,0\(\$0\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$9,0\(\$0\)'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$10,0\(\$0\)'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$11,0\(\$0\)'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$12,0\(\$0\)'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$13,0\(\$0\)'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$14,0\(\$0\)'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$15,0\(\$0\)'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$16,0\(\$0\)'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$17,0\(\$0\)'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$18,0\(\$0\)'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$19,0\(\$0\)'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$20,0\(\$0\)'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$21,0\(\$0\)'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$22,0\(\$0\)'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$23,0\(\$0\)'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$24,0\(\$0\)'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$25,0\(\$0\)'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$26,0\(\$0\)'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$27,0\(\$0\)'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$28,0\(\$0\)'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$29,0\(\$0\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$30,0\(\$0\)'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `lwc0 \$31,0\(\$0\)'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$0,0\(\$0\)'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$1,0\(\$0\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$2,0\(\$0\)'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$3,0\(\$0\)'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$4,0\(\$0\)'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$5,0\(\$0\)'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$6,0\(\$0\)'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$7,0\(\$0\)'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$8,0\(\$0\)'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$9,0\(\$0\)'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$10,0\(\$0\)'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$11,0\(\$0\)'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$12,0\(\$0\)'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$13,0\(\$0\)'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$14,0\(\$0\)'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$15,0\(\$0\)'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$16,0\(\$0\)'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$17,0\(\$0\)'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$18,0\(\$0\)'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$19,0\(\$0\)'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$20,0\(\$0\)'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$21,0\(\$0\)'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$22,0\(\$0\)'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$23,0\(\$0\)'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$24,0\(\$0\)'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$25,0\(\$0\)'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$26,0\(\$0\)'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$27,0\(\$0\)'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$28,0\(\$0\)'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$29,0\(\$0\)'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$30,0\(\$0\)'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `swc0 \$31,0\(\$0\)'
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$0'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$1'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$2'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$4'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$5'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$6'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$7'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$8'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$9'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$10'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$11'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$12'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$13'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$14'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$15'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$16'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$17'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$18'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$19'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$20'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$21'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$22'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$23'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$24'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$25'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$26'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$27'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$28'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$29'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$30'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `dmtc2 \$0,\$31'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$0'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$1'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$2'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$3'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$4'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$5'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$6'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$7'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$8'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$9'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$10'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$11'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$12'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$13'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$14'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$15'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$16'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$17'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$18'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$19'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$20'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$21'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$22'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$23'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$24'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$25'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$26'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$27'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$28'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$29'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$30'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `dmfc2 \$0,\$31'
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$0'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$1'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$2'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$4'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$5'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$6'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$7'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$8'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$9'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$10'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$11'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$12'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$13'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$14'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$15'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$16'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$17'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$18'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$19'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$20'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$21'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$22'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$23'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$24'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$25'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$26'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$27'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$28'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$29'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$30'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `mtc2 \$0,\$31'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$0'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$1'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$2'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$3'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$4'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$5'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$6'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$7'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$8'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$9'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$10'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$11'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$12'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$13'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$14'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$15'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$16'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$17'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$18'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$19'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$20'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$21'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$22'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$23'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$24'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$25'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$26'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$27'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$28'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$29'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$30'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `mfc2 \$0,\$31'
+.*:70: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$0'
+.*:71: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$1'
+.*:72: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$2'
+.*:73: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$3'
+.*:74: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$4'
+.*:75: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$5'
+.*:76: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$6'
+.*:77: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$7'
+.*:78: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$8'
+.*:79: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$9'
+.*:80: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$10'
+.*:81: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$11'
+.*:82: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$12'
+.*:83: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$13'
+.*:84: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$14'
+.*:85: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$15'
+.*:86: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$16'
+.*:87: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$17'
+.*:88: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$18'
+.*:89: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$19'
+.*:90: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$20'
+.*:91: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$21'
+.*:92: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$22'
+.*:93: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$23'
+.*:94: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$24'
+.*:95: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$25'
+.*:96: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$26'
+.*:97: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$27'
+.*:98: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$28'
+.*:99: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$29'
+.*:100: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$30'
+.*:101: Error: opcode not supported on this processor: .* \(.*\) `ctc2 \$0,\$31'
+.*:103: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$0'
+.*:104: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$1'
+.*:105: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$2'
+.*:106: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$3'
+.*:107: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$4'
+.*:108: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$5'
+.*:109: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$6'
+.*:110: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$7'
+.*:111: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$8'
+.*:112: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$9'
+.*:113: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$10'
+.*:114: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$11'
+.*:115: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$12'
+.*:116: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$13'
+.*:117: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$14'
+.*:118: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$15'
+.*:119: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$16'
+.*:120: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$17'
+.*:121: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$18'
+.*:122: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$19'
+.*:123: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$20'
+.*:124: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$21'
+.*:125: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$22'
+.*:126: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$23'
+.*:127: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$24'
+.*:128: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$25'
+.*:129: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$26'
+.*:130: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$27'
+.*:131: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$28'
+.*:132: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$29'
+.*:133: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$30'
+.*:134: Error: opcode not supported on this processor: .* \(.*\) `cfc2 \$0,\$31'
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc2f 0f'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc2t 0f'
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc2fl 0f'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc2tl 0f'
--- /dev/null
+.*: Assembler messages:
+.*:3: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$0,0\(\$0\)'
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$1,0\(\$0\)'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$2,0\(\$0\)'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$3,0\(\$0\)'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$4,0\(\$0\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$5,0\(\$0\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$6,0\(\$0\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$7,0\(\$0\)'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$8,0\(\$0\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$9,0\(\$0\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$10,0\(\$0\)'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$11,0\(\$0\)'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$12,0\(\$0\)'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$13,0\(\$0\)'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$14,0\(\$0\)'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$15,0\(\$0\)'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$16,0\(\$0\)'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$17,0\(\$0\)'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$18,0\(\$0\)'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$19,0\(\$0\)'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$20,0\(\$0\)'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$21,0\(\$0\)'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$22,0\(\$0\)'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$23,0\(\$0\)'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$24,0\(\$0\)'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$25,0\(\$0\)'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$26,0\(\$0\)'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$27,0\(\$0\)'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$28,0\(\$0\)'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$29,0\(\$0\)'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$30,0\(\$0\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `ldc2 \$31,0\(\$0\)'
+.*:36: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$0,0\(\$0\)'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$1,0\(\$0\)'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$2,0\(\$0\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$3,0\(\$0\)'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$4,0\(\$0\)'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$5,0\(\$0\)'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$6,0\(\$0\)'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$7,0\(\$0\)'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$8,0\(\$0\)'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$9,0\(\$0\)'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$10,0\(\$0\)'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$11,0\(\$0\)'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$12,0\(\$0\)'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$13,0\(\$0\)'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$14,0\(\$0\)'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$15,0\(\$0\)'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$16,0\(\$0\)'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$17,0\(\$0\)'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$18,0\(\$0\)'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$19,0\(\$0\)'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$20,0\(\$0\)'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$21,0\(\$0\)'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$22,0\(\$0\)'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$23,0\(\$0\)'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$24,0\(\$0\)'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$25,0\(\$0\)'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$26,0\(\$0\)'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$27,0\(\$0\)'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$28,0\(\$0\)'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$29,0\(\$0\)'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$30,0\(\$0\)'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `sdc2 \$31,0\(\$0\)'
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$0,0\(\$0\)'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$1,0\(\$0\)'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$2,0\(\$0\)'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$3,0\(\$0\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$4,0\(\$0\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$5,0\(\$0\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$6,0\(\$0\)'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$7,0\(\$0\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$8,0\(\$0\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$9,0\(\$0\)'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$10,0\(\$0\)'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$11,0\(\$0\)'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$12,0\(\$0\)'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$13,0\(\$0\)'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$14,0\(\$0\)'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$15,0\(\$0\)'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$16,0\(\$0\)'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$17,0\(\$0\)'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$18,0\(\$0\)'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$19,0\(\$0\)'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$20,0\(\$0\)'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$21,0\(\$0\)'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$22,0\(\$0\)'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$23,0\(\$0\)'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$24,0\(\$0\)'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$25,0\(\$0\)'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$26,0\(\$0\)'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$27,0\(\$0\)'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$28,0\(\$0\)'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$29,0\(\$0\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$30,0\(\$0\)'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `lwc2 \$31,0\(\$0\)'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$0,0\(\$0\)'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$1,0\(\$0\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$2,0\(\$0\)'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$3,0\(\$0\)'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$4,0\(\$0\)'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$5,0\(\$0\)'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$6,0\(\$0\)'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$7,0\(\$0\)'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$8,0\(\$0\)'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$9,0\(\$0\)'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$10,0\(\$0\)'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$11,0\(\$0\)'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$12,0\(\$0\)'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$13,0\(\$0\)'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$14,0\(\$0\)'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$15,0\(\$0\)'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$16,0\(\$0\)'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$17,0\(\$0\)'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$18,0\(\$0\)'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$19,0\(\$0\)'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$20,0\(\$0\)'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$21,0\(\$0\)'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$22,0\(\$0\)'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$23,0\(\$0\)'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$24,0\(\$0\)'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$25,0\(\$0\)'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$26,0\(\$0\)'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$27,0\(\$0\)'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$28,0\(\$0\)'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$29,0\(\$0\)'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$30,0\(\$0\)'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `swc2 \$31,0\(\$0\)'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP3 register move instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 4c800000 mtc3 zero,\$0
-[0-9a-f]+ <[^>]*> 4c800800 mtc3 zero,\$1
-[0-9a-f]+ <[^>]*> 4c801000 mtc3 zero,\$2
-[0-9a-f]+ <[^>]*> 4c801800 mtc3 zero,\$3
-[0-9a-f]+ <[^>]*> 4c802000 mtc3 zero,\$4
-[0-9a-f]+ <[^>]*> 4c802800 mtc3 zero,\$5
-[0-9a-f]+ <[^>]*> 4c803000 mtc3 zero,\$6
-[0-9a-f]+ <[^>]*> 4c803800 mtc3 zero,\$7
-[0-9a-f]+ <[^>]*> 4c804000 mtc3 zero,\$8
-[0-9a-f]+ <[^>]*> 4c804800 mtc3 zero,\$9
-[0-9a-f]+ <[^>]*> 4c805000 mtc3 zero,\$10
-[0-9a-f]+ <[^>]*> 4c805800 mtc3 zero,\$11
-[0-9a-f]+ <[^>]*> 4c806000 mtc3 zero,\$12
-[0-9a-f]+ <[^>]*> 4c806800 mtc3 zero,\$13
-[0-9a-f]+ <[^>]*> 4c807000 mtc3 zero,\$14
-[0-9a-f]+ <[^>]*> 4c807800 mtc3 zero,\$15
-[0-9a-f]+ <[^>]*> 4c808000 mtc3 zero,\$16
-[0-9a-f]+ <[^>]*> 4c808800 mtc3 zero,\$17
-[0-9a-f]+ <[^>]*> 4c809000 mtc3 zero,\$18
-[0-9a-f]+ <[^>]*> 4c809800 mtc3 zero,\$19
-[0-9a-f]+ <[^>]*> 4c80a000 mtc3 zero,\$20
-[0-9a-f]+ <[^>]*> 4c80a800 mtc3 zero,\$21
-[0-9a-f]+ <[^>]*> 4c80b000 mtc3 zero,\$22
-[0-9a-f]+ <[^>]*> 4c80b800 mtc3 zero,\$23
-[0-9a-f]+ <[^>]*> 4c80c000 mtc3 zero,\$24
-[0-9a-f]+ <[^>]*> 4c80c800 mtc3 zero,\$25
-[0-9a-f]+ <[^>]*> 4c80d000 mtc3 zero,\$26
-[0-9a-f]+ <[^>]*> 4c80d800 mtc3 zero,\$27
-[0-9a-f]+ <[^>]*> 4c80e000 mtc3 zero,\$28
-[0-9a-f]+ <[^>]*> 4c80e800 mtc3 zero,\$29
-[0-9a-f]+ <[^>]*> 4c80f000 mtc3 zero,\$30
-[0-9a-f]+ <[^>]*> 4c80f800 mtc3 zero,\$31
-[0-9a-f]+ <[^>]*> 4c000000 mfc3 zero,\$0
-[0-9a-f]+ <[^>]*> 4c000800 mfc3 zero,\$1
-[0-9a-f]+ <[^>]*> 4c001000 mfc3 zero,\$2
-[0-9a-f]+ <[^>]*> 4c001800 mfc3 zero,\$3
-[0-9a-f]+ <[^>]*> 4c002000 mfc3 zero,\$4
-[0-9a-f]+ <[^>]*> 4c002800 mfc3 zero,\$5
-[0-9a-f]+ <[^>]*> 4c003000 mfc3 zero,\$6
-[0-9a-f]+ <[^>]*> 4c003800 mfc3 zero,\$7
-[0-9a-f]+ <[^>]*> 4c004000 mfc3 zero,\$8
-[0-9a-f]+ <[^>]*> 4c004800 mfc3 zero,\$9
-[0-9a-f]+ <[^>]*> 4c005000 mfc3 zero,\$10
-[0-9a-f]+ <[^>]*> 4c005800 mfc3 zero,\$11
-[0-9a-f]+ <[^>]*> 4c006000 mfc3 zero,\$12
-[0-9a-f]+ <[^>]*> 4c006800 mfc3 zero,\$13
-[0-9a-f]+ <[^>]*> 4c007000 mfc3 zero,\$14
-[0-9a-f]+ <[^>]*> 4c007800 mfc3 zero,\$15
-[0-9a-f]+ <[^>]*> 4c008000 mfc3 zero,\$16
-[0-9a-f]+ <[^>]*> 4c008800 mfc3 zero,\$17
-[0-9a-f]+ <[^>]*> 4c009000 mfc3 zero,\$18
-[0-9a-f]+ <[^>]*> 4c009800 mfc3 zero,\$19
-[0-9a-f]+ <[^>]*> 4c00a000 mfc3 zero,\$20
-[0-9a-f]+ <[^>]*> 4c00a800 mfc3 zero,\$21
-[0-9a-f]+ <[^>]*> 4c00b000 mfc3 zero,\$22
-[0-9a-f]+ <[^>]*> 4c00b800 mfc3 zero,\$23
-[0-9a-f]+ <[^>]*> 4c00c000 mfc3 zero,\$24
-[0-9a-f]+ <[^>]*> 4c00c800 mfc3 zero,\$25
-[0-9a-f]+ <[^>]*> 4c00d000 mfc3 zero,\$26
-[0-9a-f]+ <[^>]*> 4c00d800 mfc3 zero,\$27
-[0-9a-f]+ <[^>]*> 4c00e000 mfc3 zero,\$28
-[0-9a-f]+ <[^>]*> 4c00e800 mfc3 zero,\$29
-[0-9a-f]+ <[^>]*> 4c00f000 mfc3 zero,\$30
-[0-9a-f]+ <[^>]*> 4c00f800 mfc3 zero,\$31
-[0-9a-f]+ <[^>]*> 4cc00000 ctc3 zero,\$0
-[0-9a-f]+ <[^>]*> 4cc00800 ctc3 zero,\$1
-[0-9a-f]+ <[^>]*> 4cc01000 ctc3 zero,\$2
-[0-9a-f]+ <[^>]*> 4cc01800 ctc3 zero,\$3
-[0-9a-f]+ <[^>]*> 4cc02000 ctc3 zero,\$4
-[0-9a-f]+ <[^>]*> 4cc02800 ctc3 zero,\$5
-[0-9a-f]+ <[^>]*> 4cc03000 ctc3 zero,\$6
-[0-9a-f]+ <[^>]*> 4cc03800 ctc3 zero,\$7
-[0-9a-f]+ <[^>]*> 4cc04000 ctc3 zero,\$8
-[0-9a-f]+ <[^>]*> 4cc04800 ctc3 zero,\$9
-[0-9a-f]+ <[^>]*> 4cc05000 ctc3 zero,\$10
-[0-9a-f]+ <[^>]*> 4cc05800 ctc3 zero,\$11
-[0-9a-f]+ <[^>]*> 4cc06000 ctc3 zero,\$12
-[0-9a-f]+ <[^>]*> 4cc06800 ctc3 zero,\$13
-[0-9a-f]+ <[^>]*> 4cc07000 ctc3 zero,\$14
-[0-9a-f]+ <[^>]*> 4cc07800 ctc3 zero,\$15
-[0-9a-f]+ <[^>]*> 4cc08000 ctc3 zero,\$16
-[0-9a-f]+ <[^>]*> 4cc08800 ctc3 zero,\$17
-[0-9a-f]+ <[^>]*> 4cc09000 ctc3 zero,\$18
-[0-9a-f]+ <[^>]*> 4cc09800 ctc3 zero,\$19
-[0-9a-f]+ <[^>]*> 4cc0a000 ctc3 zero,\$20
-[0-9a-f]+ <[^>]*> 4cc0a800 ctc3 zero,\$21
-[0-9a-f]+ <[^>]*> 4cc0b000 ctc3 zero,\$22
-[0-9a-f]+ <[^>]*> 4cc0b800 ctc3 zero,\$23
-[0-9a-f]+ <[^>]*> 4cc0c000 ctc3 zero,\$24
-[0-9a-f]+ <[^>]*> 4cc0c800 ctc3 zero,\$25
-[0-9a-f]+ <[^>]*> 4cc0d000 ctc3 zero,\$26
-[0-9a-f]+ <[^>]*> 4cc0d800 ctc3 zero,\$27
-[0-9a-f]+ <[^>]*> 4cc0e000 ctc3 zero,\$28
-[0-9a-f]+ <[^>]*> 4cc0e800 ctc3 zero,\$29
-[0-9a-f]+ <[^>]*> 4cc0f000 ctc3 zero,\$30
-[0-9a-f]+ <[^>]*> 4cc0f800 ctc3 zero,\$31
-[0-9a-f]+ <[^>]*> 4c400000 cfc3 zero,\$0
-[0-9a-f]+ <[^>]*> 4c400800 cfc3 zero,\$1
-[0-9a-f]+ <[^>]*> 4c401000 cfc3 zero,\$2
-[0-9a-f]+ <[^>]*> 4c401800 cfc3 zero,\$3
-[0-9a-f]+ <[^>]*> 4c402000 cfc3 zero,\$4
-[0-9a-f]+ <[^>]*> 4c402800 cfc3 zero,\$5
-[0-9a-f]+ <[^>]*> 4c403000 cfc3 zero,\$6
-[0-9a-f]+ <[^>]*> 4c403800 cfc3 zero,\$7
-[0-9a-f]+ <[^>]*> 4c404000 cfc3 zero,\$8
-[0-9a-f]+ <[^>]*> 4c404800 cfc3 zero,\$9
-[0-9a-f]+ <[^>]*> 4c405000 cfc3 zero,\$10
-[0-9a-f]+ <[^>]*> 4c405800 cfc3 zero,\$11
-[0-9a-f]+ <[^>]*> 4c406000 cfc3 zero,\$12
-[0-9a-f]+ <[^>]*> 4c406800 cfc3 zero,\$13
-[0-9a-f]+ <[^>]*> 4c407000 cfc3 zero,\$14
-[0-9a-f]+ <[^>]*> 4c407800 cfc3 zero,\$15
-[0-9a-f]+ <[^>]*> 4c408000 cfc3 zero,\$16
-[0-9a-f]+ <[^>]*> 4c408800 cfc3 zero,\$17
-[0-9a-f]+ <[^>]*> 4c409000 cfc3 zero,\$18
-[0-9a-f]+ <[^>]*> 4c409800 cfc3 zero,\$19
-[0-9a-f]+ <[^>]*> 4c40a000 cfc3 zero,\$20
-[0-9a-f]+ <[^>]*> 4c40a800 cfc3 zero,\$21
-[0-9a-f]+ <[^>]*> 4c40b000 cfc3 zero,\$22
-[0-9a-f]+ <[^>]*> 4c40b800 cfc3 zero,\$23
-[0-9a-f]+ <[^>]*> 4c40c000 cfc3 zero,\$24
-[0-9a-f]+ <[^>]*> 4c40c800 cfc3 zero,\$25
-[0-9a-f]+ <[^>]*> 4c40d000 cfc3 zero,\$26
-[0-9a-f]+ <[^>]*> 4c40d800 cfc3 zero,\$27
-[0-9a-f]+ <[^>]*> 4c40e000 cfc3 zero,\$28
-[0-9a-f]+ <[^>]*> 4c40e800 cfc3 zero,\$29
-[0-9a-f]+ <[^>]*> 4c40f000 cfc3 zero,\$30
-[0-9a-f]+ <[^>]*> 4c40f800 cfc3 zero,\$31
- \.\.\.
+#error_output: cp3.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$0'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$1'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$2'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$3'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$4'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$5'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$6'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$7'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$8'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$9'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$10'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$11'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$12'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$13'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$14'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$15'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$16'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$17'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$18'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$19'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$20'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$21'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$22'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$23'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$24'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$25'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$26'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$27'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$28'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$29'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$30'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `mtc3 \$0,\$31'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$0'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$1'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$2'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$3'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$4'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$5'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$6'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$7'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$8'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$9'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$10'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$11'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$12'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$13'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$14'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$15'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$16'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$17'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$18'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$19'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$20'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$21'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$22'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$23'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$24'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$25'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$26'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$27'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$28'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$29'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$30'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `mfc3 \$0,\$31'
+.*:70: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$0'
+.*:71: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$1'
+.*:72: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$2'
+.*:73: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$3'
+.*:74: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$4'
+.*:75: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$5'
+.*:76: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$6'
+.*:77: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$7'
+.*:78: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$8'
+.*:79: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$9'
+.*:80: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$10'
+.*:81: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$11'
+.*:82: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$12'
+.*:83: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$13'
+.*:84: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$14'
+.*:85: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$15'
+.*:86: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$16'
+.*:87: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$17'
+.*:88: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$18'
+.*:89: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$19'
+.*:90: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$20'
+.*:91: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$21'
+.*:92: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$22'
+.*:93: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$23'
+.*:94: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$24'
+.*:95: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$25'
+.*:96: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$26'
+.*:97: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$27'
+.*:98: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$28'
+.*:99: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$29'
+.*:100: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$30'
+.*:101: Error: opcode not supported on this processor: .* \(.*\) `ctc3 \$0,\$31'
+.*:103: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$0'
+.*:104: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$1'
+.*:105: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$2'
+.*:106: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$3'
+.*:107: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$4'
+.*:108: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$5'
+.*:109: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$6'
+.*:110: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$7'
+.*:111: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$8'
+.*:112: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$9'
+.*:113: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$10'
+.*:114: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$11'
+.*:115: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$12'
+.*:116: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$13'
+.*:117: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$14'
+.*:118: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$15'
+.*:119: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$16'
+.*:120: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$17'
+.*:121: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$18'
+.*:122: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$19'
+.*:123: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$20'
+.*:124: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$21'
+.*:125: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$22'
+.*:126: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$23'
+.*:127: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$24'
+.*:128: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$25'
+.*:129: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$26'
+.*:130: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$27'
+.*:131: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$28'
+.*:132: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$29'
+.*:133: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$30'
+.*:134: Error: opcode not supported on this processor: .* \(.*\) `cfc3 \$0,\$31'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP3 branch instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 4d000001 bc3f [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
-[0-9a-f]+ <[^>]*> 4d010001 bc3t [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
- \.\.\.
+#error_output: cp3b.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc3f 0f'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc3t 0f'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP3 branch likely instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> 4d020001 bc3fl [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
-[0-9a-f]+ <[^>]*> 4d030001 bc3tl [0-9a-f]+ <[^>]*>
-[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
- \.\.\.
+#error_output: cp3bl.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `bc3fl 0f'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `bc3tl 0f'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP3 doubleword memory access instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> dc000000 ldc3 \$0,0\(zero\)
-[0-9a-f]+ <[^>]*> dc010000 ldc3 \$1,0\(zero\)
-[0-9a-f]+ <[^>]*> dc020000 ldc3 \$2,0\(zero\)
-[0-9a-f]+ <[^>]*> dc030000 ldc3 \$3,0\(zero\)
-[0-9a-f]+ <[^>]*> dc040000 ldc3 \$4,0\(zero\)
-[0-9a-f]+ <[^>]*> dc050000 ldc3 \$5,0\(zero\)
-[0-9a-f]+ <[^>]*> dc060000 ldc3 \$6,0\(zero\)
-[0-9a-f]+ <[^>]*> dc070000 ldc3 \$7,0\(zero\)
-[0-9a-f]+ <[^>]*> dc080000 ldc3 \$8,0\(zero\)
-[0-9a-f]+ <[^>]*> dc090000 ldc3 \$9,0\(zero\)
-[0-9a-f]+ <[^>]*> dc0a0000 ldc3 \$10,0\(zero\)
-[0-9a-f]+ <[^>]*> dc0b0000 ldc3 \$11,0\(zero\)
-[0-9a-f]+ <[^>]*> dc0c0000 ldc3 \$12,0\(zero\)
-[0-9a-f]+ <[^>]*> dc0d0000 ldc3 \$13,0\(zero\)
-[0-9a-f]+ <[^>]*> dc0e0000 ldc3 \$14,0\(zero\)
-[0-9a-f]+ <[^>]*> dc0f0000 ldc3 \$15,0\(zero\)
-[0-9a-f]+ <[^>]*> dc100000 ldc3 \$16,0\(zero\)
-[0-9a-f]+ <[^>]*> dc110000 ldc3 \$17,0\(zero\)
-[0-9a-f]+ <[^>]*> dc120000 ldc3 \$18,0\(zero\)
-[0-9a-f]+ <[^>]*> dc130000 ldc3 \$19,0\(zero\)
-[0-9a-f]+ <[^>]*> dc140000 ldc3 \$20,0\(zero\)
-[0-9a-f]+ <[^>]*> dc150000 ldc3 \$21,0\(zero\)
-[0-9a-f]+ <[^>]*> dc160000 ldc3 \$22,0\(zero\)
-[0-9a-f]+ <[^>]*> dc170000 ldc3 \$23,0\(zero\)
-[0-9a-f]+ <[^>]*> dc180000 ldc3 \$24,0\(zero\)
-[0-9a-f]+ <[^>]*> dc190000 ldc3 \$25,0\(zero\)
-[0-9a-f]+ <[^>]*> dc1a0000 ldc3 \$26,0\(zero\)
-[0-9a-f]+ <[^>]*> dc1b0000 ldc3 \$27,0\(zero\)
-[0-9a-f]+ <[^>]*> dc1c0000 ldc3 \$28,0\(zero\)
-[0-9a-f]+ <[^>]*> dc1d0000 ldc3 \$29,0\(zero\)
-[0-9a-f]+ <[^>]*> dc1e0000 ldc3 \$30,0\(zero\)
-[0-9a-f]+ <[^>]*> dc1f0000 ldc3 \$31,0\(zero\)
-[0-9a-f]+ <[^>]*> fc000000 sdc3 \$0,0\(zero\)
-[0-9a-f]+ <[^>]*> fc010000 sdc3 \$1,0\(zero\)
-[0-9a-f]+ <[^>]*> fc020000 sdc3 \$2,0\(zero\)
-[0-9a-f]+ <[^>]*> fc030000 sdc3 \$3,0\(zero\)
-[0-9a-f]+ <[^>]*> fc040000 sdc3 \$4,0\(zero\)
-[0-9a-f]+ <[^>]*> fc050000 sdc3 \$5,0\(zero\)
-[0-9a-f]+ <[^>]*> fc060000 sdc3 \$6,0\(zero\)
-[0-9a-f]+ <[^>]*> fc070000 sdc3 \$7,0\(zero\)
-[0-9a-f]+ <[^>]*> fc080000 sdc3 \$8,0\(zero\)
-[0-9a-f]+ <[^>]*> fc090000 sdc3 \$9,0\(zero\)
-[0-9a-f]+ <[^>]*> fc0a0000 sdc3 \$10,0\(zero\)
-[0-9a-f]+ <[^>]*> fc0b0000 sdc3 \$11,0\(zero\)
-[0-9a-f]+ <[^>]*> fc0c0000 sdc3 \$12,0\(zero\)
-[0-9a-f]+ <[^>]*> fc0d0000 sdc3 \$13,0\(zero\)
-[0-9a-f]+ <[^>]*> fc0e0000 sdc3 \$14,0\(zero\)
-[0-9a-f]+ <[^>]*> fc0f0000 sdc3 \$15,0\(zero\)
-[0-9a-f]+ <[^>]*> fc100000 sdc3 \$16,0\(zero\)
-[0-9a-f]+ <[^>]*> fc110000 sdc3 \$17,0\(zero\)
-[0-9a-f]+ <[^>]*> fc120000 sdc3 \$18,0\(zero\)
-[0-9a-f]+ <[^>]*> fc130000 sdc3 \$19,0\(zero\)
-[0-9a-f]+ <[^>]*> fc140000 sdc3 \$20,0\(zero\)
-[0-9a-f]+ <[^>]*> fc150000 sdc3 \$21,0\(zero\)
-[0-9a-f]+ <[^>]*> fc160000 sdc3 \$22,0\(zero\)
-[0-9a-f]+ <[^>]*> fc170000 sdc3 \$23,0\(zero\)
-[0-9a-f]+ <[^>]*> fc180000 sdc3 \$24,0\(zero\)
-[0-9a-f]+ <[^>]*> fc190000 sdc3 \$25,0\(zero\)
-[0-9a-f]+ <[^>]*> fc1a0000 sdc3 \$26,0\(zero\)
-[0-9a-f]+ <[^>]*> fc1b0000 sdc3 \$27,0\(zero\)
-[0-9a-f]+ <[^>]*> fc1c0000 sdc3 \$28,0\(zero\)
-[0-9a-f]+ <[^>]*> fc1d0000 sdc3 \$29,0\(zero\)
-[0-9a-f]+ <[^>]*> fc1e0000 sdc3 \$30,0\(zero\)
-[0-9a-f]+ <[^>]*> fc1f0000 sdc3 \$31,0\(zero\)
- \.\.\.
+#error_output: cp3d.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$0,0\(\$0\)'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$1,0\(\$0\)'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$2,0\(\$0\)'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$3,0\(\$0\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$4,0\(\$0\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$5,0\(\$0\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$6,0\(\$0\)'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$7,0\(\$0\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$8,0\(\$0\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$9,0\(\$0\)'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$10,0\(\$0\)'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$11,0\(\$0\)'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$12,0\(\$0\)'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$13,0\(\$0\)'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$14,0\(\$0\)'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$15,0\(\$0\)'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$16,0\(\$0\)'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$17,0\(\$0\)'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$18,0\(\$0\)'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$19,0\(\$0\)'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$20,0\(\$0\)'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$21,0\(\$0\)'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$22,0\(\$0\)'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$23,0\(\$0\)'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$24,0\(\$0\)'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$25,0\(\$0\)'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$26,0\(\$0\)'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$27,0\(\$0\)'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$28,0\(\$0\)'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$29,0\(\$0\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$30,0\(\$0\)'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `ldc3 \$31,0\(\$0\)'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$0,0\(\$0\)'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$1,0\(\$0\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$2,0\(\$0\)'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$3,0\(\$0\)'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$4,0\(\$0\)'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$5,0\(\$0\)'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$6,0\(\$0\)'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$7,0\(\$0\)'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$8,0\(\$0\)'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$9,0\(\$0\)'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$10,0\(\$0\)'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$11,0\(\$0\)'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$12,0\(\$0\)'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$13,0\(\$0\)'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$14,0\(\$0\)'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$15,0\(\$0\)'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$16,0\(\$0\)'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$17,0\(\$0\)'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$18,0\(\$0\)'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$19,0\(\$0\)'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$20,0\(\$0\)'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$21,0\(\$0\)'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$22,0\(\$0\)'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$23,0\(\$0\)'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$24,0\(\$0\)'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$25,0\(\$0\)'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$26,0\(\$0\)'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$27,0\(\$0\)'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$28,0\(\$0\)'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$29,0\(\$0\)'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$30,0\(\$0\)'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `sdc3 \$31,0\(\$0\)'
#objdump: -d --prefix-addresses --show-raw-insn
#name: MIPS CP3 memory access instructions
#as: -32
-
-.*: +file format .*mips.*
-
-Disassembly of section \.text:
-[0-9a-f]+ <[^>]*> cc000000 lwc3 \$0,0\(zero\)
-[0-9a-f]+ <[^>]*> cc010000 lwc3 \$1,0\(zero\)
-[0-9a-f]+ <[^>]*> cc020000 lwc3 \$2,0\(zero\)
-[0-9a-f]+ <[^>]*> cc030000 lwc3 \$3,0\(zero\)
-[0-9a-f]+ <[^>]*> cc040000 lwc3 \$4,0\(zero\)
-[0-9a-f]+ <[^>]*> cc050000 lwc3 \$5,0\(zero\)
-[0-9a-f]+ <[^>]*> cc060000 lwc3 \$6,0\(zero\)
-[0-9a-f]+ <[^>]*> cc070000 lwc3 \$7,0\(zero\)
-[0-9a-f]+ <[^>]*> cc080000 lwc3 \$8,0\(zero\)
-[0-9a-f]+ <[^>]*> cc090000 lwc3 \$9,0\(zero\)
-[0-9a-f]+ <[^>]*> cc0a0000 lwc3 \$10,0\(zero\)
-[0-9a-f]+ <[^>]*> cc0b0000 lwc3 \$11,0\(zero\)
-[0-9a-f]+ <[^>]*> cc0c0000 lwc3 \$12,0\(zero\)
-[0-9a-f]+ <[^>]*> cc0d0000 lwc3 \$13,0\(zero\)
-[0-9a-f]+ <[^>]*> cc0e0000 lwc3 \$14,0\(zero\)
-[0-9a-f]+ <[^>]*> cc0f0000 lwc3 \$15,0\(zero\)
-[0-9a-f]+ <[^>]*> cc100000 lwc3 \$16,0\(zero\)
-[0-9a-f]+ <[^>]*> cc110000 lwc3 \$17,0\(zero\)
-[0-9a-f]+ <[^>]*> cc120000 lwc3 \$18,0\(zero\)
-[0-9a-f]+ <[^>]*> cc130000 lwc3 \$19,0\(zero\)
-[0-9a-f]+ <[^>]*> cc140000 lwc3 \$20,0\(zero\)
-[0-9a-f]+ <[^>]*> cc150000 lwc3 \$21,0\(zero\)
-[0-9a-f]+ <[^>]*> cc160000 lwc3 \$22,0\(zero\)
-[0-9a-f]+ <[^>]*> cc170000 lwc3 \$23,0\(zero\)
-[0-9a-f]+ <[^>]*> cc180000 lwc3 \$24,0\(zero\)
-[0-9a-f]+ <[^>]*> cc190000 lwc3 \$25,0\(zero\)
-[0-9a-f]+ <[^>]*> cc1a0000 lwc3 \$26,0\(zero\)
-[0-9a-f]+ <[^>]*> cc1b0000 lwc3 \$27,0\(zero\)
-[0-9a-f]+ <[^>]*> cc1c0000 lwc3 \$28,0\(zero\)
-[0-9a-f]+ <[^>]*> cc1d0000 lwc3 \$29,0\(zero\)
-[0-9a-f]+ <[^>]*> cc1e0000 lwc3 \$30,0\(zero\)
-[0-9a-f]+ <[^>]*> cc1f0000 lwc3 \$31,0\(zero\)
-[0-9a-f]+ <[^>]*> ec000000 swc3 \$0,0\(zero\)
-[0-9a-f]+ <[^>]*> ec010000 swc3 \$1,0\(zero\)
-[0-9a-f]+ <[^>]*> ec020000 swc3 \$2,0\(zero\)
-[0-9a-f]+ <[^>]*> ec030000 swc3 \$3,0\(zero\)
-[0-9a-f]+ <[^>]*> ec040000 swc3 \$4,0\(zero\)
-[0-9a-f]+ <[^>]*> ec050000 swc3 \$5,0\(zero\)
-[0-9a-f]+ <[^>]*> ec060000 swc3 \$6,0\(zero\)
-[0-9a-f]+ <[^>]*> ec070000 swc3 \$7,0\(zero\)
-[0-9a-f]+ <[^>]*> ec080000 swc3 \$8,0\(zero\)
-[0-9a-f]+ <[^>]*> ec090000 swc3 \$9,0\(zero\)
-[0-9a-f]+ <[^>]*> ec0a0000 swc3 \$10,0\(zero\)
-[0-9a-f]+ <[^>]*> ec0b0000 swc3 \$11,0\(zero\)
-[0-9a-f]+ <[^>]*> ec0c0000 swc3 \$12,0\(zero\)
-[0-9a-f]+ <[^>]*> ec0d0000 swc3 \$13,0\(zero\)
-[0-9a-f]+ <[^>]*> ec0e0000 swc3 \$14,0\(zero\)
-[0-9a-f]+ <[^>]*> ec0f0000 swc3 \$15,0\(zero\)
-[0-9a-f]+ <[^>]*> ec100000 swc3 \$16,0\(zero\)
-[0-9a-f]+ <[^>]*> ec110000 swc3 \$17,0\(zero\)
-[0-9a-f]+ <[^>]*> ec120000 swc3 \$18,0\(zero\)
-[0-9a-f]+ <[^>]*> ec130000 swc3 \$19,0\(zero\)
-[0-9a-f]+ <[^>]*> ec140000 swc3 \$20,0\(zero\)
-[0-9a-f]+ <[^>]*> ec150000 swc3 \$21,0\(zero\)
-[0-9a-f]+ <[^>]*> ec160000 swc3 \$22,0\(zero\)
-[0-9a-f]+ <[^>]*> ec170000 swc3 \$23,0\(zero\)
-[0-9a-f]+ <[^>]*> ec180000 swc3 \$24,0\(zero\)
-[0-9a-f]+ <[^>]*> ec190000 swc3 \$25,0\(zero\)
-[0-9a-f]+ <[^>]*> ec1a0000 swc3 \$26,0\(zero\)
-[0-9a-f]+ <[^>]*> ec1b0000 swc3 \$27,0\(zero\)
-[0-9a-f]+ <[^>]*> ec1c0000 swc3 \$28,0\(zero\)
-[0-9a-f]+ <[^>]*> ec1d0000 swc3 \$29,0\(zero\)
-[0-9a-f]+ <[^>]*> ec1e0000 swc3 \$30,0\(zero\)
-[0-9a-f]+ <[^>]*> ec1f0000 swc3 \$31,0\(zero\)
- \.\.\.
+#error_output: cp3m.l
--- /dev/null
+.*: Assembler messages:
+.*:4: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$0,0\(\$0\)'
+.*:5: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$1,0\(\$0\)'
+.*:6: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$2,0\(\$0\)'
+.*:7: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$3,0\(\$0\)'
+.*:8: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$4,0\(\$0\)'
+.*:9: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$5,0\(\$0\)'
+.*:10: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$6,0\(\$0\)'
+.*:11: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$7,0\(\$0\)'
+.*:12: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$8,0\(\$0\)'
+.*:13: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$9,0\(\$0\)'
+.*:14: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$10,0\(\$0\)'
+.*:15: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$11,0\(\$0\)'
+.*:16: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$12,0\(\$0\)'
+.*:17: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$13,0\(\$0\)'
+.*:18: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$14,0\(\$0\)'
+.*:19: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$15,0\(\$0\)'
+.*:20: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$16,0\(\$0\)'
+.*:21: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$17,0\(\$0\)'
+.*:22: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$18,0\(\$0\)'
+.*:23: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$19,0\(\$0\)'
+.*:24: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$20,0\(\$0\)'
+.*:25: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$21,0\(\$0\)'
+.*:26: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$22,0\(\$0\)'
+.*:27: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$23,0\(\$0\)'
+.*:28: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$24,0\(\$0\)'
+.*:29: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$25,0\(\$0\)'
+.*:30: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$26,0\(\$0\)'
+.*:31: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$27,0\(\$0\)'
+.*:32: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$28,0\(\$0\)'
+.*:33: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$29,0\(\$0\)'
+.*:34: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$30,0\(\$0\)'
+.*:35: Error: opcode not supported on this processor: .* \(.*\) `lwc3 \$31,0\(\$0\)'
+.*:37: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$0,0\(\$0\)'
+.*:38: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$1,0\(\$0\)'
+.*:39: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$2,0\(\$0\)'
+.*:40: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$3,0\(\$0\)'
+.*:41: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$4,0\(\$0\)'
+.*:42: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$5,0\(\$0\)'
+.*:43: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$6,0\(\$0\)'
+.*:44: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$7,0\(\$0\)'
+.*:45: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$8,0\(\$0\)'
+.*:46: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$9,0\(\$0\)'
+.*:47: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$10,0\(\$0\)'
+.*:48: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$11,0\(\$0\)'
+.*:49: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$12,0\(\$0\)'
+.*:50: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$13,0\(\$0\)'
+.*:51: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$14,0\(\$0\)'
+.*:52: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$15,0\(\$0\)'
+.*:53: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$16,0\(\$0\)'
+.*:54: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$17,0\(\$0\)'
+.*:55: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$18,0\(\$0\)'
+.*:56: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$19,0\(\$0\)'
+.*:57: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$20,0\(\$0\)'
+.*:58: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$21,0\(\$0\)'
+.*:59: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$22,0\(\$0\)'
+.*:60: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$23,0\(\$0\)'
+.*:61: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$24,0\(\$0\)'
+.*:62: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$25,0\(\$0\)'
+.*:63: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$26,0\(\$0\)'
+.*:64: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$27,0\(\$0\)'
+.*:65: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$28,0\(\$0\)'
+.*:66: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$29,0\(\$0\)'
+.*:67: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$30,0\(\$0\)'
+.*:68: Error: opcode not supported on this processor: .* \(.*\) `swc3 \$31,0\(\$0\)'
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
run_dump_test "cp0sel-names-sb1"
run_dump_test_arches "cp0c" [mips_arch_list_matching mips1 \
- !mips32 !micromips]
+ !micromips]
run_dump_test_arches "cp0b" [mips_arch_list_matching mips1 \
- !mips4 !mips32 !micromips]
- run_dump_test_arches "cp0bl" [mips_arch_list_matching mips2 \
- !mips4 !mips32 !micromips]
+ !micromips]
+ run_dump_test_arches "cp0bl" [mips_arch_list_matching mips1 \
+ !micromips]
run_dump_test_arches "cp0m" [mips_arch_list_matching mips1 \
- !mips2 !micromips]
+ !micromips]
run_dump_test_arches "rfe" [mips_arch_list_matching mips1 \
!mips3 !mips32 !micromips]
run_dump_test "cp1-names-mips64r2"
run_dump_test "cp1-names-sb1"
+ # The VR5400 and R5900 have their own sets of COP2 instructions, so
+ # exclude them from generic testing. Likewise the Octeon and DMFC2/DMTC2.
run_dump_test_arches "cp2" [mips_arch_list_matching mips1 \
+ !vr5400 !r5900]
+ run_dump_test_arches "cp2-64" [mips_arch_list_matching mips1 \
!vr5400 !r5900 !octeon]
- run_dump_test_arches "cp2-64" [mips_arch_list_matching mips3 \
- !vr5400 !r5900 !octeon]
- run_dump_test_arches "cp2b" [mips_arch_list_matching mips1 \
- !mips32r6 !vr5400 !r5900 !octeon]
- run_dump_test_arches "cp2bl" [mips_arch_list_matching mips2 \
- !mips32r6 !vr5400 !r5900 !octeon]
- run_dump_test_arches "cp2m" [mips_arch_list_matching mips1 \
- !vr5400 !r5900 !octeon]
- run_dump_test_arches "cp2d" [mips_arch_list_matching mips2 \
- !vr5400 !r5900 !octeon]
+ run_dump_test_arches "cp2b" [mips_arch_list_matching mips1]
+ run_dump_test_arches "cp2bl" [mips_arch_list_matching mips1]
+ run_dump_test_arches "cp2m" [mips_arch_list_matching mips1]
+ run_dump_test_arches "cp2d" [mips_arch_list_matching mips1]
run_dump_test_arches "cp3" [mips_arch_list_matching mips1 \
- !mips3 !mips32r2 !micromips]
+ !micromips]
run_dump_test_arches "cp3b" [mips_arch_list_matching mips1 \
- !mips3 !mips32r2 !micromips]
- run_dump_test_arches "cp3bl" [mips_arch_list_matching mips2 \
- !mips3 !mips32r2 !micromips]
+ !micromips]
+ run_dump_test_arches "cp3bl" [mips_arch_list_matching mips1 \
+ !micromips]
run_dump_test_arches "cp3m" [mips_arch_list_matching mips1 \
- !mips3 !mips32 !micromips]
- run_dump_test_arches "cp3d" [mips_arch_list_matching mips2 \
- !mips3 !mips32 !micromips]
+ !micromips]
+ run_dump_test_arches "cp3d" [mips_arch_list_matching mips1 \
+ !micromips]
run_dump_test "hwr-names-numeric"
run_dump_test "hwr-names-mips32r2"
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41000001 bc0f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 41010001 bc0t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 40c00000 ctc0 zero,\$0
+[0-9a-f]+ <[^>]*> 40c00800 ctc0 zero,\$1
+[0-9a-f]+ <[^>]*> 40c01000 ctc0 zero,\$2
+[0-9a-f]+ <[^>]*> 40c01800 ctc0 zero,\$3
+[0-9a-f]+ <[^>]*> 40c02000 ctc0 zero,\$4
+[0-9a-f]+ <[^>]*> 40c02800 ctc0 zero,\$5
+[0-9a-f]+ <[^>]*> 40c03000 ctc0 zero,\$6
+[0-9a-f]+ <[^>]*> 40c03800 ctc0 zero,\$7
+[0-9a-f]+ <[^>]*> 40c04000 ctc0 zero,\$8
+[0-9a-f]+ <[^>]*> 40c04800 ctc0 zero,\$9
+[0-9a-f]+ <[^>]*> 40c05000 ctc0 zero,\$10
+[0-9a-f]+ <[^>]*> 40c05800 ctc0 zero,\$11
+[0-9a-f]+ <[^>]*> 40c06000 ctc0 zero,\$12
+[0-9a-f]+ <[^>]*> 40c06800 ctc0 zero,\$13
+[0-9a-f]+ <[^>]*> 40c07000 ctc0 zero,\$14
+[0-9a-f]+ <[^>]*> 40c07800 ctc0 zero,\$15
+[0-9a-f]+ <[^>]*> 40c08000 ctc0 zero,\$16
+[0-9a-f]+ <[^>]*> 40c08800 ctc0 zero,\$17
+[0-9a-f]+ <[^>]*> 40c09000 ctc0 zero,\$18
+[0-9a-f]+ <[^>]*> 40c09800 ctc0 zero,\$19
+[0-9a-f]+ <[^>]*> 40c0a000 ctc0 zero,\$20
+[0-9a-f]+ <[^>]*> 40c0a800 ctc0 zero,\$21
+[0-9a-f]+ <[^>]*> 40c0b000 ctc0 zero,\$22
+[0-9a-f]+ <[^>]*> 40c0b800 ctc0 zero,\$23
+[0-9a-f]+ <[^>]*> 40c0c000 ctc0 zero,\$24
+[0-9a-f]+ <[^>]*> 40c0c800 ctc0 zero,\$25
+[0-9a-f]+ <[^>]*> 40c0d000 ctc0 zero,\$26
+[0-9a-f]+ <[^>]*> 40c0d800 ctc0 zero,\$27
+[0-9a-f]+ <[^>]*> 40c0e000 ctc0 zero,\$28
+[0-9a-f]+ <[^>]*> 40c0e800 ctc0 zero,\$29
+[0-9a-f]+ <[^>]*> 40c0f000 ctc0 zero,\$30
+[0-9a-f]+ <[^>]*> 40c0f800 ctc0 zero,\$31
+[0-9a-f]+ <[^>]*> 40400000 cfc0 zero,\$0
+[0-9a-f]+ <[^>]*> 40400800 cfc0 zero,\$1
+[0-9a-f]+ <[^>]*> 40401000 cfc0 zero,\$2
+[0-9a-f]+ <[^>]*> 40401800 cfc0 zero,\$3
+[0-9a-f]+ <[^>]*> 40402000 cfc0 zero,\$4
+[0-9a-f]+ <[^>]*> 40402800 cfc0 zero,\$5
+[0-9a-f]+ <[^>]*> 40403000 cfc0 zero,\$6
+[0-9a-f]+ <[^>]*> 40403800 cfc0 zero,\$7
+[0-9a-f]+ <[^>]*> 40404000 cfc0 zero,\$8
+[0-9a-f]+ <[^>]*> 40404800 cfc0 zero,\$9
+[0-9a-f]+ <[^>]*> 40405000 cfc0 zero,\$10
+[0-9a-f]+ <[^>]*> 40405800 cfc0 zero,\$11
+[0-9a-f]+ <[^>]*> 40406000 cfc0 zero,\$12
+[0-9a-f]+ <[^>]*> 40406800 cfc0 zero,\$13
+[0-9a-f]+ <[^>]*> 40407000 cfc0 zero,\$14
+[0-9a-f]+ <[^>]*> 40407800 cfc0 zero,\$15
+[0-9a-f]+ <[^>]*> 40408000 cfc0 zero,\$16
+[0-9a-f]+ <[^>]*> 40408800 cfc0 zero,\$17
+[0-9a-f]+ <[^>]*> 40409000 cfc0 zero,\$18
+[0-9a-f]+ <[^>]*> 40409800 cfc0 zero,\$19
+[0-9a-f]+ <[^>]*> 4040a000 cfc0 zero,\$20
+[0-9a-f]+ <[^>]*> 4040a800 cfc0 zero,\$21
+[0-9a-f]+ <[^>]*> 4040b000 cfc0 zero,\$22
+[0-9a-f]+ <[^>]*> 4040b800 cfc0 zero,\$23
+[0-9a-f]+ <[^>]*> 4040c000 cfc0 zero,\$24
+[0-9a-f]+ <[^>]*> 4040c800 cfc0 zero,\$25
+[0-9a-f]+ <[^>]*> 4040d000 cfc0 zero,\$26
+[0-9a-f]+ <[^>]*> 4040d800 cfc0 zero,\$27
+[0-9a-f]+ <[^>]*> 4040e000 cfc0 zero,\$28
+[0-9a-f]+ <[^>]*> 4040e800 cfc0 zero,\$29
+[0-9a-f]+ <[^>]*> 4040f000 cfc0 zero,\$30
+[0-9a-f]+ <[^>]*> 4040f800 cfc0 zero,\$31
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 memory access instructions
+#as: -32
+#source: cp0m.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> c0000000 lwc0 c0_index,0\(zero\)
+[0-9a-f]+ <[^>]*> c0010000 lwc0 c0_random,0\(zero\)
+[0-9a-f]+ <[^>]*> c0020000 lwc0 c0_entrylo,0\(zero\)
+[0-9a-f]+ <[^>]*> c0030000 lwc0 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> c0040000 lwc0 c0_context,0\(zero\)
+[0-9a-f]+ <[^>]*> c0050000 lwc0 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> c0060000 lwc0 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> c0070000 lwc0 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> c0080000 lwc0 c0_badvaddr,0\(zero\)
+[0-9a-f]+ <[^>]*> c0090000 lwc0 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> c00a0000 lwc0 c0_entryhi,0\(zero\)
+[0-9a-f]+ <[^>]*> c00b0000 lwc0 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> c00c0000 lwc0 c0_sr,0\(zero\)
+[0-9a-f]+ <[^>]*> c00d0000 lwc0 c0_cause,0\(zero\)
+[0-9a-f]+ <[^>]*> c00e0000 lwc0 c0_epc,0\(zero\)
+[0-9a-f]+ <[^>]*> c00f0000 lwc0 c0_prid,0\(zero\)
+[0-9a-f]+ <[^>]*> c0100000 lwc0 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> c0110000 lwc0 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> c0120000 lwc0 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> c0130000 lwc0 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> c0140000 lwc0 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> c0150000 lwc0 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> c0160000 lwc0 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> c0170000 lwc0 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> c0180000 lwc0 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> c0190000 lwc0 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> c01a0000 lwc0 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> c01b0000 lwc0 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> c01c0000 lwc0 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> c01d0000 lwc0 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> c01e0000 lwc0 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> c01f0000 lwc0 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> e0000000 swc0 c0_index,0\(zero\)
+[0-9a-f]+ <[^>]*> e0010000 swc0 c0_random,0\(zero\)
+[0-9a-f]+ <[^>]*> e0020000 swc0 c0_entrylo,0\(zero\)
+[0-9a-f]+ <[^>]*> e0030000 swc0 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> e0040000 swc0 c0_context,0\(zero\)
+[0-9a-f]+ <[^>]*> e0050000 swc0 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> e0060000 swc0 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> e0070000 swc0 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> e0080000 swc0 c0_badvaddr,0\(zero\)
+[0-9a-f]+ <[^>]*> e0090000 swc0 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> e00a0000 swc0 c0_entryhi,0\(zero\)
+[0-9a-f]+ <[^>]*> e00b0000 swc0 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> e00c0000 swc0 c0_sr,0\(zero\)
+[0-9a-f]+ <[^>]*> e00d0000 swc0 c0_cause,0\(zero\)
+[0-9a-f]+ <[^>]*> e00e0000 swc0 c0_epc,0\(zero\)
+[0-9a-f]+ <[^>]*> e00f0000 swc0 c0_prid,0\(zero\)
+[0-9a-f]+ <[^>]*> e0100000 swc0 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> e0110000 swc0 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> e0120000 swc0 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> e0130000 swc0 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> e0140000 swc0 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> e0150000 swc0 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> e0160000 swc0 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> e0170000 swc0 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> e0180000 swc0 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> e0190000 swc0 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> e01a0000 swc0 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> e01b0000 swc0 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> e01c0000 swc0 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> e01d0000 swc0 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> e01e0000 swc0 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> e01f0000 swc0 \$31,0\(zero\)
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#error_output: cp0bl.l
+#source: cp0bl.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#error_output: cp2d.l
+#source: cp2d.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+#source: cp3.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4c800000 mtc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4c800800 mtc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4c801000 mtc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4c801800 mtc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4c802000 mtc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4c802800 mtc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4c803000 mtc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4c803800 mtc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4c804000 mtc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4c804800 mtc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4c805000 mtc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4c805800 mtc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4c806000 mtc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4c806800 mtc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4c807000 mtc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4c807800 mtc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4c808000 mtc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4c808800 mtc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4c809000 mtc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4c809800 mtc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4c80a000 mtc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4c80a800 mtc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4c80b000 mtc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4c80b800 mtc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4c80c000 mtc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4c80c800 mtc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4c80d000 mtc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4c80d800 mtc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4c80e000 mtc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4c80e800 mtc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4c80f000 mtc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4c80f800 mtc3 zero,\$31
+[0-9a-f]+ <[^>]*> 4c000000 mfc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4c000800 mfc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4c001000 mfc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4c001800 mfc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4c002000 mfc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4c002800 mfc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4c003000 mfc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4c003800 mfc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4c004000 mfc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4c004800 mfc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4c005000 mfc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4c005800 mfc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4c006000 mfc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4c006800 mfc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4c007000 mfc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4c007800 mfc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4c008000 mfc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4c008800 mfc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4c009000 mfc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4c009800 mfc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4c00a000 mfc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4c00a800 mfc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4c00b000 mfc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4c00b800 mfc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4c00c000 mfc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4c00c800 mfc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4c00d000 mfc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4c00d800 mfc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4c00e000 mfc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4c00e800 mfc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4c00f000 mfc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4c00f800 mfc3 zero,\$31
+[0-9a-f]+ <[^>]*> 4cc00000 ctc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4cc00800 ctc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4cc01000 ctc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4cc01800 ctc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4cc02000 ctc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4cc02800 ctc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4cc03000 ctc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4cc03800 ctc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4cc04000 ctc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4cc04800 ctc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4cc05000 ctc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4cc05800 ctc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4cc06000 ctc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4cc06800 ctc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4cc07000 ctc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4cc07800 ctc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4cc08000 ctc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4cc08800 ctc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4cc09000 ctc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4cc09800 ctc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4cc0a000 ctc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4cc0a800 ctc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4cc0b000 ctc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4cc0b800 ctc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4cc0c000 ctc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4cc0c800 ctc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4cc0d000 ctc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4cc0d800 ctc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4cc0e000 ctc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4cc0e800 ctc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4cc0f000 ctc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4cc0f800 ctc3 zero,\$31
+[0-9a-f]+ <[^>]*> 4c400000 cfc3 zero,\$0
+[0-9a-f]+ <[^>]*> 4c400800 cfc3 zero,\$1
+[0-9a-f]+ <[^>]*> 4c401000 cfc3 zero,\$2
+[0-9a-f]+ <[^>]*> 4c401800 cfc3 zero,\$3
+[0-9a-f]+ <[^>]*> 4c402000 cfc3 zero,\$4
+[0-9a-f]+ <[^>]*> 4c402800 cfc3 zero,\$5
+[0-9a-f]+ <[^>]*> 4c403000 cfc3 zero,\$6
+[0-9a-f]+ <[^>]*> 4c403800 cfc3 zero,\$7
+[0-9a-f]+ <[^>]*> 4c404000 cfc3 zero,\$8
+[0-9a-f]+ <[^>]*> 4c404800 cfc3 zero,\$9
+[0-9a-f]+ <[^>]*> 4c405000 cfc3 zero,\$10
+[0-9a-f]+ <[^>]*> 4c405800 cfc3 zero,\$11
+[0-9a-f]+ <[^>]*> 4c406000 cfc3 zero,\$12
+[0-9a-f]+ <[^>]*> 4c406800 cfc3 zero,\$13
+[0-9a-f]+ <[^>]*> 4c407000 cfc3 zero,\$14
+[0-9a-f]+ <[^>]*> 4c407800 cfc3 zero,\$15
+[0-9a-f]+ <[^>]*> 4c408000 cfc3 zero,\$16
+[0-9a-f]+ <[^>]*> 4c408800 cfc3 zero,\$17
+[0-9a-f]+ <[^>]*> 4c409000 cfc3 zero,\$18
+[0-9a-f]+ <[^>]*> 4c409800 cfc3 zero,\$19
+[0-9a-f]+ <[^>]*> 4c40a000 cfc3 zero,\$20
+[0-9a-f]+ <[^>]*> 4c40a800 cfc3 zero,\$21
+[0-9a-f]+ <[^>]*> 4c40b000 cfc3 zero,\$22
+[0-9a-f]+ <[^>]*> 4c40b800 cfc3 zero,\$23
+[0-9a-f]+ <[^>]*> 4c40c000 cfc3 zero,\$24
+[0-9a-f]+ <[^>]*> 4c40c800 cfc3 zero,\$25
+[0-9a-f]+ <[^>]*> 4c40d000 cfc3 zero,\$26
+[0-9a-f]+ <[^>]*> 4c40d800 cfc3 zero,\$27
+[0-9a-f]+ <[^>]*> 4c40e000 cfc3 zero,\$28
+[0-9a-f]+ <[^>]*> 4c40e800 cfc3 zero,\$29
+[0-9a-f]+ <[^>]*> 4c40f000 cfc3 zero,\$30
+[0-9a-f]+ <[^>]*> 4c40f800 cfc3 zero,\$31
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+#source: cp3b.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4d000001 bc3f [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 4d010001 bc3t [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 memory access instructions
+#as: -32
+#source: cp3m.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> cc000000 lwc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> cc010000 lwc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> cc020000 lwc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> cc030000 lwc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> cc040000 lwc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> cc050000 lwc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> cc060000 lwc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> cc070000 lwc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> cc080000 lwc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> cc090000 lwc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0a0000 lwc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0b0000 lwc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0c0000 lwc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0d0000 lwc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0e0000 lwc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> cc0f0000 lwc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> cc100000 lwc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> cc110000 lwc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> cc120000 lwc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> cc130000 lwc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> cc140000 lwc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> cc150000 lwc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> cc160000 lwc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> cc170000 lwc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> cc180000 lwc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> cc190000 lwc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1a0000 lwc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1b0000 lwc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1c0000 lwc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1d0000 lwc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1e0000 lwc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> cc1f0000 lwc3 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> ec000000 swc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> ec010000 swc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> ec020000 swc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> ec030000 swc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> ec040000 swc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> ec050000 swc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> ec060000 swc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> ec070000 swc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> ec080000 swc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> ec090000 swc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0a0000 swc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0b0000 swc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0c0000 swc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0d0000 swc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0e0000 swc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> ec0f0000 swc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> ec100000 swc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> ec110000 swc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> ec120000 swc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> ec130000 swc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> ec140000 swc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> ec150000 swc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> ec160000 swc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> ec170000 swc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> ec180000 swc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> ec190000 swc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1a0000 swc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1b0000 swc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1c0000 swc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1d0000 swc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1e0000 swc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> ec1f0000 swc3 \$31,0\(zero\)
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#dump: mips1@cp0b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+#source: cp0bl.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 41020001 bc0fl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 41030001 bc0tl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+#source: cp3.s
+#dump: mips1@cp3.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+#source: cp3b.s
+#dump: mips1@cp3b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch likely instructions
+#as: -32
+#source: cp3bl.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> 4d020001 bc3fl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+[0-9a-f]+ <[^>]*> 4d030001 bc3tl [0-9a-f]+ <[^>]*>
+[0-9a-f]+ <[^>]*> 02108026 xor s0,s0,s0
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 doubleword memory access instructions
+#as: -32
+#source: cp3d.s
+
+.*: +file format .*mips.*
+
+Disassembly of section \.text:
+[0-9a-f]+ <[^>]*> dc000000 ldc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> dc010000 ldc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> dc020000 ldc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> dc030000 ldc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> dc040000 ldc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> dc050000 ldc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> dc060000 ldc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> dc070000 ldc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> dc080000 ldc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> dc090000 ldc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0a0000 ldc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0b0000 ldc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0c0000 ldc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0d0000 ldc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0e0000 ldc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> dc0f0000 ldc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> dc100000 ldc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> dc110000 ldc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> dc120000 ldc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> dc130000 ldc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> dc140000 ldc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> dc150000 ldc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> dc160000 ldc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> dc170000 ldc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> dc180000 ldc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> dc190000 ldc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1a0000 ldc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1b0000 ldc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1c0000 ldc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1d0000 ldc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1e0000 ldc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> dc1f0000 ldc3 \$31,0\(zero\)
+[0-9a-f]+ <[^>]*> fc000000 sdc3 \$0,0\(zero\)
+[0-9a-f]+ <[^>]*> fc010000 sdc3 \$1,0\(zero\)
+[0-9a-f]+ <[^>]*> fc020000 sdc3 \$2,0\(zero\)
+[0-9a-f]+ <[^>]*> fc030000 sdc3 \$3,0\(zero\)
+[0-9a-f]+ <[^>]*> fc040000 sdc3 \$4,0\(zero\)
+[0-9a-f]+ <[^>]*> fc050000 sdc3 \$5,0\(zero\)
+[0-9a-f]+ <[^>]*> fc060000 sdc3 \$6,0\(zero\)
+[0-9a-f]+ <[^>]*> fc070000 sdc3 \$7,0\(zero\)
+[0-9a-f]+ <[^>]*> fc080000 sdc3 \$8,0\(zero\)
+[0-9a-f]+ <[^>]*> fc090000 sdc3 \$9,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0a0000 sdc3 \$10,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0b0000 sdc3 \$11,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0c0000 sdc3 \$12,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0d0000 sdc3 \$13,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0e0000 sdc3 \$14,0\(zero\)
+[0-9a-f]+ <[^>]*> fc0f0000 sdc3 \$15,0\(zero\)
+[0-9a-f]+ <[^>]*> fc100000 sdc3 \$16,0\(zero\)
+[0-9a-f]+ <[^>]*> fc110000 sdc3 \$17,0\(zero\)
+[0-9a-f]+ <[^>]*> fc120000 sdc3 \$18,0\(zero\)
+[0-9a-f]+ <[^>]*> fc130000 sdc3 \$19,0\(zero\)
+[0-9a-f]+ <[^>]*> fc140000 sdc3 \$20,0\(zero\)
+[0-9a-f]+ <[^>]*> fc150000 sdc3 \$21,0\(zero\)
+[0-9a-f]+ <[^>]*> fc160000 sdc3 \$22,0\(zero\)
+[0-9a-f]+ <[^>]*> fc170000 sdc3 \$23,0\(zero\)
+[0-9a-f]+ <[^>]*> fc180000 sdc3 \$24,0\(zero\)
+[0-9a-f]+ <[^>]*> fc190000 sdc3 \$25,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1a0000 sdc3 \$26,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1b0000 sdc3 \$27,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1c0000 sdc3 \$28,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1d0000 sdc3 \$29,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1e0000 sdc3 \$30,0\(zero\)
+[0-9a-f]+ <[^>]*> fc1f0000 sdc3 \$31,0\(zero\)
+ \.\.\.
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 memory access instructions
+#as: -32
+#source: cp3m.s
+#dump: mips1@cp3m.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+#source: cp3.s
+#dump: mips1@cp3.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+#source: cp3b.s
+#dump: mips1@cp3b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch likely instructions
+#as: -32
+#source: cp3bl.s
+#dump: mips2@cp3bl.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#dump: mips1@cp0b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+#source: cp0bl.s
+#dump: mips2@cp0bl.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32
+#error_output: cp2b.l
+#source: cp2b.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#error_output: cp0bl.l
+#source: cp0bl.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 register move instructions
+#as: -32
+#error_output: cp2.l
+#source: cp2.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32
+#error_output: cp2b.l
+#source: cp2b.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#error_output: cp0bl.l
+#source: cp0bl.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#error_output: cp2d.l
+#source: cp2d.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 memory access instructions
+#as: -32
+#error_output: cp2m.l
+#source: cp2m.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#dump: mips1@cp0b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 memory access instructions
+#as: -32
+#source: cp0m.s
+#dump: mips1@cp0m.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#error_output: cp0bl.l
+#source: cp0bl.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#error_output: cp2d.l
+#source: cp2d.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+#source: cp3.s
+#dump: mips1@cp3.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+#source: cp3b.s
+#dump: mips1@cp3b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 memory access instructions
+#as: -32
+#source: cp3m.s
+#dump: mips1@cp3m.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#dump: mips1@cp0b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+#source: cp0bl.s
+#dump: mips2@cp0bl.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 64-bit move instructions
+#as: -32
+#error_output: cp2-64.l
+#source: cp2-64.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#error_output: cp2d.l
+#source: cp2d.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 register move instructions
+#as: -32
+#source: cp3.s
+#dump: mips1@cp3.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch instructions
+#as: -32
+#source: cp3b.s
+#dump: mips1@cp3b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 branch likely instructions
+#as: -32
+#source: cp3bl.s
+#dump: mips2@cp3bl.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP3 memory access instructions
+#as: -32
+#source: cp3m.s
+#dump: mips1@cp3m.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#dump: mips1@cp0b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+#source: cp0bl.s
+#dump: mips2@cp0bl.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch instructions
+#as: -32
+#source: cp0b.s
+#dump: mips1@cp0b.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 branch likely instructions
+#as: -32
+#source: cp0bl.s
+#dump: mips2@cp0bl.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#error_output: cp2d.l
+#source: cp2d.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 memory access instructions
+#as: -32
+#error_output: cp2m.l
+#source: cp2m.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP0 control register move instructions
+#as: -32
+#source: cp0c.s
+#dump: mips1@cp0c.d
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch instructions
+#as: -32
+#error_output: cp2b.l
+#source: cp2b.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 branch likely instructions
+#as: -32
+#error_output: cp0bl.l
+#source: cp0bl.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 doubleword memory access instructions
+#as: -32
+#error_output: cp2d.l
+#source: cp2d.s
--- /dev/null
+#objdump: -d --prefix-addresses --show-raw-insn
+#name: MIPS CP2 memory access instructions
+#as: -32
+#error_output: cp2m.l
+#source: cp2m.s
projects / thirdparty / binutils-gdb.git / commitdiff
