Allow negated test when watching value within core.
+Tue May 27 14:32:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-watch.c (schedule_watchpoint): Add is_within option so that
+ inequality test is possible.
+ (handle_watchpoint): Re-pass is_within arg.
+ (watch_option_handler): When `!' prefix to pc-watchpoint arg pass
+ 0 to schedule_watchpoint's is_within arg.
+ (sim_watchpoint_init): Re-pass is_within arg.
+
+ * sim-options.c (sim_print_help): Add is_command argument. Don't
+ include -- prefix when called from the command line interpreter.
+
+ * sim-watch.c (schedule_watchpoint): Pass true is_within argument.
+
+ * sim-events.c (sim_events_watch_sim): Add is_within argument,
+ zero indicates that the test should be reversed.
+ (sim_events_watch_core): Ditto.
+ (WATCH_CORE): Compare range against is_within.
+ (WATCH_SIM): Ditto.
+
+Tue May 27 12:48:03 1997 Andrew Cagney <cagney@b2.cygnus.com>
+
+ * sim-events.c (WATCH_CORE): Pass NULL cpu argument to
+ sim_core_read_buffer. Check nr-bytes transfered.
+
+ * sim-core.h (sim_core_common): Define a new struct that contains
+ the common data. to sd and cpu structures.
+ * sim-core.c (sim_core_attach): Update.
+ (sim_core_init): Update. Remember to copy initialized data to each
+ cpu.
+ (sim_core_find_mapping): Ditto.
+
+ * sim-core.c (sim_core_read_buffer): Add cpu argument.
+ (sim_core_write_buffer): Ditto.
+
+ * sim-n-core.h (sim_core_read_unaligned_N): When mis-aligned
+ transfer use xor version of read buffer.
+ (sim_core_write_unaligned_N): Ditto for write.
+
+ * sim-core.c (sim_core_xor_read_buffer): New function implement
+ xor-endian data read breaking transfer up into xor-endian sized
+ blocks.
+ (sim_core_xor_write_buffer): Ditto for write.
+ (reverse_n): Reverse order of arbitrary number of bytes in buffer
+ - needed for xor-endian transfers.
+
Fri May 23 14:24:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-inline.h: Review description.
/* watch sim addr */
void *host_addr;
/* watch core/sim range */
+ int is_within; /* 0/1 */
unsigned ub;
unsigned lb;
unsigned64 ub64;
void *host_addr,
int nr_bytes,
int byte_order,
+ int is_within,
unsigned64 lb,
unsigned64 ub,
sim_event_handler *handler,
new_event->lb64 = lb;
new_event->ub = ub;
new_event->ub64 = ub;
+ new_event->is_within = (is_within != 0);
/* insert */
new_event->next = events->watchpoints;
events->watchpoints = new_event;
sim_core_maps core_map,
int nr_bytes,
int byte_order,
+ int is_within,
unsigned64 lb,
unsigned64 ub,
sim_event_handler *handler,
new_event->lb64 = lb;
new_event->ub = ub;
new_event->ub64 = ub;
+ new_event->is_within = (is_within != 0);
/* insert */
new_event->next = events->watchpoints;
events->watchpoints = new_event;
#define WATCH_CORE(N,OP,EXT) \
{ \
- unsigned_##N word; \
- sim_core_read_buffer (sd, to_do->core_map, &word, to_do->core_addr, sizeof (word)); \
+ unsigned_##N word = 0; \
+ int nr_read = sim_core_read_buffer (sd, NULL, to_do->core_map, &word, to_do->core_addr, sizeof (word)); \
OP (word); \
- return (word >= to_do->lb##EXT && word <= to_do->ub##EXT); \
+ return (nr_read == sizeof (unsigned_##N) \
+ && (to_do->is_within \
+ == (word >= to_do->lb##EXT \
+ && word <= to_do->ub##EXT))); \
}
case watch_core_targ_1: WATCH_CORE (1, T2H,);
case watch_core_targ_2: WATCH_CORE (2, T2H,);
{ \
unsigned_##N word = *(unsigned_##N*)to_do->host_addr; \
OP (word); \
- return (word >= to_do->lb##EXT && word <= to_do->ub##EXT); \
+ return (to_do->is_within \
+ == (word >= to_do->lb##EXT \
+ && word <= to_do->ub##EXT)); \
}
case watch_sim_host_1: WATCH_SIM (1, word = ,);
unsigned_word xaddr)
{
sim_cpu_core *cpu_core = CPU_CORE (cpu);
- sim_core *core = &cpu_core->common;
+ sim_core_common *core = &cpu_core->common;
unsigned_N val;
sim_core_mapping *mapping;
address_word addr;
case NONSTRICT_ALIGNMENT:
{
unsigned_N val;
- if (sim_core_read_buffer (CPU_STATE (cpu), map, &val, addr,
- sizeof(unsigned_N))
+ if (sim_core_xor_read_buffer (CPU_STATE (cpu), cpu, map, &val, addr,
+ sizeof(unsigned_N))
!= sizeof(unsigned_N))
SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map,
sizeof (unsigned_N), addr,
unsigned_N val)
{
sim_cpu_core *cpu_core = CPU_CORE (cpu);
- sim_core *core = &cpu_core->common;
+ sim_core_common *core = &cpu_core->common;
sim_core_mapping *mapping;
address_word addr;
if (WITH_XOR_ENDIAN)
break;
case NONSTRICT_ALIGNMENT:
{
- val = T2H_N(val);
- if (sim_core_write_buffer (CPU_STATE (cpu), map, &val, addr,
- sizeof(unsigned_N))
+ unsigned_N val = H2T_N (val);
+ if (sim_core_xor_write_buffer (CPU_STATE (cpu), cpu, map, &val, addr,
+ sizeof(unsigned_N))
!= sizeof(unsigned_N))
SIM_CORE_SIGNAL (CPU_STATE (cpu), cpu, cia, map,
sizeof (unsigned_N), addr,
break;
case 'H':
- sim_print_help (sd);
+ sim_print_help (sd, is_command);
if (STATE_OPEN_KIND (sd) == SIM_OPEN_STANDALONE)
exit (0);
/* FIXME: 'twould be nice to do something similar if gdb. */
/* Print help messages for the options. */
void
-sim_print_help (sd)
+sim_print_help (sd, is_command)
SIM_DESC sd;
+ int is_command;
{
const struct option_list *ol;
const OPTION *opt;
comma = 0;
len = 2;
- o = opt;
- do
+ if (!is_command)
{
- if (o->shortopt != '\0')
+ o = opt;
+ do
{
- sim_io_printf (sd, "%s-%c", comma ? ", " : "", o->shortopt);
- len += (comma ? 2 : 0) + 2;
- if (o->arg != NULL)
+ if (o->shortopt != '\0')
{
- if (o->opt.has_arg == optional_argument)
- {
- sim_io_printf (sd, "[%s]", o->arg);
- len += 1 + strlen (o->arg) + 1;
- }
- else
+ sim_io_printf (sd, "%s-%c", comma ? ", " : "", o->shortopt);
+ len += (comma ? 2 : 0) + 2;
+ if (o->arg != NULL)
{
- sim_io_printf (sd, " %s", o->arg);
- len += 1 + strlen (o->arg);
+ if (o->opt.has_arg == optional_argument)
+ {
+ sim_io_printf (sd, "[%s]", o->arg);
+ len += 1 + strlen (o->arg) + 1;
+ }
+ else
+ {
+ sim_io_printf (sd, " %s", o->arg);
+ len += 1 + strlen (o->arg);
+ }
}
+ comma = 1;
}
- comma = 1;
+ ++o;
}
- ++o;
+ while (o->opt.name != NULL && o->doc == NULL);
}
- while (o->opt.name != NULL && o->doc == NULL);
-
+
o = opt;
do
{
name = o->opt.name;
if (name != NULL)
{
- sim_io_printf (sd, "%s--%s",
+ sim_io_printf (sd, "%s%s%s",
comma ? ", " : "",
+ is_command ? "" : "--",
name);
len += ((comma ? 2 : 0)
- + 2
+ + (is_command ? 0 : 2)
+ strlen (name));
if (o->arg != NULL)
{
typedef struct _sim_watch_point {
watchpoint_action action;
+ int is_within;
long arg;
sim_event *event;
} sim_watch_point;
+Tue May 27 14:12:32 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * igen.h: Stop options and code gen type bit masks overlaping.
+
Fri May 23 12:01:08 1997 Andrew Cagney <cagney@b1.cygnus.com>
* gen-semantics.c (print_semantic_body): Incorrect test for
--- /dev/null
+/* This file is part of the program psim.
+
+ Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+
+ */
+
+
+/* What does the instruction look like - bit ordering, size, widths or offesets */
+extern int hi_bit_nr;
+extern int insn_bit_size;
+extern int insn_specifying_widths;
+
+
+/* what should global names be prefixed with? */
+extern const char *global_name_prefix;
+extern const char *global_uname_prefix;
+
+
+/* generation options: */
+
+
+enum {
+ generate_with_direct_access = 0x1,
+ generate_with_icache = 0x2,
+ generate_with_semantic_icache = 0x4,
+ generate_with_insn_in_icache = 0x8,
+
+ generate_with_semantic_returning_modified_nia_only = 0x010,
+ generate_with_semantic_conditional_issue = 0x020,
+ generate_with_idecode_slot_verification = 0x040,
+ generate_with_semantic_delayed_branch = 0x080,
+ generate_with_semantic_zero_r0 = 0x100
+};
+
+
+typedef enum {
+
+ /* Transfer control to an instructions semantic code using the the
+ standard call/return mechanism */
+
+ generate_calls = 0x1000,
+
+
+ /* Transfer control to an instructions semantic code using
+ (computed) goto's instead of the more conventional call/return
+ mechanism */
+
+ generate_jumps = 0x2000,
+
+
+} igen_code;
+
+extern int code;
+
+
+
+
+extern int icache_size;
+
+
+/* Instruction expansion?
+
+ Should the semantic code for each instruction, when the oportunity
+ arrises, be expanded according to the variable opcode files that
+ the instruction decode process renders constant */
+
+extern int generate_expanded_instructions;
+
+
+/* SMP?
+
+ Should the generated code include SMP support (>0) and if so, for
+ how many processors? */
+
+extern int generate_smp;
+
+
+
+
+/* Misc junk */
+
+
+
+/* Function header definitions */
+
+
+/* Cache functions: */
+
+extern int print_icache_function_formal
+(lf *file);
+
+extern int print_icache_function_actual
+(lf *file);
+
+extern int print_icache_function_type
+(lf *file);
+
+extern int print_semantic_function_formal
+(lf *file);
+
+extern int print_semantic_function_actual
+(lf *file);
+
+extern int print_semantic_function_type
+(lf *file);
+
+extern void print_my_defines
+(lf *file,
+ insn_bits *expanded_bits,
+ table_entry *file_entry);
+
+extern void print_itrace
+(lf *file,
+ table_entry *file_entry,
+ int idecode);
+
+
+typedef enum {
+ function_name_prefix_semantics,
+ function_name_prefix_idecode,
+ function_name_prefix_itable,
+ function_name_prefix_icache,
+ function_name_prefix_none
+} lf_function_name_prefixes;
+
+extern int print_function_name
+(lf *file,
+ const char *basename,
+ insn_bits *expanded_bits,
+ lf_function_name_prefixes prefix);
+Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
+ mips architectures.
+
+Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * interp.c (sim_do_command): Check for common commands if a
+ simulator specific command fails.
+
Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
* interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
/* NOTE: Accessed from the GDB "sim" commmand: */
for (cptr = sim_commands; cptr && cptr->name; cptr++)
- if (strncmp(cmd,cptr->name,strlen(cptr->name)) == 0) {
- cmd += strlen(cptr->name);
- switch (cptr->id) {
- case e_help: /* no arguments */
- { /* no arguments */
- struct t_sim_command *lptr;
- callback->printf_filtered(callback,"List of MIPS simulator commands:\n");
- for (lptr = sim_commands; lptr->name; lptr++)
- callback->printf_filtered(callback,"%s %s\n",lptr->name,lptr->help);
- }
+ if (strncmp (cmd, cptr->name, strlen(cptr->name)) == 0)
+ {
+ cmd += strlen(cptr->name);
+ switch (cptr->id) {
+ case e_help: /* no arguments */
+ { /* no arguments */
+ struct t_sim_command *lptr;
+ callback->printf_filtered(callback,"List of MIPS simulator commands:\n");
+ for (lptr = sim_commands; lptr->name; lptr++)
+ callback->printf_filtered(callback,"%s %s\n",lptr->name,lptr->help);
+ sim_args_command (sd, "help");
+ }
break;
- case e_setmemsize: /* memory size argument */
- {
- unsigned int newsize = (unsigned int)getnum(cmd);
- sim_size(newsize);
- }
+ case e_setmemsize: /* memory size argument */
+ {
+ unsigned int newsize = (unsigned int)getnum(cmd);
+ sim_size(newsize);
+ }
break;
- case e_reset: /* no arguments */
- ColdReset();
- /* NOTE: See the comments in sim_open() relating to device
- initialisation. */
- break;
+ case e_reset: /* no arguments */
+ ColdReset();
+ /* NOTE: See the comments in sim_open() relating to device
+ initialisation. */
+ break;
- default:
- callback->printf_filtered(callback,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id);
- break;
- }
- break;
- }
+ default:
+ callback->printf_filtered(callback,"FATAL: Matched \"%s\", but failed to match command id %d.\n",cmd,cptr->id);
+ break;
+ }
+ break;
+ }
if (!(cptr->name))
- callback->printf_filtered(callback,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd);
+ {
+ /* try for a common command when the sim specific lookup fails */
+ if (sim_args_command (sd, cmd) != SIM_RC_OK)
+ callback->printf_filtered(callback,"Error: \"%s\" is not a valid MIPS simulator command.\n",cmd);
+ }
return;
}
/*-- co-processor support routines ------------------------------------------*/
-static int
+static int UNUSED
CoProcPresent(coproc_number)
unsigned int coproc_number;
{
+Tue May 27 13:22:13 1997 Andrew Cagney <cagney@b1.cygnus.com>
+
+ * sim-calls.c (sim_read): Pass NULL cpu to sim_core_read_buffer.
+ (sim_write): Ditto for write.
+
Tue May 20 09:33:31 1997 Andrew Cagney <cagney@b1.cygnus.com>
* sim-calls.c (sim_load): Set STATE_LOADED_P.
int
sim_read (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
{
- return sim_core_read_buffer (sd, sim_core_write_map,
+ return sim_core_read_buffer (sd, NULL, sim_core_write_map,
buf, mem, length);
}
int
sim_write (SIM_DESC sd, SIM_ADDR mem, unsigned char *buf, int length)
{
- return sim_core_write_buffer (sd, sim_core_write_map,
+ return sim_core_write_buffer (sd, NULL, sim_core_write_map,
buf, mem, length);
}
projects / thirdparty / binutils-gdb.git / commitdiff
