aarch64: Remove duplicate system register entries

There is a lot of overlap between the ETM and ETE system registers,
so some registers were listed twice.

Already tested by etm.[sd] and ete.[sd].

opcodes/
	* aarch64-opc.c (aarch64_sys_regs): Combine ETE and ETM blocks
	and remove redundant entries.

gas/
	* testsuite/gas/aarch64/etm.s: Remove duplicated test.
	* testsuite/gas/aarch64/etm.d: Update accordingly.

diff --git a/gas/testsuite/gas/aarch64/etm.d b/gas/testsuite/gas/aarch64/etm.d
index 4472b2f677e786161fca9a522805accc910247ac..ea00b868cd31dd273a0161f63732c96a13591ff2 100644 (file)
--- a/gas/testsuite/gas/aarch64/etm.d
+++ b/gas/testsuite/gas/aarch64/etm.d
@@ -90,7 +90,6 @@ Disassembly of section \.text:
 [^:]+: d5310a80        mrs     x0, trcextinselr2
 [^:]+: d5310b80        mrs     x0, trcextinselr3
 [^:]+: d53100e0        mrs     x0, trcimspec0
-[^:]+: d53100e0        mrs     x0, trcimspec0
 [^:]+: d53101e0        mrs     x0, trcimspec1
 [^:]+: d53102e0        mrs     x0, trcimspec2
 [^:]+: d53103e0        mrs     x0, trcimspec3
@@ -267,7 +266,6 @@ Disassembly of section \.text:
 [^:]+: d5110a80        msr     trcextinselr2, x0
 [^:]+: d5110b80        msr     trcextinselr3, x0
 [^:]+: d51100e0        msr     trcimspec0, x0
-[^:]+: d51100e0        msr     trcimspec0, x0
 [^:]+: d51101e0        msr     trcimspec1, x0
 [^:]+: d51102e0        msr     trcimspec2, x0
 [^:]+: d51103e0        msr     trcimspec3, x0

diff --git a/gas/testsuite/gas/aarch64/etm.s b/gas/testsuite/gas/aarch64/etm.s
index 8f1947db736429721730817c6f9a6e84d306a881..761f56a2204fabfec590b10423689d25b55d1784 100644 (file)
--- a/gas/testsuite/gas/aarch64/etm.s
+++ b/gas/testsuite/gas/aarch64/etm.s
@@ -86,7 +86,6 @@ mrs x0, trcextinselr1
 mrs x0, trcextinselr2
 mrs x0, trcextinselr3
 mrs x0, trcimspec0
-mrs x0, trcimspec0
 mrs x0, trcimspec1
 mrs x0, trcimspec2
 mrs x0, trcimspec3
@@ -265,7 +264,6 @@ msr trcextinselr1, x0
 msr trcextinselr2, x0
 msr trcextinselr3, x0
 msr trcimspec0, x0
-msr trcimspec0, x0
 msr trcimspec1, x0
 msr trcimspec2, x0
 msr trcimspec3, x0

diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index ef0ba8a68f4cd430651763492604d99f97a0dc1d..714c705ea9172d4c81b8ec26741664974f4a81ed 100644 (file)
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4486,12 +4486,6 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE("trbsr_el1",         CPENC (3,0,C9,C11,3),   0),
   SR_CORE("trbtrg_el1",        CPENC (3,0,C9,C11,6),   0),
 
-  SR_CORE ("trcextinselr0",    CPENC (2,1,C0,C8,4),    0),
-  SR_CORE ("trcextinselr1",    CPENC (2,1,C0,C9,4),    0),
-  SR_CORE ("trcextinselr2",    CPENC (2,1,C0,C10,4),   0),
-  SR_CORE ("trcextinselr3",    CPENC (2,1,C0,C11,4),   0),
-  SR_CORE ("trcrsr",           CPENC (2,1,C0,C10,0),   0),
-
   SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ),
   SR_CORE ("trccidr0",      CPENC (2,1,C7,C12,7), F_REG_READ),
   SR_CORE ("trccidr1",      CPENC (2,1,C7,C13,7), F_REG_READ),
@@ -4612,7 +4606,6 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
   SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
   SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0),
-  SR_CORE ("trcimspec0",    CPENC (2,1,C0,C0,7),  0),
   SR_CORE ("trcimspec1",    CPENC (2,1,C0,C1,7),  0),
   SR_CORE ("trcimspec2",    CPENC (2,1,C0,C2,7),  0),
   SR_CORE ("trcimspec3",    CPENC (2,1,C0,C3,7),  0),
@@ -4625,6 +4618,7 @@ const aarch64_sys_reg aarch64_sys_regs [] =
   SR_CORE ("trcprgctlr",    CPENC (2,1,C0,C1,0),  0),
   SR_CORE ("trcprocselr",   CPENC (2,1,C0,C2,0),  0),
   SR_CORE ("trcqctlr",      CPENC (2,1,C0,C1,1),  0),
+  SR_CORE ("trcrsr",        CPENC (2,1,C0,C10,0), 0),
   SR_CORE ("trcrsctlr2",    CPENC (2,1,C1,C2,0),  0),
   SR_CORE ("trcrsctlr3",    CPENC (2,1,C1,C3,0),  0),
   SR_CORE ("trcrsctlr4",    CPENC (2,1,C1,C4,0),  0),