+2016-05-31 Oleg Endo <olegendo@gcc.gnu.org>
+
+ * config/sh/constraints.md (b): Remove constraint.
+ * config/sh/predicates.md (arith_reg_operand): Remove TARGET_REGISTER_P.
+ * config/sh/sh-modes.def (PDI): Remove.
+ * config/sh/sh.c (sh_target_reg_class,
+ sh_optimize_target_register_callee_saved): Remove functions.
+ (sh_option_override): Don't set MASK_SAVE_ALL_TARGET_REGS.
+ (sh_expand_epilogue): Update comment.
+ (sh_hard_regno_mode_ok, sh_register_move_cost, calc_live_regs,
+ sh_secondary_reload): Remove TARGET_REGS related code.
+ * config/sh/sh.h (FIRST_TARGET_REG, LAST_TARGET_REG,
+ TARGET_REGISTER_P): Remove macros.
+ (SH_DBX_REGISTER_NUMBER, REG_ALLOC_ORDER): Remove target regs.
+ * config/sh/sh.md (PR_MEDIA_REG, T_MEDIA_REG, FR23_REG, TR0_REG,
+ TR1_REG, TR2_REG): Remove constants.
+ * config/sh/sh.opt (SAVE_ALL_TARGET_REGS): Remove.
+
2016-05-31 Oleg Endo <olegendo@gcc.gnu.org>
* config/sh/sh.md (adddi3, subdi3, negdi2, abs<mode>2): Remove
(define_register_constraint "a" "ALL_REGS"
"@internal")
-(define_register_constraint "b" "TARGET_REGS"
- "Branch target registers.")
-
(define_register_constraint "c" "FPSCR_REGS"
"Floating-point status register.")
return 1;
return (regno != T_REG && regno != PR_REG
- && ! TARGET_REGISTER_P (regno)
&& regno != FPUL_REG && regno != FPSCR_REG
&& regno != MACH_REG && regno != MACL_REG);
}
along with GCC; see the file COPYING3. If not see
<http://www.gnu.org/licenses/>. */
-/* PDI mode is used to represent a function address in a target register. */
-PARTIAL_INT_MODE (DI, 64, PDI);
-
/* Vector modes. */
VECTOR_MODE (INT, QI, 2); /* V2QI */
VECTOR_MODES (INT, 4); /* V4QI V2HI */
static bool sh_function_ok_for_sibcall (tree, tree);
static bool sh_can_follow_jump (const rtx_insn *, const rtx_insn *);
-static reg_class_t sh_target_reg_class (void);
-static bool sh_optimize_target_register_callee_saved (bool);
static bool sh_ms_bitfield_layout_p (const_tree);
static void sh_init_builtins (void);
#undef TARGET_CAN_FOLLOW_JUMP
#define TARGET_CAN_FOLLOW_JUMP sh_can_follow_jump
-#undef TARGET_BRANCH_TARGET_REGISTER_CLASS
-#define TARGET_BRANCH_TARGET_REGISTER_CLASS sh_target_reg_class
-#undef TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED
-#define TARGET_BRANCH_TARGET_REGISTER_CALLEE_SAVED \
- sh_optimize_target_register_callee_saved
#undef TARGET_MS_BITFIELD_LAYOUT_P
#define TARGET_MS_BITFIELD_LAYOUT_P sh_ms_bitfield_layout_p
int regno;
SUBTARGET_OVERRIDE_OPTIONS;
- if (optimize > 1 && !optimize_size)
- target_flags |= MASK_SAVE_ALL_TARGET_REGS;
sh_cpu = PROCESSOR_SH1;
assembler_dialect = 0;
if (nosave_low_regs && reg == R8_REG)
break;
}
- /* If we have a target register optimization pass after prologue / epilogue
- threading, we need to assume all target registers will be live even if
- they aren't now. */
- if (flag_branch_target_load_optimize2 && TARGET_SAVE_ALL_TARGET_REGS)
- for (reg = LAST_TARGET_REG; reg >= FIRST_TARGET_REG; reg--)
- if ((! call_really_used_regs[reg] || interrupt_handler)
- && ! TEST_HARD_REG_BIT (*live_regs_mask, reg))
- {
- SET_HARD_REG_BIT (*live_regs_mask, reg);
- count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (reg));
- }
- /* If this is an interrupt handler, we don't have any call-clobbered
- registers we can conveniently use for target register save/restore.
- Make sure we save at least one general purpose register when we need
- to save target registers. */
- if (interrupt_handler
- && hard_reg_set_intersect_p (*live_regs_mask,
- reg_class_contents[TARGET_REGS])
- && ! hard_reg_set_intersect_p (*live_regs_mask,
- reg_class_contents[GENERAL_REGS]))
- {
- SET_HARD_REG_BIT (*live_regs_mask, R0_REG);
- count += GET_MODE_SIZE (REGISTER_NATURAL_MODE (R0_REG));
- }
return count;
}
emit_insn (gen_sp_switch_2 ());
/* Tell flow the insn that pops PR isn't dead. */
- /* PR_REG will never be live in SHmedia mode, and we don't need to
- USE PR_MEDIA_REG, since it will be explicitly copied to TR0_REG
- by the return pattern. */
if (TEST_HARD_REG_BIT (live_regs_mask, PR_REG))
emit_use (gen_rtx_REG (SImode, PR_REG));
}
return 0;
}
-static reg_class_t
-sh_target_reg_class (void)
-{
- return NO_REGS;
-}
-
-static bool
-sh_optimize_target_register_callee_saved (bool after_prologue_epilogue_gen
- ATTRIBUTE_UNUSED)
-{
- return false;
-}
-
static bool
sh_ms_bitfield_layout_p (const_tree record_type ATTRIBUTE_UNUSED)
{
if (XD_REGISTER_P (regno))
return mode == DFmode;
- if (TARGET_REGISTER_P (regno))
- return (mode == DImode || mode == SImode || mode == PDImode);
-
if (regno == PR_REG)
return mode == SImode;
&& (dstclass == PR_REGS || dstclass == MAC_REGS)))
return 7;
- if ((srcclass == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
- || ((dstclass) == TARGET_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
- return 20;
-
if ((srcclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (dstclass))
|| (dstclass == FPSCR_REGS && ! REGCLASS_HAS_GENERAL_REG (srcclass)))
return 4;
return GENERAL_REGS;
return NO_REGS; // LRA wants NO_REGS here, it used to be FPUL_REGS;
}
- if (rclass == TARGET_REGS
- && !satisfies_constraint_Csy (x)
- && (!REG_P (x) || ! GENERAL_REGISTER_P (REGNO (x))))
- return GENERAL_REGS;
+
if ((rclass == MAC_REGS || rclass == PR_REGS)
&& REG_P (x) && ! GENERAL_REGISTER_P (REGNO (x))
&& rclass != REGNO_REG_CLASS (REGNO (x)))
return GENERAL_REGS;
- if (rclass != GENERAL_REGS && REG_P (x)
- && TARGET_REGISTER_P (REGNO (x)))
- return GENERAL_REGS;
/* If here fall back to loading FPUL register through general registers.
This case can happen when movsi_ie insn is picked initially to
#define LAST_FP_REG (FIRST_FP_REG + (TARGET_SH2E ? 15 : -1))
#define FIRST_XD_REG XD0_REG
#define LAST_XD_REG (FIRST_XD_REG + ((TARGET_SH4 && TARGET_FMOVD) ? 7 : -1))
-#define FIRST_TARGET_REG TR0_REG
-#define LAST_TARGET_REG (FIRST_TARGET_REG + (-1))
/* Registers that can be accessed through bank0 or bank1 depending on sr.md. */
#define FIRST_BANKED_REG R0_REG
|| (REGNO) == MACH_REG || (REGNO) == MACL_REG \
|| (REGNO) == FPSCR_MODES_REG || (REGNO) == FPSCR_STAT_REG)
-#define TARGET_REGISTER_P(REGNO) \
- ((int) (REGNO) >= FIRST_TARGET_REG && (int) (REGNO) <= LAST_TARGET_REG)
-
#define VALID_REGISTER_P(REGNO) \
(GENERAL_REGISTER_P (REGNO) || FP_REGISTER_P (REGNO) \
|| XD_REGISTER_P (REGNO) \
44, 45, 46, 47, 48, 49, 50, 51, \
52, 53, 54, 55, 56, 57, 58, 59, \
/* FPUL */ 150, \
- /* SH5 branch target registers */ \
- 128,129,130,131,132,133,134,135, \
/* Fixed registers */ \
15, 16, 24, 25, 26, 27, 63,144, \
145,146,147,148,149,152,153,154,155 }
register exists, so we should return -1 for invalid register numbers. */
#define DBX_REGISTER_NUMBER(REGNO) SH_DBX_REGISTER_NUMBER (REGNO)
-/* SHcompact PR_REG used to use the encoding 241, and SHcompact FP registers
- used to use the encodings 245..260, but that doesn't make sense:
- PR_REG and PR_MEDIA_REG are actually the same register, and likewise
- the FP registers stay the same when switching between compact and media
- mode. Hence, we also need to use the same dwarf frame columns.
- Likewise, we need to support unwind information for SHmedia registers
- even in compact code. */
#define SH_DBX_REGISTER_NUMBER(REGNO) \
(IN_RANGE ((REGNO), \
(unsigned HOST_WIDE_INT) FIRST_GENERAL_REG, \
? ((unsigned) (REGNO) - FIRST_FP_REG + 25) \
: XD_REGISTER_P (REGNO) \
? ((unsigned) (REGNO) - FIRST_XD_REG + 87) \
- : TARGET_REGISTER_P (REGNO) \
- ? ((unsigned) (REGNO) - FIRST_TARGET_REG + 68) \
: (REGNO) == PR_REG \
? (17) \
- : (REGNO) == PR_MEDIA_REG \
- ? ((unsigned) -1) \
: (REGNO) == GBR_REG \
? (18) \
: (REGNO) == MACH_REG \
(FP_REG 14)
(SP_REG 15)
- (PR_MEDIA_REG 18)
- (T_MEDIA_REG 19)
-
(R0_REG 0)
(R1_REG 1)
(R2_REG 2)
(DR0_REG 64)
(DR2_REG 66)
(DR4_REG 68)
- (FR23_REG 87)
-
- (TR0_REG 128)
- (TR1_REG 129)
- (TR2_REG 130)
(XD0_REG 136)
;; Set if compiling for SH4 hardware (to be used for insn costs etc.)
Mask(HARD_SH4)
-;; Set if we should save all target registers.
-Mask(SAVE_ALL_TARGET_REGS)
-
m1
Target RejectNegative Mask(SH1) Condition(SUPPORT_SH1)
Generate SH1 code.
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