RISC-V: Print symbol address for jalr w/ zero offset.

	ld/
	* testsuite/ld-riscv-elf/disas-jalr.d: New.
	* testsuite/ld-riscv-elf/disas-jalr.s: New.
	* testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase.

	opcodes/
	* riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
	jalr.

diff --git a/ld/ChangeLog b/ld/ChangeLog
index 97032775e9dada1fe777aaff980dea569680bdf6..8825b2e7089959c78fb297c052476c66ab95173e 100644 (file)
--- a/ld/ChangeLog
+++ b/ld/ChangeLog
@@ -1,5 +1,9 @@
 2018-01-05  Jim Wilson  <jimw@sifive.com>
 
+       * testsuite/ld-riscv-elf/disas-jalr.d: New.
+       * testsuite/ld-riscv-elf/disas-jalr.s: New.
+       * testsuite/ld-riscv-elf/ld-riscv-elf.exp: Run new testcase.
+
        * emulparams/elf32lriscv-defs.sh (GENERATE_SHLIB_SCRIPT): Move inside
        case on $target, and don't set for riscv*-elf targets.
        (GENERATE_PIE_SCRIPT): Likewise.

diff --git a/ld/testsuite/ld-riscv-elf/disas-jalr.d b/ld/testsuite/ld-riscv-elf/disas-jalr.d
new file mode 100644 (file)
index 0000000..d523e95
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/disas-jalr.d
@@ -0,0 +1,13 @@
+#name: jalr zero-offset symbols
+#source: disas-jalr.s
+#ld: --no-relax
+#objdump: -d
+
+.*:[   ]+file format .*
+
+Disassembly of section \.text:
+
+.* <_start>:
+#...
+.*:[   ]+fffff097[     ]+auipc[        ]+ra,0xfffff
+.*:[   ]+000080e7[     ]+jalr[         ]+ra # .* <_start>

diff --git a/ld/testsuite/ld-riscv-elf/disas-jalr.s b/ld/testsuite/ld-riscv-elf/disas-jalr.s
new file mode 100644 (file)
index 0000000..28ce478
--- /dev/null
+++ b/ld/testsuite/ld-riscv-elf/disas-jalr.s
@@ -0,0 +1,5 @@
+       .text
+       .globl _start
+_start:
+       .skip 4096
+       call _start

diff --git a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
index aaee4ac7bc46ff1625837ed866eacca23881f8cb..5b5d2ea004dbb8a7a1b585856d839a301d8d209a 100644 (file)
--- a/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
+++ b/ld/testsuite/ld-riscv-elf/ld-riscv-elf.exp
@@ -21,6 +21,7 @@
 
 if [istarget "riscv*-*-*"] {
     run_dump_test "c-lui"
+    run_dump_test "disas-jalr"
 
     set abis { rv32gc ilp32 elf32lriscv rv64gc lp64 elf64lriscv }
     foreach { arch abi emul } $abis {

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 076cd149fb564e4d2f03935377f2581bd148d647..fcfef762b5e4939f9ca0078883475ebdd7cf1a1a 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-01-05  Jim Wilson  <jimw@sifive.com>
+
+       * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
+       jalr.
+
 2018-01-03  Alan Modra  <amodra@gmail.com>
 
        Update year range in copyright notice of all files.

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index 972cbcfd2f38dd4e9b625193907d49202fae366d..cc427b4b935fb5c467375eb50a2f0a6f79119358 100644 (file)
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -226,6 +226,8 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 
        case 'b':
        case 's':
+         if ((l & MASK_JALR) == MATCH_JALR)
+           maybe_print_address (pd, rs1, 0);
          print (info->stream, "%s", riscv_gpr_names[rs1]);
          break;