2002-03-01 Chris Demetriou <cgd@broadcom.com>

        * mips.igen (do_divu): Fix spacing.

        * mips.igen (do_dsllv): Move to be right before DSLLV,
        to match the rest of the do_<shift> functions.

diff --git a/sim/mips/ChangeLog b/sim/mips/ChangeLog
index 95f2f36d3c8cb9f8ccd803128e6cae1b7995c714..4ffef07d97cdaace1135b7de459fa229e5b98263 100644 (file)
--- a/sim/mips/ChangeLog
+++ b/sim/mips/ChangeLog
@@ -1,3 +1,10 @@
+2002-03-01  Chris Demetriou  <cgd@broadcom.com>
+
+       * mips.igen (do_divu): Fix spacing.
+
+       * mips.igen (do_dsllv): Move to be right before DSLLV,
+       to match the rest of the do_<shift> functions.
+
 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 
        * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,

diff --git a/sim/mips/mips.igen b/sim/mips/mips.igen
index b4043116dac7b1010449afcd8a4bdb7b8d459401..b5930d58c18611a13621cc4cdecd4c15d74c9f88 100644 (file)
--- a/sim/mips/mips.igen
+++ b/sim/mips/mips.igen
@@ -1041,11 +1041,11 @@
        LO = EXTEND32 (0x80000000);
        HI = EXTEND32 (0);
       }
-   else
-     {
-       LO = EXTEND32 (n / d);
-       HI = EXTEND32 (n % d);
-     }
+    else
+      {
+       LO = EXTEND32 (n / d);
+       HI = EXTEND32 (n % d);
+      }
   }
   TRACE_ALU_RESULT2 (HI, LO);
 }
@@ -1185,15 +1185,6 @@
   TRACE_ALU_RESULT (GPR[rd]);
 }
 
-:function:::void:do_dsllv:int rs, int rt, int rd
-{
-  int s = MASKED64 (GPR[rs], 5, 0);
-  TRACE_ALU_INPUT2 (GPR[rt], s);
-  GPR[rd] = GPR[rt] << s;
-  TRACE_ALU_RESULT (GPR[rd]);
-}
-
-
 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
 "dsll r<RD>, r<RT>, <SHIFT>"
 *mipsIII:
@@ -1222,6 +1213,14 @@
   TRACE_ALU_RESULT (GPR[RD]);
 }
 
+:function:::void:do_dsllv:int rs, int rt, int rd
+{
+  int s = MASKED64 (GPR[rs], 5, 0);
+  TRACE_ALU_INPUT2 (GPR[rt], s);
+  GPR[rd] = GPR[rt] << s;
+  TRACE_ALU_RESULT (GPR[rd]);
+}
+
 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
 "dsllv r<RD>, r<RT>, r<RS>"
 *mipsIII: