aarch64: Add support for FEAT_LSCP

This patch adds the new instructions from FEAT_LSCP.
These instructions are LDAP, LDAPP and STLP.

diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0ca54c3bd40bc87c8927c9e6f1ed1fb71e2ed289..42a04c58ddbfb3bf0ef2f3c24350cea3dc53d514 100644 (file)
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -10823,6 +10823,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
   {"sha3",             AARCH64_FEATURE (SHA3), AARCH64_FEATURE (SHA2)},
   {"rng",              AARCH64_FEATURE (RNG), AARCH64_NO_FEATURES},
   {"ssbs",             AARCH64_FEATURE (SSBS), AARCH64_NO_FEATURES},
+  {"lscp",             AARCH64_FEATURE (LSCP), AARCH64_NO_FEATURES},
   {"memtag",           AARCH64_FEATURE (MEMTAG), AARCH64_NO_FEATURES},
   {"occmo",            AARCH64_FEATURE (OCCMO), AARCH64_NO_FEATURES},
   {"cmpbr",            AARCH64_FEATURE (CMPBR), AARCH64_NO_FEATURES},

diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 9683d411ce9130af0bc7243b3991b92e028816e6..caec5a5dc8a010c6f61687959c2778e876c6e56e 100644 (file)
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -239,6 +239,8 @@ automatically cause those extensions to be disabled.
  @tab Enable Limited Ordering Regions extensions.
 @item @code{ls64} @tab
  @tab Enable the 64 Byte Loads/Stores extensions.
+@item @code{lscp} @tab
+ @tab Enable the load acquire and store release pair extension.
 @item @code{lse} @tab
  @tab Enable Large System extensions.
 @item @code{lse128} @tab @code{lse}

diff --git a/gas/testsuite/gas/aarch64/lscp-warn.l b/gas/testsuite/gas/aarch64/lscp-warn.l
new file mode 100644 (file)
index 0000000..298f89f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lscp-warn.l
@@ -0,0 +1,5 @@
+.*: Assembler messages:
+.*: Warning: unpredictable load of register pair -- `ldap x0,x0,\[x0\]'
+.*: Warning: unpredictable load of register pair -- `ldap x0,x0,\[sp\]'
+.*: Warning: unpredictable load of register pair -- `ldapp x0,x0,\[x0\]'
+.*: Warning: unpredictable load of register pair -- `ldapp x0,x0,\[sp\]'

diff --git a/gas/testsuite/gas/aarch64/lscp.d b/gas/testsuite/gas/aarch64/lscp.d
new file mode 100644 (file)
index 0000000..d030769
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lscp.d
@@ -0,0 +1,27 @@
+#name: LSCP instructions
+#as: -march=armv8-a+lscp
+#objdump: -dr
+#warning_output: lscp-warn.l
+
+.*:     file format .*
+
+
+Disassembly of section .*:
+
+.* <a>:
+.*:    d9405800        ldap    x0, x0, \[x0\]
+.*:    d940581f        ldap    xzr, x0, \[x0\]
+.*:    d95f5800        ldap    x0, xzr, \[x0\]
+.*:    d9405be0        ldap    x0, x0, \[sp\]
+
+.* <b>:
+.*:    d9407800        ldapp   x0, x0, \[x0\]
+.*:    d940781f        ldapp   xzr, x0, \[x0\]
+.*:    d95f7800        ldapp   x0, xzr, \[x0\]
+.*:    d9407be0        ldapp   x0, x0, \[sp\]
+
+.* <c>:
+.*:    d9005800        stlp    x0, x0, \[x0\]
+.*:    d900581f        stlp    xzr, x0, \[x0\]
+.*:    d91f5800        stlp    x0, xzr, \[x0\]
+.*:    d9005be0        stlp    x0, x0, \[sp\]

diff --git a/gas/testsuite/gas/aarch64/lscp.s b/gas/testsuite/gas/aarch64/lscp.s
new file mode 100644 (file)
index 0000000..fa6d32f
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/lscp.s
@@ -0,0 +1,19 @@
+/* Load acquire and store release pair instructions.  */
+
+a:
+       ldap x0, x0, [x0]
+       ldap xzr, x0, [x0]
+       ldap x0, xzr, [x0]
+       ldap x0, x0, [sp]
+
+b:
+       ldapp x0, x0, [x0]
+       ldapp xzr, x0, [x0]
+       ldapp x0, xzr, [x0]
+       ldapp x0, x0, [sp]
+
+c:
+       stlp x0, x0, [x0]
+       stlp xzr, x0, [x0]
+       stlp x0, xzr, [x0]
+       stlp x0, x0, [sp]

diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 68a181c531f7ca87b60da1728c2c208fa6ff793e..5db5932b3bdc9448a1b157e15ae2ce2ff309a246 100644 (file)
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -263,6 +263,8 @@ enum aarch64_feature_bit {
   AARCH64_FEATURE_SME_TMOP,
   /* SME MOP4 instructions.  */
   AARCH64_FEATURE_SME_MOP4,
+  /* LSCP instructions.  */
+  AARCH64_FEATURE_LSCP,
 
   /* Virtual features.  These are used to gate instructions that are enabled
      by either of two (or more) sets of command line flags.  */

diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ecaea2d2fdba98a73d902cdc97466bc469787fd3..80f14b37af4926fe6187a706fa157b49818e6fe3 100644 (file)
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -10627,10 +10627,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                         {
                                           if (((word >> 21) & 0x1) == 0)
                                             {
-                                              /* 33222222222211111111110000000000
-                                                 10987654321098765432109876543210
-                                                 xx011001000xxxxxxxxx10xxxxxxxxxx.  */
-                                              return A64_OPID_19000800_stilp_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB;
+                                              if (((word >> 14) & 0x1) == 0)
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xx011001000xxxxxx0xx10xxxxxxxxxx.  */
+                                                  return A64_OPID_19000800_stilp_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB;
+                                                }
+                                              else
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xx011001000xxxxxx1xx10xxxxxxxxxx.  */
+                                                  return A64_OPID_d9005800_stlp_Rt_Rs_ADDR_SIMPLE;
+                                                }
                                             }
                                           else
                                             {
@@ -11084,10 +11094,30 @@ aarch64_opcode_lookup_1 (uint32_t word)
                                         {
                                           if (((word >> 21) & 0x1) == 0)
                                             {
-                                              /* 33222222222211111111110000000000
-                                                 10987654321098765432109876543210
-                                                 xx011001010xxxxxxxxx10xxxxxxxxxx.  */
-                                              return A64_OPID_19400800_ldiapp_Rt_Rs_RCPC3_ADDR_OPT_POSTIND;
+                                              if (((word >> 13) & 0x1) == 0)
+                                                {
+                                                  if (((word >> 14) & 0x1) == 0)
+                                                    {
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         xx011001010xxxxxx00x10xxxxxxxxxx.  */
+                                                      return A64_OPID_19400800_ldiapp_Rt_Rs_RCPC3_ADDR_OPT_POSTIND;
+                                                    }
+                                                  else
+                                                    {
+                                                      /* 33222222222211111111110000000000
+                                                         10987654321098765432109876543210
+                                                         xx011001010xxxxxx10x10xxxxxxxxxx.  */
+                                                      return A64_OPID_d9405800_ldap_Rt_Rs_ADDR_SIMPLE;
+                                                    }
+                                                }
+                                              else
+                                                {
+                                                  /* 33222222222211111111110000000000
+                                                     10987654321098765432109876543210
+                                                     xx011001010xxxxxxx1x10xxxxxxxxxx.  */
+                                                  return A64_OPID_d9407800_ldapp_Rt_Rs_ADDR_SIMPLE;
+                                                }
                                             }
                                           else
                                             {

diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index 1263f1f9bd8da85305696d009e7804948a8aecc5..c254440f323be49c2d58efebbfeb505b12f1369f 100644 (file)
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -1057,6 +1057,9 @@ enum aarch64_opcode_idx
   A64_OPID_889f7c00_stllr_Rt_ADDR_SIMPLE,
   A64_OPID_089f7c00_stllrb_Rt_ADDR_SIMPLE,
   A64_OPID_489f7c00_stllrh_Rt_ADDR_SIMPLE,
+  A64_OPID_d9405800_ldap_Rt_Rs_ADDR_SIMPLE,
+  A64_OPID_d9407800_ldapp_Rt_Rs_ADDR_SIMPLE,
+  A64_OPID_d9005800_stlp_Rt_Rs_ADDR_SIMPLE,
   A64_OPID_28000000_stnp_Rt_Rt2_ADDR_SIMM7,
   A64_OPID_28400000_ldnp_Rt_Rt2_ADDR_SIMM7,
   A64_OPID_2c000000_stnp_Ft_Ft2_ADDR_SIMM7,

diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2fc69c27791b1249bcff6f20bd468ae878044e09..3b14b6863c657cd8c055a8aa6a9457ba40807cf4 100644 (file)
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -2917,6 +2917,8 @@ static const aarch64_feature_set aarch64_feature_v8r =
   AARCH64_FEATURE (V8R);
 static const aarch64_feature_set aarch64_feature_ls64 =
   AARCH64_FEATURE (LS64);
+static const aarch64_feature_set aarch64_feature_lscp =
+  AARCH64_FEATURE (LSCP);
 static const aarch64_feature_set aarch64_feature_flagm =
   AARCH64_FEATURE (FLAGM);
 static const aarch64_feature_set aarch64_feature_xs =
@@ -3111,6 +3113,7 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
 #define I8MM      &aarch64_feature_i8mm
 #define ARMV8R   &aarch64_feature_v8r
 #define LS64     &aarch64_feature_ls64
+#define LSCP     &aarch64_feature_lscp
 #define FLAGM    &aarch64_feature_flagm
 #define XS       &aarch64_feature_xs
 #define WFXT     &aarch64_feature_wfxt
@@ -3363,6 +3366,8 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
   { NAME, OPCODE, MASK, CLASS, 0, WFXT, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define _LS64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, LS64, OPS, QUALS, FLAGS, 0, 0, NULL }
+#define _LSCP_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
+  { NAME, OPCODE, MASK, CLASS, 0, LSCP, OPS, QUALS, FLAGS, 0, 0, NULL }
 #define FLAGM_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS) \
   { NAME, OPCODE, MASK, CLASS, 0, FLAGM, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
 #define MOPS_INSN(NAME, OPCODE, MASK, CLASS, OPS, QUALS, FLAGS, CONSTRAINTS, VERIFIER) \
@@ -4658,6 +4663,10 @@ const struct aarch64_opcode aarch64_opcode_table[] =
   _LOR_INSN ("stllr",  0x889f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_R1NIL,       F_GPRSIZE_IN_Q),
   _LOR_INSN ("stllrb", 0x089f7c00, 0xffe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
   _LOR_INSN ("stllrh", 0x489f7c00, 0xbfe08000, ldstexcl, OP2 (Rt, ADDR_SIMPLE), QL_W1_LDST_EXC, 0),
+  /* Load acquire and store release pair.  */
+  _LSCP_INSN ("ldap", 0xd9405800, 0xffe0fc00, ldstpair_off, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, F_LDST_LOAD),
+  _LSCP_INSN ("ldapp", 0xd9407800, 0xffe0fc00, ldstpair_off, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, F_LDST_LOAD),
+  _LSCP_INSN ("stlp", 0xd9005800, 0xffe0fc00, ldstpair_off, OP3 (Rt, Rs, ADDR_SIMPLE), QL_X2NIL, F_LDST_STORE),
   /* Load/store no-allocate pair (offset).  */
   CORE_INSN ("stnp", 0x28000000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_STORE | F_SF),
   CORE_INSN ("ldnp", 0x28400000, 0x7fc00000, ldstnapair_offs, 0, OP3 (Rt, Rt2, ADDR_SIMM7), QL_LDST_PAIR_R, F_LDST_LOAD | F_SF),