* ld-mips-elf/mips16-call-global-2.s,

	ld-mips-elf/mips16-call-global-3.s, ld-mips-elf/mips16-call-global.d:
	Improve test robustness.

diff --git a/ld/testsuite/ChangeLog b/ld/testsuite/ChangeLog
index 466a20c5fc84aeb5c589124ad16f09eb50ed56f2..ca1c4f4f76d78ee07a834f7011712b92cf11159d 100644 (file)
--- a/ld/testsuite/ChangeLog
+++ b/ld/testsuite/ChangeLog
@@ -1,3 +1,9 @@
+2006-07-25  Thiemo Seufer  <ths@mips.com>
+
+       * ld-mips-elf/mips16-call-global-2.s,
+       ld-mips-elf/mips16-call-global-3.s, ld-mips-elf/mips16-call-global.d:
+       Improve test robustness.
+
 2006-07-21  Nick Clifton  <nickc@redhat.com>
 
        * ld-sh/arch/arch.exp (test_arch): Set the endian flag to suit the

diff --git a/ld/testsuite/ld-mips-elf/mips16-call-global-2.s b/ld/testsuite/ld-mips-elf/mips16-call-global-2.s
index bae3195799cb13676fbe00c9e3aa5dccce959fc6..2843fcd6ecd40690cb72c75f7a0b9c7865e65c9b 100644 (file)
--- a/ld/testsuite/ld-mips-elf/mips16-call-global-2.s
+++ b/ld/testsuite/ld-mips-elf/mips16-call-global-2.s
@@ -1,4 +1,4 @@
-       .set mips16
+       .set    mips16
 
        .globl  x
        .ent    x

diff --git a/ld/testsuite/ld-mips-elf/mips16-call-global-3.s b/ld/testsuite/ld-mips-elf/mips16-call-global-3.s
index e776b3d548ef247aa10aa72738870b27e1944b80..5113c5d44a946f1d751c0d92059b8e8d9c3cf02a 100644 (file)
--- a/ld/testsuite/ld-mips-elf/mips16-call-global-3.s
+++ b/ld/testsuite/ld-mips-elf/mips16-call-global-3.s
@@ -1,6 +1,16 @@
+       .set    nomips16
+
        .globl  y
        .ent    y
        .type   y,@function
 y:
        jr      $31
        .end    y
+
+       .ent    z
+       .type   z,@function
+z:
+       jr      $31
+       .end    z
+
+       .space 8

diff --git a/ld/testsuite/ld-mips-elf/mips16-call-global.d b/ld/testsuite/ld-mips-elf/mips16-call-global.d
index bd5095e66dcfb8638a0c0664bdf57021e14f62f1..051ebcdae8b24d72bf9844a21580b878960d1e6d 100644 (file)
--- a/ld/testsuite/ld-mips-elf/mips16-call-global.d
+++ b/ld/testsuite/ld-mips-elf/mips16-call-global.d
@@ -1,37 +1,39 @@
-#as: -mips32r2
-#source: mips16-call-global-1.S mips16-call-global-2.S mips16-call-global-3.S
 
 .*:     file format elf.*mips
 
 Disassembly of section .text:
 
-00400090 <__start>:
-  400090:      64c3            save    24,ra
-  400092:      1a00 002e       jal     4000b8 <x\+0x8>
-  400096:      6500            nop
-  400098:      1e00 0032       jalx    4000c8 <y\+0x8>
-  40009c:      6500            nop
-  40009e:      6443            restore 24,ra
-  4000a0:      e8a0            jrc     ra
-  4000a2:      6500            nop
-  4000a4:      6500            nop
-  4000a6:      6500            nop
-  4000a8:      6500            nop
-  4000aa:      6500            nop
-  4000ac:      6500            nop
-  4000ae:      6500            nop
+.*0090 <__start>:
+.*0090:        64c3            save    24,ra
+.*0092:        1a00 002e       jal     .*00b8 <x\+0x8>
+.*0096:        6500            nop
+.*0098:        1e00 0032       jalx    .*00c8 <z>
+.*009c:        6500            nop
+.*009e:        6443            restore 24,ra
+.*00a0:        e8a0            jrc     ra
+.*00a2:        6500            nop
+.*00a4:        6500            nop
+.*00a6:        6500            nop
+.*00a8:        6500            nop
+.*00aa:        6500            nop
+.*00ac:        6500            nop
+.*00ae:        6500            nop
 
-004000b0 <x>:
-  4000b0:      e8a0            jrc     ra
-  4000b2:      6500            nop
-  4000b4:      6500            nop
-  4000b6:      6500            nop
-  4000b8:      6500            nop
-  4000ba:      6500            nop
-  4000bc:      6500            nop
-  4000be:      6500            nop
+.*00b0 <x>:
+.*00b0:        e8a0            jrc     ra
+.*00b2:        6500            nop
+.*00b4:        6500            nop
+.*00b6:        6500            nop
+.*00b8:        6500            nop
+.*00ba:        6500            nop
+.*00bc:        6500            nop
+.*00be:        6500            nop
 
-004000c0 <y>:
-  4000c0:      03e00008        jr      ra
-  4000c4:      00000000        nop
+.*00c0 <y>:
+.*00c0:        03e00008        jr      ra
+.*00c4:        00000000        nop
+
+.*00c8 <z>:
+.*00c8:        03e00008        jr      ra
+.*00cc:        00000000        nop
        \.\.\.