x86/Intel: accept "oword ptr" for INVPCID

The insn is no different in this reagrd from INVEPT and INVVPID.

diff --git a/gas/ChangeLog b/gas/ChangeLog
index 93dc1c7e02615c1bc3ee21efc7a44a402ecb54c4..14f03bc8107ce8c00cdbe8745106d0e2d71e999a 100644 (file)
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,13 @@
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       *  testsuite/gas/i386/invpcid.s,
+       testsuite/gas/i386/x86-64-invpcid.s: Add test with explicit
+       "oword ptr".
+       * testsuite/gas/i386/invpcid.d,
+       testsuite/gas/i386/invpcid-intel.d,
+       testsuite/gas/i386/x86-64-invpcid.d,
+       testsuite/gas/i386/x86-64-invpcid-intel.d: Adjust expectations.
+
 2018-05-30  Amit Pawar  <amit.pawar@amd.com>
 
        * config/tc-i386.c (cpu_flag_init): Add CPU_ZNVER2_FLAGS.

diff --git a/gas/testsuite/gas/i386/invpcid-intel.d b/gas/testsuite/gas/i386/invpcid-intel.d
index f0b4dc9111a14538a6d0b3954479079a37e069b9..8d1b5a97bf284ff9caca6398fa6d07add8eef92f 100644 (file)
--- a/gas/testsuite/gas/i386/invpcid-intel.d
+++ b/gas/testsuite/gas/i386/invpcid-intel.d
@@ -11,4 +11,5 @@ Disassembly of section .text:
 0+ <foo>:
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid edx,\[eax\]
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid edx,\[eax\]
+[      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid edx,\[eax\]
 #pass

diff --git a/gas/testsuite/gas/i386/invpcid.d b/gas/testsuite/gas/i386/invpcid.d
index 3ebd2026b2c8ee75e705eb2151907963dbfb6334..3619e59ac4ac0abdaf2a4ae1427272d3d98c218e 100644 (file)
--- a/gas/testsuite/gas/i386/invpcid.d
+++ b/gas/testsuite/gas/i386/invpcid.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <foo>:
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid \(%eax\),%edx
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid \(%eax\),%edx
+[      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid \(%eax\),%edx
 #pass

diff --git a/gas/testsuite/gas/i386/invpcid.s b/gas/testsuite/gas/i386/invpcid.s
index 9f127316a5c9555e5301eb268f8a099dd8aef3bd..32067cb839975f6dc906d8256cbf154ea3798de9 100644 (file)
--- a/gas/testsuite/gas/i386/invpcid.s
+++ b/gas/testsuite/gas/i386/invpcid.s
@@ -6,3 +6,4 @@ foo:
 
        .intel_syntax noprefix
        invpcid edx,[eax]
+       invpcid edx,oword ptr [eax]

diff --git a/gas/testsuite/gas/i386/x86-64-invpcid-intel.d b/gas/testsuite/gas/i386/x86-64-invpcid-intel.d
index 35dc9e9c60d279ef7d6750d5d7495f363c2e4d6b..94a78617edfadf24881535306e30527cc5709a89 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-invpcid-intel.d
+++ b/gas/testsuite/gas/i386/x86-64-invpcid-intel.d
@@ -11,4 +11,5 @@ Disassembly of section .text:
 0+ <foo>:
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid rdx,\[rax\]
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid rdx,\[rax\]
+[      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid rdx,\[rax\]
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-invpcid.d b/gas/testsuite/gas/i386/x86-64-invpcid.d
index af0fc4ad0184cd28ec9e34af7c7314bf997bb7e8..7a3101aacbef3e0425e2010a56c715f88745477a 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-invpcid.d
+++ b/gas/testsuite/gas/i386/x86-64-invpcid.d
@@ -10,4 +10,5 @@ Disassembly of section .text:
 0+ <foo>:
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid \(%rax\),%rdx
 [      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid \(%rax\),%rdx
+[      ]*[a-f0-9]+:    66 0f 38 82 10          invpcid \(%rax\),%rdx
 #pass

diff --git a/gas/testsuite/gas/i386/x86-64-invpcid.s b/gas/testsuite/gas/i386/x86-64-invpcid.s
index 89dd2114e0716b23f3226351e1ed0d824a24e553..5db90af7d712a860df85e7a6d8733a4d3f73a237 100644 (file)
--- a/gas/testsuite/gas/i386/x86-64-invpcid.s
+++ b/gas/testsuite/gas/i386/x86-64-invpcid.s
@@ -6,3 +6,4 @@ foo:
 
        .intel_syntax noprefix
        invpcid rdx,[rax]
+       invpcid rdx,oword ptr [rax]

diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 725bf15358589491c50b3fe5797928e85e59fc63..3cc3f99a8cf93b8712ec8ff32ac116691c36357e 100644 (file)
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,8 @@
+2018-06-01  Jan Beulich  <jbeulich@suse.com>
+
+       * i386-opc.tbl (invpcid): Add Oword.
+       * i386-tbl.h: Re-generate.
+
 2018-06-01  Alan Modra  <amodra@gmail.com>
 
        * sysdep.h (_bfd_error_handler): Don't declare.

diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 201586cbccdbd5b8b4e92d554260f44f66922801..fe2e626e70af7f701cafe15d5c8aba4fa372df7d 100644 (file)
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -1583,8 +1583,8 @@ invvpid, 2, 0x660f3881, None, 3, CpuEPT|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|
 
 // INVPCID instruction
 
-invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Unspecified|BaseIndex, Reg32 }
-invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Unspecified|BaseIndex, Reg64 }
+invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|CpuNo64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf, { Oword|Unspecified|BaseIndex, Reg32 }
+invpcid, 2, 0x660f3882, None, 3, CpuINVPCID|Cpu64, Modrm|No_bSuf|No_wSuf|No_lSuf|No_qSuf|No_sSuf|No_ldSuf|NoRex64, { Oword|Unspecified|BaseIndex, Reg64 }
 
 // SSSE3 instructions.
 

diff --git a/opcodes/i386-tbl.h b/opcodes/i386-tbl.h
index 23643fcb525f2781230fc4009eb61a2a4b6361f7..78eef83823c51dd16715067644a5df4acfa36744 100644 (file)
--- a/opcodes/i386-tbl.h
+++ b/opcodes/i386-tbl.h
@@ -20804,12 +20804,12 @@ const insn_template i386_optab[] =
         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 1, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 0,
-         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
          0, 0, 0 } },
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0,
@@ -20821,12 +20821,12 @@ const insn_template i386_optab[] =
         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
         0, 0, 1, 0, 0 } },
-    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1,
+    { 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1,
       1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0,
       0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
       0, 0 },
     { { { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 1, 1,
-         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0,
+         0, 0, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 0,
          0, 0, 0 } },
       { { 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
          0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0,